MipsMSAInstrInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips MSA ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 49def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 50def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 51def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 52def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 53def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 54def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 55def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 56def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 57 58def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 59def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 60 61def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 63def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 65 66// Operands 67 68def uimm2 : Operand<i32> { 69 let PrintMethod = "printUnsignedImm"; 70} 71 72// The immediate of an LSA instruction needs special handling 73// as the encoded value should be subtracted by one. 74def uimm2LSAAsmOperand : AsmOperandClass { 75 let Name = "LSAImm"; 76 let ParserMethod = "ParseLSAImm"; 77 let RenderMethod = "addImmOperands"; 78} 79 80def LSAImm : Operand<i32> { 81 let PrintMethod = "printUnsignedImm"; 82 let EncoderMethod = "getLSAImmEncoding"; 83 let DecoderMethod = "DecodeLSAImm"; 84 let ParserMatchClass = uimm2LSAAsmOperand; 85} 86 87def uimm3 : Operand<i32> { 88 let PrintMethod = "printUnsignedImm8"; 89} 90 91def uimm4 : Operand<i32> { 92 let PrintMethod = "printUnsignedImm8"; 93} 94 95def uimm8 : Operand<i32> { 96 let PrintMethod = "printUnsignedImm8"; 97} 98 99def simm5 : Operand<i32>; 100 101def vsplat_uimm1 : Operand<vAny> { 102 let PrintMethod = "printUnsignedImm8"; 103} 104 105def vsplat_uimm2 : Operand<vAny> { 106 let PrintMethod = "printUnsignedImm8"; 107} 108 109def vsplat_uimm3 : Operand<vAny> { 110 let PrintMethod = "printUnsignedImm8"; 111} 112 113def vsplat_uimm4 : Operand<vAny> { 114 let PrintMethod = "printUnsignedImm8"; 115} 116 117def vsplat_uimm5 : Operand<vAny> { 118 let PrintMethod = "printUnsignedImm8"; 119} 120 121def vsplat_uimm6 : Operand<vAny> { 122 let PrintMethod = "printUnsignedImm8"; 123} 124 125def vsplat_uimm8 : Operand<vAny> { 126 let PrintMethod = "printUnsignedImm8"; 127} 128 129def vsplat_simm5 : Operand<vAny>; 130 131def vsplat_simm10 : Operand<vAny>; 132 133def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 134 135// Pattern fragments 136def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 137 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 138def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 139 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 140def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 141 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 142def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 143 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 144 145def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 146 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 147def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 148 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 149def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 150 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 151def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 152 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 153 154def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 155 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 156def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 157 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 158def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 159 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 160def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 161 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 162 163def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 164 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 165def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 166 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 167def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 168 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 169def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 170 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 171 172class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 173 PatFrag<(ops node:$lhs, node:$rhs), 174 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 175 176// ISD::SETFALSE cannot occur 177def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 178def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 179def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 180def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 181def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 182def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 183def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 184def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 185def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 186def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 187def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 188def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 189def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 190def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 191def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 192def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 193def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 194def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 195def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 196def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 197def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 198def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 199def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 200def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 201def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 202def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 203def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 204def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 205// ISD::SETTRUE cannot occur 206// ISD::SETFALSE2 cannot occur 207// ISD::SETTRUE2 cannot occur 208 209class vsetcc_type<ValueType ResTy, CondCode CC> : 210 PatFrag<(ops node:$lhs, node:$rhs), 211 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 212 213def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 214def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 215def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 216def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 217def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 218def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 219def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 220def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 221def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 222def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 223def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 224def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 225def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 226def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 227def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 228def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 229def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 230def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 231def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 232def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 233 234def vsplati8 : PatFrag<(ops node:$e0), 235 (v16i8 (build_vector node:$e0, node:$e0, 236 node:$e0, node:$e0, 237 node:$e0, node:$e0, 238 node:$e0, node:$e0, 239 node:$e0, node:$e0, 240 node:$e0, node:$e0, 241 node:$e0, node:$e0, 242 node:$e0, node:$e0))>; 243def vsplati16 : PatFrag<(ops node:$e0), 244 (v8i16 (build_vector node:$e0, node:$e0, 245 node:$e0, node:$e0, 246 node:$e0, node:$e0, 247 node:$e0, node:$e0))>; 248def vsplati32 : PatFrag<(ops node:$e0), 249 (v4i32 (build_vector node:$e0, node:$e0, 250 node:$e0, node:$e0))>; 251def vsplati64 : PatFrag<(ops node:$e0), 252 (v2i64 (build_vector node:$e0, node:$e0))>; 253def vsplatf32 : PatFrag<(ops node:$e0), 254 (v4f32 (build_vector node:$e0, node:$e0, 255 node:$e0, node:$e0))>; 256def vsplatf64 : PatFrag<(ops node:$e0), 257 (v2f64 (build_vector node:$e0, node:$e0))>; 258 259def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 260 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 261def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 262 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 263def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 264 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 265def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 266 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; 267 268class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 269 SDNodeXForm xform = NOOP_SDNodeXForm> 270 : PatLeaf<frag, pred, xform> { 271 Operand OpClass = opclass; 272} 273 274class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 275 list<SDNode> roots = [], 276 list<SDNodeProperty> props = []> : 277 ComplexPattern<ty, numops, fn, roots, props> { 278 Operand OpClass = opclass; 279} 280 281def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 282 "selectVSplatUimm3", 283 [build_vector, bitconvert]>; 284 285def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 286 "selectVSplatUimm4", 287 [build_vector, bitconvert]>; 288 289def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 290 "selectVSplatUimm5", 291 [build_vector, bitconvert]>; 292 293def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 294 "selectVSplatUimm8", 295 [build_vector, bitconvert]>; 296 297def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 298 "selectVSplatSimm5", 299 [build_vector, bitconvert]>; 300 301def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 302 "selectVSplatUimm3", 303 [build_vector, bitconvert]>; 304 305def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 306 "selectVSplatUimm4", 307 [build_vector, bitconvert]>; 308 309def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 310 "selectVSplatUimm5", 311 [build_vector, bitconvert]>; 312 313def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 314 "selectVSplatSimm5", 315 [build_vector, bitconvert]>; 316 317def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 318 "selectVSplatUimm2", 319 [build_vector, bitconvert]>; 320 321def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 322 "selectVSplatUimm5", 323 [build_vector, bitconvert]>; 324 325def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 326 "selectVSplatSimm5", 327 [build_vector, bitconvert]>; 328 329def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 330 "selectVSplatUimm1", 331 [build_vector, bitconvert]>; 332 333def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 334 "selectVSplatUimm5", 335 [build_vector, bitconvert]>; 336 337def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 338 "selectVSplatUimm6", 339 [build_vector, bitconvert]>; 340 341def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 342 "selectVSplatSimm5", 343 [build_vector, bitconvert]>; 344 345// Any build_vector that is a constant splat with a value that is an exact 346// power of 2 347def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 348 [build_vector, bitconvert]>; 349 350// Any build_vector that is a constant splat with a value that is the bitwise 351// inverse of an exact power of 2 352def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 353 [build_vector, bitconvert]>; 354 355// Any build_vector that is a constant splat with only a consecutive sequence 356// of left-most bits set. 357def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 358 "selectVSplatMaskL", 359 [build_vector, bitconvert]>; 360 361// Any build_vector that is a constant splat with only a consecutive sequence 362// of right-most bits set. 363def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 364 "selectVSplatMaskR", 365 [build_vector, bitconvert]>; 366 367// Any build_vector that is a constant splat with a value that equals 1 368// FIXME: These should be a ComplexPattern but we can't use them because the 369// ISel generator requires the uses to have a name, but providing a name 370// causes other errors ("used in pattern but not operand list") 371def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 372 APInt Imm; 373 EVT EltTy = N->getValueType(0).getVectorElementType(); 374 375 return selectVSplat (N, Imm) && 376 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 377}]>; 378 379def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 380 APInt Imm; 381 SDNode *BV = N->getOperand(0).getNode(); 382 EVT EltTy = N->getValueType(0).getVectorElementType(); 383 384 return selectVSplat (BV, Imm) && 385 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 386}]>; 387 388def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 389 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 390 immAllOnesV))>; 391def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 392 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 393 immAllOnesV))>; 394def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 395 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 396 immAllOnesV))>; 397def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 398 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 399 node:$wt), 400 (bitconvert (v4i32 immAllOnesV))))>; 401 402def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 403 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 404def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 405 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 406def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 407 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 408def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 409 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 410 node:$wt))>; 411 412def vbset_b : PatFrag<(ops node:$ws, node:$wt), 413 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 414def vbset_h : PatFrag<(ops node:$ws, node:$wt), 415 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 416def vbset_w : PatFrag<(ops node:$ws, node:$wt), 417 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 418def vbset_d : PatFrag<(ops node:$ws, node:$wt), 419 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 420 node:$wt))>; 421 422def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), 423 (fsub node:$wd, (fmul node:$ws, node:$wt))>; 424 425def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 426 (add node:$wd, (mul node:$ws, node:$wt))>; 427 428def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 429 (sub node:$wd, (mul node:$ws, node:$wt))>; 430 431def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 432 (fmul node:$ws, (fexp2 node:$wt))>; 433 434// Immediates 435def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>; 436def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>; 437 438// Instruction encoding. 439class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 440class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 441class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 442class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 443 444class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 445class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 446class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 447class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 448 449class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 450class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 451class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 452class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 453 454class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 455class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 456class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 457class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 458 459class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 460class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 461class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 462class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 463 464class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 465class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 466class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 467class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 468 469class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 470 471class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 472 473class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 474class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 475class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 476class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 477 478class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 479class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 480class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 481class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 482 483class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 484class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 485class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 486class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 487 488class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 489class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 490class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 491class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 492 493class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 494class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 495class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 496class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 497 498class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 499class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 500class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 501class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 502 503class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 504class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 505class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 506class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 507 508class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 509class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 510class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 511class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 512 513class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 514class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 515class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 516class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 517 518class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 519class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 520class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 521class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 522 523class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 524class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 525class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 526class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 527 528class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 529class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 530class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 531class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 532 533class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 534 535class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 536 537class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 538 539class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 540 541class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 542class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 543class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 544class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 545 546class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 547class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 548class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 549class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 550 551class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 552class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 553class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 554class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 555 556class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 557 558class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 559 560class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 561 562class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 563class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 564class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 565class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 566 567class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 568class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 569class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 570class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 571 572class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 573class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 574class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 575class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 576 577class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 578 579class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 580class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 581class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 582class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 583 584class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 585class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 586class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 587class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 588 589class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 590 591class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 592class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 593class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 594class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 595 596class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 597class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 598class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 599class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 600 601class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 602class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 603class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 604class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 605 606class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 607class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 608class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 609class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 610 611class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 612class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 613class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 614class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 615 616class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 617class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 618class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 619class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 620 621class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 622class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 623class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 624class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 625 626class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 627class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 628class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 629class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 630 631class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 632class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 633class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 634class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 635 636class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 637class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 638class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 639class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>; 640 641class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 642 643class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 644class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 645class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 646class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 647 648class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 649class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 650class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 651class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 652 653class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 654class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 655class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 656 657class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 658class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 659class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 660 661class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 662class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 663class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 664 665class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 666class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 667class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 668 669class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 670class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 671class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 672 673class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 674class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 675class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 676 677class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 678class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 679 680class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 681class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 682 683class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 684class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 685 686class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 687class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 688 689class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 690class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 691 692class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 693class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 694 695class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 696class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 697 698class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 699class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 700 701class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 702class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 703 704class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 705class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 706 707class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 708class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 709 710class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 711class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 712 713class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 714class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 715 716class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 717class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 718 719class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 720class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 721 722class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 723class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 724 725class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 726class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 727 728class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 729class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 730 731class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 732class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 733 734class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 735class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 736 737class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 738class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 739 740class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 741class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 742 743class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 744class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 745class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 746class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 747 748class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 749class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 750 751class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 752class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 753 754class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 755class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 756 757class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 758class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 759 760class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 761class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 762 763class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 764class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 765 766class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 767class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 768 769class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 770class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 771 772class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 773class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 774 775class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 776class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 777 778class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 779class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 780 781class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 782class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 783 784class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 785class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 786 787class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 788class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 789 790class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 791class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 792 793class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 794class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 795 796class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 797class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 798 799class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 800class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 801 802class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 803class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 804 805class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 806class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 807 808class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 809class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 810 811class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 812class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 813 814class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 815class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 816 817class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 818class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 819 820class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 821class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 822 823class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 824class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 825 826class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 827class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 828 829class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 830class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 831 832class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 833class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 834 835class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 836class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 837class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 838 839class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 840class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 841class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 842 843class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 844class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 845class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 846 847class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 848class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 849class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 850 851class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 852class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 853class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 854class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 855 856class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 857class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 858class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 859class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 860 861class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 862class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 863class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 864class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 865 866class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 867class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 868class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 869class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 870 871class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 872class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 873class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 874class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 875 876class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 877class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 878class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 879class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 880 881class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 882class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 883class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 884class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 885 886class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 887class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 888class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 889class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 890 891class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 892class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 893 894class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 895class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 896 897class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 898class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 899 900class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 901class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 902class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 903class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 904 905class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 906class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 907class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 908class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 909 910class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 911class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 912class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 913class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 914 915class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 916class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 917class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 918class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 919 920class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 921class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 922class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 923class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 924 925class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 926class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 927class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 928class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 929 930class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 931class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 932class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 933class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 934 935class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 936class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 937class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 938class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 939 940class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 941class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 942class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 943class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 944 945class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 946class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 947class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 948class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 949 950class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 951class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 952class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 953class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 954 955class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 956class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 957class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 958class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 959 960class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 961class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 962class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 963class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 964 965class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 966 967class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 968class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 969 970class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 971class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 972 973class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 974class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 975class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 976class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 977 978class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 979class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 980 981class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 982class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 983 984class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 985class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 986class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 987class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 988 989class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 990class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 991class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 992class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 993 994class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 995class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 996class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 997class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 998 999class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 1000 1001class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 1002 1003class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 1004 1005class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 1006 1007class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 1008class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 1009class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 1010class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 1011 1012class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 1013class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 1014class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 1015class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 1016 1017class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 1018class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 1019class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 1020class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 1021 1022class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 1023class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 1024class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 1025class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 1026 1027class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 1028class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 1029class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 1030class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 1031 1032class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1033class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1034class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1035 1036class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1037class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1038class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1039class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1040 1041class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1042class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1043class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1044class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1045 1046class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1047class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1048class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1049class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1050 1051class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1052class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1053class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1054class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1055 1056class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1057class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1058class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1059class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1060 1061class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1062class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1063class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1064class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1065 1066class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1067class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1068class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1069class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1070 1071class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1072class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1073class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1074class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1075 1076class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1077class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1078class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1079class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1080 1081class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1082class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1083class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1084class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1085 1086class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1087class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1088class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1089class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1090 1091class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1092class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1093class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1094class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1095 1096class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1097class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1098class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1099class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1100 1101class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1102class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1103class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1104class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1105 1106class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1107class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1108class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1109class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1110 1111class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1112class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1113class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1114class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1115 1116class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1117class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1118class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1119class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1120 1121class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1122class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1123class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1124class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1125 1126class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1127class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1128class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1129class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1130 1131class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1132class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1133class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1134class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1135 1136class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1137class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1138class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1139class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1140 1141class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1142class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1143class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1144class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1145 1146class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1147 1148class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1149 1150// Instruction desc. 1151class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1152 ComplexPattern Imm, RegisterOperand ROWD, 1153 RegisterOperand ROWS = ROWD, 1154 InstrItinClass itin = NoItinerary> { 1155 dag OutOperandList = (outs ROWD:$wd); 1156 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1157 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1158 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1159 InstrItinClass Itinerary = itin; 1160} 1161 1162class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1163 ComplexPattern Imm, RegisterOperand ROWD, 1164 RegisterOperand ROWS = ROWD, 1165 InstrItinClass itin = NoItinerary> { 1166 dag OutOperandList = (outs ROWD:$wd); 1167 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1168 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1169 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1170 InstrItinClass Itinerary = itin; 1171} 1172 1173class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1174 ComplexPattern Imm, RegisterOperand ROWD, 1175 RegisterOperand ROWS = ROWD, 1176 InstrItinClass itin = NoItinerary> { 1177 dag OutOperandList = (outs ROWD:$wd); 1178 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1179 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1180 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1181 InstrItinClass Itinerary = itin; 1182} 1183 1184class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1185 ComplexPattern Imm, RegisterOperand ROWD, 1186 RegisterOperand ROWS = ROWD, 1187 InstrItinClass itin = NoItinerary> { 1188 dag OutOperandList = (outs ROWD:$wd); 1189 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1190 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1191 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1192 InstrItinClass Itinerary = itin; 1193} 1194 1195// This class is deprecated and will be removed soon. 1196class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1197 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1198 InstrItinClass itin = NoItinerary> { 1199 dag OutOperandList = (outs ROWD:$wd); 1200 dag InOperandList = (ins ROWS:$ws, uimm3:$m); 1201 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1202 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))]; 1203 InstrItinClass Itinerary = itin; 1204} 1205 1206// This class is deprecated and will be removed soon. 1207class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1208 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1209 InstrItinClass itin = NoItinerary> { 1210 dag OutOperandList = (outs ROWD:$wd); 1211 dag InOperandList = (ins ROWS:$ws, uimm4:$m); 1212 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1213 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))]; 1214 InstrItinClass Itinerary = itin; 1215} 1216 1217// This class is deprecated and will be removed soon. 1218class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1219 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1220 InstrItinClass itin = NoItinerary> { 1221 dag OutOperandList = (outs ROWD:$wd); 1222 dag InOperandList = (ins ROWS:$ws, uimm5:$m); 1223 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1224 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))]; 1225 InstrItinClass Itinerary = itin; 1226} 1227 1228// This class is deprecated and will be removed soon. 1229class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1230 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1231 InstrItinClass itin = NoItinerary> { 1232 dag OutOperandList = (outs ROWD:$wd); 1233 dag InOperandList = (ins ROWS:$ws, uimm6:$m); 1234 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1235 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))]; 1236 InstrItinClass Itinerary = itin; 1237} 1238 1239class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1240 ComplexPattern Mask, RegisterOperand ROWD, 1241 RegisterOperand ROWS = ROWD, 1242 InstrItinClass itin = NoItinerary> { 1243 dag OutOperandList = (outs ROWD:$wd); 1244 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); 1245 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1246 // Note that binsxi and vselect treat the condition operand the opposite 1247 // way to each other. 1248 // (vselect cond, if_set, if_clear) 1249 // (BSEL_V cond, if_clear, if_set) 1250 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1251 ROWS:$wd_in))]; 1252 InstrItinClass Itinerary = itin; 1253 string Constraints = "$wd = $wd_in"; 1254} 1255 1256class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1257 RegisterOperand ROWD, 1258 RegisterOperand ROWS = ROWD, 1259 InstrItinClass itin = NoItinerary> : 1260 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>; 1261 1262class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1263 RegisterOperand ROWD, 1264 RegisterOperand ROWS = ROWD, 1265 InstrItinClass itin = NoItinerary> : 1266 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>; 1267 1268class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1269 SplatComplexPattern SplatImm, 1270 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1271 InstrItinClass itin = NoItinerary> { 1272 dag OutOperandList = (outs ROWD:$wd); 1273 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1274 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1275 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1276 InstrItinClass Itinerary = itin; 1277} 1278 1279class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1280 ValueType VecTy, RegisterOperand ROD, 1281 RegisterOperand ROWS, 1282 InstrItinClass itin = NoItinerary> { 1283 dag OutOperandList = (outs ROD:$rd); 1284 dag InOperandList = (ins ROWS:$ws, uimm4:$n); 1285 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1286 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))]; 1287 InstrItinClass Itinerary = itin; 1288} 1289 1290class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1291 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1292 InstrItinClass itin = NoItinerary> { 1293 dag OutOperandList = (outs ROWD:$wd); 1294 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n); 1295 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1296 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1297 immZExt4:$n))]; 1298 string Constraints = "$wd = $wd_in"; 1299 InstrItinClass Itinerary = itin; 1300} 1301 1302class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1303 RegisterClass RCD, RegisterClass RCWS> : 1304 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n), 1305 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> { 1306 bit usesCustomInserter = 1; 1307} 1308 1309class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1310 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1311 RegisterOperand ROWS = ROWD, 1312 InstrItinClass itin = NoItinerary> { 1313 dag OutOperandList = (outs ROWD:$wd); 1314 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1315 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1316 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1317 InstrItinClass Itinerary = itin; 1318} 1319 1320class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1321 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1322 RegisterOperand ROWS = ROWD, 1323 InstrItinClass itin = NoItinerary> { 1324 dag OutOperandList = (outs ROWD:$wd); 1325 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1326 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1327 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1328 InstrItinClass Itinerary = itin; 1329} 1330 1331class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1332 RegisterOperand ROWS = ROWD, 1333 InstrItinClass itin = NoItinerary> { 1334 dag OutOperandList = (outs ROWD:$wd); 1335 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1336 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1337 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1338 InstrItinClass Itinerary = itin; 1339} 1340 1341class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1342 InstrItinClass itin = NoItinerary> { 1343 dag OutOperandList = (outs ROWD:$wd); 1344 dag InOperandList = (ins vsplat_simm10:$s10); 1345 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1346 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1347 list<dag> Pattern = []; 1348 bit hasSideEffects = 0; 1349 InstrItinClass Itinerary = itin; 1350} 1351 1352class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1353 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1354 InstrItinClass itin = NoItinerary> { 1355 dag OutOperandList = (outs ROWD:$wd); 1356 dag InOperandList = (ins ROWS:$ws); 1357 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1358 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1359 InstrItinClass Itinerary = itin; 1360} 1361 1362class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1363 SDPatternOperator OpNode, RegisterOperand ROWD, 1364 RegisterOperand ROS = ROWD, 1365 InstrItinClass itin = NoItinerary> { 1366 dag OutOperandList = (outs ROWD:$wd); 1367 dag InOperandList = (ins ROS:$rs); 1368 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1369 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1370 InstrItinClass Itinerary = itin; 1371} 1372 1373class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1374 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1375 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1376 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1377 let usesCustomInserter = 1; 1378} 1379 1380class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1381 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1382 InstrItinClass itin = NoItinerary> { 1383 dag OutOperandList = (outs ROWD:$wd); 1384 dag InOperandList = (ins ROWS:$ws); 1385 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1386 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1387 InstrItinClass Itinerary = itin; 1388} 1389 1390class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1391 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1392 RegisterOperand ROWT = ROWD, 1393 InstrItinClass itin = NoItinerary> { 1394 dag OutOperandList = (outs ROWD:$wd); 1395 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1396 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1397 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1398 InstrItinClass Itinerary = itin; 1399} 1400 1401class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1402 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1403 RegisterOperand ROWT = ROWD, 1404 InstrItinClass itin = NoItinerary> { 1405 dag OutOperandList = (outs ROWD:$wd); 1406 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1407 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1408 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1409 ROWT:$wt))]; 1410 string Constraints = "$wd = $wd_in"; 1411 InstrItinClass Itinerary = itin; 1412} 1413 1414class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1415 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1416 InstrItinClass itin = NoItinerary> { 1417 dag OutOperandList = (outs ROWD:$wd); 1418 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1419 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1420 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1421 InstrItinClass Itinerary = itin; 1422} 1423 1424class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1425 RegisterOperand ROWS = ROWD, 1426 RegisterOperand ROWT = ROWD, 1427 InstrItinClass itin = NoItinerary> { 1428 dag OutOperandList = (outs ROWD:$wd); 1429 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1430 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1431 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1432 ROWT:$wt))]; 1433 string Constraints = "$wd = $wd_in"; 1434 InstrItinClass Itinerary = itin; 1435} 1436 1437class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1438 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1439 InstrItinClass itin = NoItinerary> { 1440 dag OutOperandList = (outs ROWD:$wd); 1441 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1442 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1443 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1444 GPR32Opnd:$rt))]; 1445 InstrItinClass Itinerary = itin; 1446 string Constraints = "$wd = $wd_in"; 1447} 1448 1449class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1450 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1451 RegisterOperand ROWT = ROWD, 1452 InstrItinClass itin = NoItinerary> { 1453 dag OutOperandList = (outs ROWD:$wd); 1454 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1455 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1456 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1457 ROWT:$wt))]; 1458 InstrItinClass Itinerary = itin; 1459 string Constraints = "$wd = $wd_in"; 1460} 1461 1462class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1463 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1464 RegisterOperand ROWT = ROWD, 1465 InstrItinClass itin = NoItinerary> : 1466 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1467 1468class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1469 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1470 RegisterOperand ROWT = ROWD, 1471 InstrItinClass itin = NoItinerary> : 1472 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1473 1474class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1475 dag OutOperandList = (outs); 1476 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1477 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1478 list<dag> Pattern = []; 1479 InstrItinClass Itinerary = IIBranch; 1480 bit isBranch = 1; 1481 bit isTerminator = 1; 1482 bit hasDelaySlot = 1; 1483 list<Register> Defs = [AT]; 1484} 1485 1486class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1487 RegisterOperand ROWD, RegisterOperand ROS, 1488 InstrItinClass itin = NoItinerary> { 1489 dag OutOperandList = (outs ROWD:$wd); 1490 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n); 1491 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1492 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1493 ROS:$rs, 1494 immZExt6:$n))]; 1495 InstrItinClass Itinerary = itin; 1496 string Constraints = "$wd = $wd_in"; 1497} 1498 1499class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1500 RegisterOperand ROWD, RegisterOperand ROFS> : 1501 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs), 1502 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1503 immZExt6:$n))]> { 1504 bit usesCustomInserter = 1; 1505 string Constraints = "$wd = $wd_in"; 1506} 1507 1508class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1509 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1510 InstrItinClass itin = NoItinerary> { 1511 dag OutOperandList = (outs ROWD:$wd); 1512 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2); 1513 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1514 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1515 immZExt6:$n, 1516 ROWS:$ws, 1517 immz:$n2))]; 1518 InstrItinClass Itinerary = itin; 1519 string Constraints = "$wd = $wd_in"; 1520} 1521 1522class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1523 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1524 RegisterOperand ROWT = ROWD, 1525 InstrItinClass itin = NoItinerary> { 1526 dag OutOperandList = (outs ROWD:$wd); 1527 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1528 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1529 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1530 InstrItinClass Itinerary = itin; 1531} 1532 1533class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1534 RegisterOperand ROWD, 1535 RegisterOperand ROWS = ROWD, 1536 InstrItinClass itin = NoItinerary> { 1537 dag OutOperandList = (outs ROWD:$wd); 1538 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1539 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1540 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1541 ROWS:$ws))]; 1542 InstrItinClass Itinerary = itin; 1543} 1544 1545class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1546 RegisterOperand ROWS = ROWD, 1547 RegisterOperand ROWT = ROWD> : 1548 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1549 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1550 1551class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1552 IsCommutable; 1553class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1554 IsCommutable; 1555class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1556 IsCommutable; 1557class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1558 IsCommutable; 1559 1560class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1561 MSA128BOpnd>, IsCommutable; 1562class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1563 MSA128HOpnd>, IsCommutable; 1564class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1565 MSA128WOpnd>, IsCommutable; 1566class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1567 MSA128DOpnd>, IsCommutable; 1568 1569class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1570 MSA128BOpnd>, IsCommutable; 1571class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1572 MSA128HOpnd>, IsCommutable; 1573class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1574 MSA128WOpnd>, IsCommutable; 1575class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1576 MSA128DOpnd>, IsCommutable; 1577 1578class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1579 MSA128BOpnd>, IsCommutable; 1580class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1581 MSA128HOpnd>, IsCommutable; 1582class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1583 MSA128WOpnd>, IsCommutable; 1584class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1585 MSA128DOpnd>, IsCommutable; 1586 1587class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1588class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1589class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1590class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1591 1592class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1593 MSA128BOpnd>; 1594class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1595 MSA128HOpnd>; 1596class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1597 MSA128WOpnd>; 1598class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1599 MSA128DOpnd>; 1600 1601class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1602class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1603class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1604class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1605 1606class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1607 MSA128BOpnd>; 1608 1609class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1610 MSA128BOpnd>; 1611class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1612 MSA128HOpnd>; 1613class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1614 MSA128WOpnd>; 1615class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1616 MSA128DOpnd>; 1617 1618class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1619 MSA128BOpnd>; 1620class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1621 MSA128HOpnd>; 1622class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1623 MSA128WOpnd>; 1624class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1625 MSA128DOpnd>; 1626 1627class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1628 IsCommutable; 1629class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1630 IsCommutable; 1631class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1632 IsCommutable; 1633class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1634 IsCommutable; 1635 1636class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1637 IsCommutable; 1638class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1639 IsCommutable; 1640class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1641 IsCommutable; 1642class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1643 IsCommutable; 1644 1645class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1646 MSA128BOpnd>, IsCommutable; 1647class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1648 MSA128HOpnd>, IsCommutable; 1649class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1650 MSA128WOpnd>, IsCommutable; 1651class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1652 MSA128DOpnd>, IsCommutable; 1653 1654class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1655 MSA128BOpnd>, IsCommutable; 1656class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1657 MSA128HOpnd>, IsCommutable; 1658class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1659 MSA128WOpnd>, IsCommutable; 1660class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1661 MSA128DOpnd>, IsCommutable; 1662 1663class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1664class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1665class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1666class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1667 1668class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1669 MSA128BOpnd>; 1670class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1671 MSA128HOpnd>; 1672class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1673 MSA128WOpnd>; 1674class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1675 MSA128DOpnd>; 1676 1677class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1678 MSA128BOpnd>; 1679class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1680 MSA128HOpnd>; 1681class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1682 MSA128WOpnd>; 1683class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1684 MSA128DOpnd>; 1685 1686class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; 1687class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; 1688class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; 1689class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; 1690 1691class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1692 MSA128BOpnd>; 1693class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1694 MSA128HOpnd>; 1695class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1696 MSA128WOpnd>; 1697class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1698 MSA128DOpnd>; 1699 1700class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; 1701class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; 1702class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; 1703class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; 1704 1705class BMNZ_V_DESC { 1706 dag OutOperandList = (outs MSA128BOpnd:$wd); 1707 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1708 MSA128BOpnd:$wt); 1709 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1710 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1711 MSA128BOpnd:$ws, 1712 MSA128BOpnd:$wd_in))]; 1713 InstrItinClass Itinerary = NoItinerary; 1714 string Constraints = "$wd = $wd_in"; 1715} 1716 1717class BMNZI_B_DESC { 1718 dag OutOperandList = (outs MSA128BOpnd:$wd); 1719 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1720 vsplat_uimm8:$u8); 1721 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1722 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1723 MSA128BOpnd:$ws, 1724 MSA128BOpnd:$wd_in))]; 1725 InstrItinClass Itinerary = NoItinerary; 1726 string Constraints = "$wd = $wd_in"; 1727} 1728 1729class BMZ_V_DESC { 1730 dag OutOperandList = (outs MSA128BOpnd:$wd); 1731 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1732 MSA128BOpnd:$wt); 1733 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1734 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1735 MSA128BOpnd:$wd_in, 1736 MSA128BOpnd:$ws))]; 1737 InstrItinClass Itinerary = NoItinerary; 1738 string Constraints = "$wd = $wd_in"; 1739} 1740 1741class BMZI_B_DESC { 1742 dag OutOperandList = (outs MSA128BOpnd:$wd); 1743 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1744 vsplat_uimm8:$u8); 1745 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1746 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1747 MSA128BOpnd:$wd_in, 1748 MSA128BOpnd:$ws))]; 1749 InstrItinClass Itinerary = NoItinerary; 1750 string Constraints = "$wd = $wd_in"; 1751} 1752 1753class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1754class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1755class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1756class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1757 1758class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1759 MSA128BOpnd>; 1760class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1761 MSA128HOpnd>; 1762class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1763 MSA128WOpnd>; 1764class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1765 MSA128DOpnd>; 1766 1767class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1768class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1769class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1770class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1771 1772class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1773 1774class BSEL_V_DESC { 1775 dag OutOperandList = (outs MSA128BOpnd:$wd); 1776 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1777 MSA128BOpnd:$wt); 1778 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1779 // Note that vselect and BSEL_V treat the condition operand the opposite way 1780 // from each other. 1781 // (vselect cond, if_set, if_clear) 1782 // (BSEL_V cond, if_clear, if_set) 1783 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1784 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1785 MSA128BOpnd:$ws))]; 1786 InstrItinClass Itinerary = NoItinerary; 1787 string Constraints = "$wd = $wd_in"; 1788} 1789 1790class BSELI_B_DESC { 1791 dag OutOperandList = (outs MSA128BOpnd:$wd); 1792 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1793 vsplat_uimm8:$u8); 1794 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1795 // Note that vselect and BSEL_V treat the condition operand the opposite way 1796 // from each other. 1797 // (vselect cond, if_set, if_clear) 1798 // (BSEL_V cond, if_clear, if_set) 1799 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1800 vsplati8_uimm8:$u8, 1801 MSA128BOpnd:$ws))]; 1802 InstrItinClass Itinerary = NoItinerary; 1803 string Constraints = "$wd = $wd_in"; 1804} 1805 1806class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1807class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1808class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1809class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1810 1811class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1812 MSA128BOpnd>; 1813class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1814 MSA128HOpnd>; 1815class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1816 MSA128WOpnd>; 1817class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1818 MSA128DOpnd>; 1819 1820class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1821class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1822class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1823class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1824 1825class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1826 1827class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1828 IsCommutable; 1829class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1830 IsCommutable; 1831class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1832 IsCommutable; 1833class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1834 IsCommutable; 1835 1836class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1837 MSA128BOpnd>; 1838class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1839 MSA128HOpnd>; 1840class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1841 MSA128WOpnd>; 1842class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1843 MSA128DOpnd>; 1844 1845class CFCMSA_DESC { 1846 dag OutOperandList = (outs GPR32Opnd:$rd); 1847 dag InOperandList = (ins MSA128CROpnd:$cs); 1848 string AsmString = "cfcmsa\t$rd, $cs"; 1849 InstrItinClass Itinerary = NoItinerary; 1850 bit hasSideEffects = 1; 1851} 1852 1853class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1854class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1855class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1856class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1857 1858class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1859class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1860class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1861class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1862 1863class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1864 vsplati8_simm5, MSA128BOpnd>; 1865class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1866 vsplati16_simm5, MSA128HOpnd>; 1867class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1868 vsplati32_simm5, MSA128WOpnd>; 1869class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1870 vsplati64_simm5, MSA128DOpnd>; 1871 1872class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1873 vsplati8_uimm5, MSA128BOpnd>; 1874class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1875 vsplati16_uimm5, MSA128HOpnd>; 1876class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1877 vsplati32_uimm5, MSA128WOpnd>; 1878class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1879 vsplati64_uimm5, MSA128DOpnd>; 1880 1881class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1882class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1883class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1884class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1885 1886class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1887class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1888class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1889class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1890 1891class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1892 vsplati8_simm5, MSA128BOpnd>; 1893class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1894 vsplati16_simm5, MSA128HOpnd>; 1895class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1896 vsplati32_simm5, MSA128WOpnd>; 1897class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1898 vsplati64_simm5, MSA128DOpnd>; 1899 1900class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1901 vsplati8_uimm5, MSA128BOpnd>; 1902class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1903 vsplati16_uimm5, MSA128HOpnd>; 1904class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1905 vsplati32_uimm5, MSA128WOpnd>; 1906class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1907 vsplati64_uimm5, MSA128DOpnd>; 1908 1909class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1910 GPR32Opnd, MSA128BOpnd>; 1911class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1912 GPR32Opnd, MSA128HOpnd>; 1913class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1914 GPR32Opnd, MSA128WOpnd>; 1915class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1916 GPR64Opnd, MSA128DOpnd>; 1917 1918class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1919 GPR32Opnd, MSA128BOpnd>; 1920class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1921 GPR32Opnd, MSA128HOpnd>; 1922class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1923 GPR32Opnd, MSA128WOpnd>; 1924class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64, 1925 GPR64Opnd, MSA128DOpnd>; 1926 1927class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32, 1928 MSA128W>; 1929class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64, 1930 MSA128D>; 1931 1932class CTCMSA_DESC { 1933 dag OutOperandList = (outs); 1934 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1935 string AsmString = "ctcmsa\t$cd, $rs"; 1936 InstrItinClass Itinerary = NoItinerary; 1937 bit hasSideEffects = 1; 1938} 1939 1940class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1941class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1942class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1943class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1944 1945class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1946class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1947class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1948class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1949 1950class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1951 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1952 IsCommutable; 1953class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1954 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1955 IsCommutable; 1956class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1957 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1958 IsCommutable; 1959 1960class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1961 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1962 IsCommutable; 1963class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1964 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1965 IsCommutable; 1966class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1967 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1968 IsCommutable; 1969 1970class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1971 MSA128HOpnd, MSA128BOpnd, 1972 MSA128BOpnd>, IsCommutable; 1973class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1974 MSA128WOpnd, MSA128HOpnd, 1975 MSA128HOpnd>, IsCommutable; 1976class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1977 MSA128DOpnd, MSA128WOpnd, 1978 MSA128WOpnd>, IsCommutable; 1979 1980class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1981 MSA128HOpnd, MSA128BOpnd, 1982 MSA128BOpnd>, IsCommutable; 1983class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1984 MSA128WOpnd, MSA128HOpnd, 1985 MSA128HOpnd>, IsCommutable; 1986class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1987 MSA128DOpnd, MSA128WOpnd, 1988 MSA128WOpnd>, IsCommutable; 1989 1990class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1991 MSA128HOpnd, MSA128BOpnd, 1992 MSA128BOpnd>; 1993class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1994 MSA128WOpnd, MSA128HOpnd, 1995 MSA128HOpnd>; 1996class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1997 MSA128DOpnd, MSA128WOpnd, 1998 MSA128WOpnd>; 1999 2000class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 2001 MSA128HOpnd, MSA128BOpnd, 2002 MSA128BOpnd>; 2003class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 2004 MSA128WOpnd, MSA128HOpnd, 2005 MSA128HOpnd>; 2006class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 2007 MSA128DOpnd, MSA128WOpnd, 2008 MSA128WOpnd>; 2009 2010class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 2011 IsCommutable; 2012class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 2013 IsCommutable; 2014 2015class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 2016 IsCommutable; 2017class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 2018 IsCommutable; 2019 2020class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 2021 IsCommutable; 2022class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 2023 IsCommutable; 2024 2025class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 2026 MSA128WOpnd>; 2027class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 2028 MSA128DOpnd>; 2029 2030class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 2031class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 2032 2033class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 2034class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 2035 2036class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2037 IsCommutable; 2038class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2039 IsCommutable; 2040 2041class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2042 IsCommutable; 2043class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2044 IsCommutable; 2045 2046class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2047 IsCommutable; 2048class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2049 IsCommutable; 2050 2051class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2052 IsCommutable; 2053class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2054 IsCommutable; 2055 2056class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2057 IsCommutable; 2058class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2059 IsCommutable; 2060 2061class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2062 IsCommutable; 2063class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2064 IsCommutable; 2065 2066class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2067 IsCommutable; 2068class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2069 IsCommutable; 2070 2071class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2072class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2073 2074class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2075 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2076class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2077 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2078 2079// The fexp2.df instruction multiplies the first operand by 2 to the power of 2080// the second operand. We therefore need a pseudo-insn in order to invent the 2081// 1.0 when we only need to match ISD::FEXP2. 2082class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2083class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2084let usesCustomInserter = 1 in { 2085 class FEXP2_W_1_PSEUDO_DESC : 2086 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2087 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2088 class FEXP2_D_1_PSEUDO_DESC : 2089 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2090 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2091} 2092 2093class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2094 MSA128WOpnd, MSA128HOpnd>; 2095class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2096 MSA128DOpnd, MSA128WOpnd>; 2097 2098class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2099 MSA128WOpnd, MSA128HOpnd>; 2100class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2101 MSA128DOpnd, MSA128WOpnd>; 2102 2103class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2104class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2105 2106class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2107class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2108 2109class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2110 MSA128WOpnd, MSA128HOpnd>; 2111class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2112 MSA128DOpnd, MSA128WOpnd>; 2113 2114class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2115 MSA128WOpnd, MSA128HOpnd>; 2116class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2117 MSA128DOpnd, MSA128WOpnd>; 2118 2119class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2120 MSA128BOpnd, GPR32Opnd>; 2121class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2122 MSA128HOpnd, GPR32Opnd>; 2123class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2124 MSA128WOpnd, GPR32Opnd>; 2125class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2126 MSA128DOpnd, GPR64Opnd>; 2127 2128class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2129 FGR32>; 2130class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2131 FGR64>; 2132 2133class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2134class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2135 2136class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2137class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2138 2139class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2140class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2141 2142class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2143 MSA128WOpnd>; 2144class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2145 MSA128DOpnd>; 2146 2147class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2148class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2149 2150class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2151 MSA128WOpnd>; 2152class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2153 MSA128DOpnd>; 2154 2155class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>; 2156class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>; 2157 2158class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2159class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2160 2161class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2162class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2163 2164class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2165class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2166 2167class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2168 MSA128WOpnd>; 2169class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2170 MSA128DOpnd>; 2171 2172class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2173class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2174 2175class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2176class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2177 2178class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2179class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2180 2181class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2182class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2183 2184class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2185class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2186 2187class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2188class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2189 2190class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2191class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2192 2193class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2194class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2195 2196class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2197 MSA128WOpnd>; 2198class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2199 MSA128DOpnd>; 2200 2201class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2202 MSA128WOpnd>; 2203class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2204 MSA128DOpnd>; 2205 2206class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2207 MSA128WOpnd>; 2208class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2209 MSA128DOpnd>; 2210 2211class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2212 MSA128WOpnd>; 2213class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2214 MSA128DOpnd>; 2215 2216class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2217 MSA128WOpnd>; 2218class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2219 MSA128DOpnd>; 2220 2221class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2222 MSA128WOpnd>; 2223class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2224 MSA128DOpnd>; 2225 2226class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2227 MSA128WOpnd>; 2228class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2229 MSA128DOpnd>; 2230 2231class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2232 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2233class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2234 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2235 2236class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2237 MSA128WOpnd>; 2238class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2239 MSA128DOpnd>; 2240 2241class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2242 MSA128WOpnd>; 2243class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2244 MSA128DOpnd>; 2245 2246class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2247 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2248class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2249 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2250class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2251 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2252 2253class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2254 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2255class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2256 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2257class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2258 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2259 2260class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2261 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2262class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2263 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2264class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2265 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2266 2267class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2268 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2269class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2270 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2271class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2272 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2273 2274class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2275class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2276class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2277class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2278 2279class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2280class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2281class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2282class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2283 2284class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2285class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2286class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2287class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2288 2289class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2290class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2291class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2292class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2293 2294class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, 2295 MSA128BOpnd, GPR32Opnd>; 2296class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, 2297 MSA128HOpnd, GPR32Opnd>; 2298class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, 2299 MSA128WOpnd, GPR32Opnd>; 2300class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, 2301 MSA128DOpnd, GPR64Opnd>; 2302 2303class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2304 MSA128WOpnd, FGR32Opnd>; 2305class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2306 MSA128DOpnd, FGR64Opnd>; 2307 2308class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, 2309 MSA128BOpnd>; 2310class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, 2311 MSA128HOpnd>; 2312class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, 2313 MSA128WOpnd>; 2314class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, 2315 MSA128DOpnd>; 2316 2317class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2318 ValueType TyNode, RegisterOperand ROWD, 2319 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2320 InstrItinClass itin = NoItinerary> { 2321 dag OutOperandList = (outs ROWD:$wd); 2322 dag InOperandList = (ins MemOpnd:$addr); 2323 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2324 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2325 InstrItinClass Itinerary = itin; 2326 string DecoderMethod = "DecodeMSA128Mem"; 2327} 2328 2329class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; 2330class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; 2331class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; 2332class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; 2333 2334class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2335class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2336class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2337class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2338 2339class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2340 RegisterOperand RORS = RORD, RegisterOperand RORT = RORD, 2341 InstrItinClass itin = NoItinerary > { 2342 dag OutOperandList = (outs RORD:$rd); 2343 dag InOperandList = (ins RORS:$rs, RORT:$rt, LSAImm:$sa); 2344 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2345 list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt, 2346 (shl RORS:$rs, 2347 immZExt2Lsa:$sa)))]; 2348 InstrItinClass Itinerary = itin; 2349} 2350 2351class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>; 2352class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>; 2353 2354class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2355 MSA128HOpnd>; 2356class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2357 MSA128WOpnd>; 2358 2359class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2360 MSA128HOpnd>; 2361class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2362 MSA128WOpnd>; 2363 2364class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2365class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2366class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2367class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2368 2369class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2370class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2371class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2372class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2373 2374class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; 2375class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; 2376class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; 2377class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; 2378 2379class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; 2380class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; 2381class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; 2382class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; 2383 2384class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, 2385 MSA128BOpnd>; 2386class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, 2387 MSA128HOpnd>; 2388class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, 2389 MSA128WOpnd>; 2390class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, 2391 MSA128DOpnd>; 2392 2393class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, 2394 MSA128BOpnd>; 2395class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, 2396 MSA128HOpnd>; 2397class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, 2398 MSA128WOpnd>; 2399class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, 2400 MSA128DOpnd>; 2401 2402class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2403class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2404class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2405class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2406 2407class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; 2408class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; 2409class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; 2410class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; 2411 2412class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; 2413class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; 2414class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; 2415class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; 2416 2417class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, 2418 MSA128BOpnd>; 2419class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, 2420 MSA128HOpnd>; 2421class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, 2422 MSA128WOpnd>; 2423class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, 2424 MSA128DOpnd>; 2425 2426class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, 2427 MSA128BOpnd>; 2428class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, 2429 MSA128HOpnd>; 2430class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, 2431 MSA128WOpnd>; 2432class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, 2433 MSA128DOpnd>; 2434 2435class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2436class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2437class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2438class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2439 2440class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2441class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2442class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2443class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2444 2445class MOVE_V_DESC { 2446 dag OutOperandList = (outs MSA128BOpnd:$wd); 2447 dag InOperandList = (ins MSA128BOpnd:$ws); 2448 string AsmString = "move.v\t$wd, $ws"; 2449 list<dag> Pattern = []; 2450 InstrItinClass Itinerary = NoItinerary; 2451} 2452 2453class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2454 MSA128HOpnd>; 2455class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2456 MSA128WOpnd>; 2457 2458class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2459 MSA128HOpnd>; 2460class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2461 MSA128WOpnd>; 2462 2463class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2464class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2465class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2466class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2467 2468class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2469 MSA128HOpnd>; 2470class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2471 MSA128WOpnd>; 2472 2473class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2474 MSA128HOpnd>; 2475class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2476 MSA128WOpnd>; 2477 2478class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2479class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2480class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2481class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2482 2483class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2484class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2485class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2486class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2487 2488class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2489class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2490class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2491class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2492 2493class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2494class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2495class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2496class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2497 2498class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2499 MSA128BOpnd>; 2500 2501class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2502class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2503class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2504class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2505 2506class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2507 2508class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2509class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2510class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2511class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2512 2513class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2514class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2515class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2516class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2517 2518class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2519class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2520class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2521class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2522 2523class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, 2524 MSA128BOpnd>; 2525class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, 2526 MSA128HOpnd>; 2527class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, 2528 MSA128WOpnd>; 2529class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, 2530 MSA128DOpnd>; 2531 2532class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, 2533 MSA128BOpnd>; 2534class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, 2535 MSA128HOpnd>; 2536class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, 2537 MSA128WOpnd>; 2538class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, 2539 MSA128DOpnd>; 2540 2541class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2542class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2543class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2544 2545class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2546class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2547class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2548class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2549 2550class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2551 MSA128BOpnd>; 2552class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2553 MSA128HOpnd>; 2554class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2555 MSA128WOpnd>; 2556class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2557 MSA128DOpnd>; 2558 2559class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2560class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2561class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2562class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2563 2564class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2565 MSA128BOpnd>; 2566class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2567 MSA128HOpnd>; 2568class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2569 MSA128WOpnd>; 2570class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2571 MSA128DOpnd>; 2572 2573class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2574 MSA128BOpnd>; 2575class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2576 MSA128HOpnd>; 2577class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2578 MSA128WOpnd>; 2579class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2580 MSA128DOpnd>; 2581 2582class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2583 MSA128BOpnd>; 2584class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2585 MSA128HOpnd>; 2586class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2587 MSA128WOpnd>; 2588class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2589 MSA128DOpnd>; 2590 2591class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2592class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2593class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2594class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2595 2596class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2597 MSA128BOpnd>; 2598class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2599 MSA128HOpnd>; 2600class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2601 MSA128WOpnd>; 2602class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2603 MSA128DOpnd>; 2604 2605class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2606class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2607class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2608class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2609 2610class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b, 2611 MSA128BOpnd>; 2612class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h, 2613 MSA128HOpnd>; 2614class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w, 2615 MSA128WOpnd>; 2616class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d, 2617 MSA128DOpnd>; 2618 2619class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2620class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2621class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2622class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2623 2624class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2625 MSA128BOpnd>; 2626class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2627 MSA128HOpnd>; 2628class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2629 MSA128WOpnd>; 2630class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2631 MSA128DOpnd>; 2632 2633class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2634class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2635class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2636class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2637 2638class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b, 2639 MSA128BOpnd>; 2640class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h, 2641 MSA128HOpnd>; 2642class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w, 2643 MSA128WOpnd>; 2644class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, 2645 MSA128DOpnd>; 2646 2647class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2648 ValueType TyNode, RegisterOperand ROWD, 2649 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2650 InstrItinClass itin = NoItinerary> { 2651 dag OutOperandList = (outs); 2652 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2653 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2654 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2655 InstrItinClass Itinerary = itin; 2656 string DecoderMethod = "DecodeMSA128Mem"; 2657} 2658 2659class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; 2660class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; 2661class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; 2662class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; 2663 2664class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2665 MSA128BOpnd>; 2666class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2667 MSA128HOpnd>; 2668class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2669 MSA128WOpnd>; 2670class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2671 MSA128DOpnd>; 2672 2673class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2674 MSA128BOpnd>; 2675class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2676 MSA128HOpnd>; 2677class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2678 MSA128WOpnd>; 2679class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2680 MSA128DOpnd>; 2681 2682class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2683 MSA128BOpnd>; 2684class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2685 MSA128HOpnd>; 2686class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2687 MSA128WOpnd>; 2688class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2689 MSA128DOpnd>; 2690 2691class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2692 MSA128BOpnd>; 2693class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2694 MSA128HOpnd>; 2695class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2696 MSA128WOpnd>; 2697class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2698 MSA128DOpnd>; 2699 2700class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2701class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2702class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2703class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2704 2705class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2706 MSA128BOpnd>; 2707class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2708 MSA128HOpnd>; 2709class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2710 MSA128WOpnd>; 2711class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2712 MSA128DOpnd>; 2713 2714class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2715class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2716class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2717class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2718 2719class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2720class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2721class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2722class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2723 2724class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2725 MSA128BOpnd>; 2726 2727// Instruction defs. 2728def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2729def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2730def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2731def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2732 2733def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2734def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2735def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2736def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2737 2738def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2739def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2740def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2741def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2742 2743def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2744def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2745def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2746def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2747 2748def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2749def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2750def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2751def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2752 2753def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2754def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2755def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2756def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2757 2758def AND_V : AND_V_ENC, AND_V_DESC; 2759def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2760 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2761 MSA128BOpnd:$ws, 2762 MSA128BOpnd:$wt)>; 2763def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2764 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2765 MSA128BOpnd:$ws, 2766 MSA128BOpnd:$wt)>; 2767def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2768 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2769 MSA128BOpnd:$ws, 2770 MSA128BOpnd:$wt)>; 2771 2772def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2773 2774def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2775def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2776def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2777def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2778 2779def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2780def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2781def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2782def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2783 2784def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2785def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2786def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2787def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2788 2789def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2790def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2791def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2792def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2793 2794def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2795def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2796def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2797def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2798 2799def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2800def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2801def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2802def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2803 2804def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2805def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2806def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2807def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2808 2809def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2810def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2811def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2812def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2813 2814def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2815def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2816def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2817def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2818 2819def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2820def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2821def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2822def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2823 2824def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2825def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2826def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2827def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2828 2829def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2830def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2831def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2832def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2833 2834def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2835 2836def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2837 2838def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2839 2840def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2841 2842def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2843def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2844def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2845def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2846 2847def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2848def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2849def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2850def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2851 2852def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2853def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2854def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2855def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2856 2857def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2858 2859def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2860 2861class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2862 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2863 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2864 // Note that vselect and BSEL_V treat the condition operand the opposite way 2865 // from each other. 2866 // (vselect cond, if_set, if_clear) 2867 // (BSEL_V cond, if_clear, if_set) 2868 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2869 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2870 let Constraints = "$wd_in = $wd"; 2871} 2872 2873def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2874def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2875def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2876def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2877def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2878 2879def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2880 2881def BSET_B : BSET_B_ENC, BSET_B_DESC; 2882def BSET_H : BSET_H_ENC, BSET_H_DESC; 2883def BSET_W : BSET_W_ENC, BSET_W_DESC; 2884def BSET_D : BSET_D_ENC, BSET_D_DESC; 2885 2886def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2887def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2888def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2889def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2890 2891def BZ_B : BZ_B_ENC, BZ_B_DESC; 2892def BZ_H : BZ_H_ENC, BZ_H_DESC; 2893def BZ_W : BZ_W_ENC, BZ_W_DESC; 2894def BZ_D : BZ_D_ENC, BZ_D_DESC; 2895 2896def BZ_V : BZ_V_ENC, BZ_V_DESC; 2897 2898def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2899def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2900def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2901def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2902 2903def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2904def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2905def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2906def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2907 2908def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2909 2910def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2911def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2912def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2913def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2914 2915def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2916def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2917def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2918def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2919 2920def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2921def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2922def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2923def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2924 2925def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2926def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2927def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2928def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2929 2930def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2931def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2932def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2933def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2934 2935def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2936def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2937def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2938def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2939 2940def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2941def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2942def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2943def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2944 2945def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2946def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2947def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2948def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2949 2950def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2951def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2952def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2953def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC; 2954 2955def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2956def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2957def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC; 2958def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC; 2959 2960def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2961def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2962 2963def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2964 2965def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2966def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2967def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2968def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2969 2970def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2971def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2972def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2973def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2974 2975def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2976def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2977def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2978 2979def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2980def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2981def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2982 2983def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2984def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2985def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2986 2987def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2988def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2989def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2990 2991def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2992def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2993def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2994 2995def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2996def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 2997def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 2998 2999def FADD_W : FADD_W_ENC, FADD_W_DESC; 3000def FADD_D : FADD_D_ENC, FADD_D_DESC; 3001 3002def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3003def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3004 3005def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3006def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3007 3008def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3009def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3010 3011def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3012def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3013 3014def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3015def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3016 3017def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3018def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3019 3020def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3021def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3022 3023def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3024def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3025 3026def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3027def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3028 3029def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3030def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3031 3032def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3033def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3034 3035def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3036def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3037 3038def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3039def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3040 3041def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3042def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3043 3044def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3045def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3046def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3047def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3048 3049def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3050def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3051 3052def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3053def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3054 3055def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3056def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3057 3058def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3059def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3060 3061def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3062def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3063 3064def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3065def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3066 3067def FILL_B : FILL_B_ENC, FILL_B_DESC; 3068def FILL_H : FILL_H_ENC, FILL_H_DESC; 3069def FILL_W : FILL_W_ENC, FILL_W_DESC; 3070def FILL_D : FILL_D_ENC, FILL_D_DESC; 3071def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3072def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3073 3074def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3075def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3076 3077def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3078def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3079 3080def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3081def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3082 3083def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3084def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3085 3086def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3087def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3088 3089def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3090def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3091 3092def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3093def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3094 3095def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3096def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3097 3098def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3099def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3100 3101def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3102def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3103 3104def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3105def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3106 3107def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3108def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3109 3110def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3111def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3112 3113def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3114def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3115 3116def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3117def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3118 3119def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3120def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3121 3122def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3123def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3124 3125def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3126def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3127 3128def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3129def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3130 3131def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3132def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3133 3134def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3135def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3136 3137def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3138def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3139 3140def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3141def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3142 3143def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3144def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3145 3146def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3147def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3148 3149def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3150def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3151 3152def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3153def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3154 3155def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3156def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3157 3158def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3159def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3160 3161def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3162def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3163def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3164 3165def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3166def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3167def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3168 3169def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3170def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3171def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3172 3173def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3174def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3175def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3176 3177def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3178def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3179def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3180def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3181 3182def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3183def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3184def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3185def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3186 3187def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3188def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3189def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3190def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3191 3192def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3193def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3194def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3195def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3196 3197def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3198def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3199def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3200def INSERT_D : INSERT_D_ENC, INSERT_D_DESC; 3201 3202// INSERT_FW_PSEUDO defined after INSVE_W 3203// INSERT_FD_PSEUDO defined after INSVE_D 3204 3205// There is a fourth operand that is not present in the encoding. Use a 3206// custom decoder to get a chance to add it. 3207let DecoderMethod = "DecodeINSVE_DF" in { 3208 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3209 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3210 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3211 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3212} 3213 3214def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3215def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3216 3217def LD_B: LD_B_ENC, LD_B_DESC; 3218def LD_H: LD_H_ENC, LD_H_DESC; 3219def LD_W: LD_W_ENC, LD_W_DESC; 3220def LD_D: LD_D_ENC, LD_D_DESC; 3221 3222def LDI_B : LDI_B_ENC, LDI_B_DESC; 3223def LDI_H : LDI_H_ENC, LDI_H_DESC; 3224def LDI_W : LDI_W_ENC, LDI_W_DESC; 3225def LDI_D : LDI_D_ENC, LDI_D_DESC; 3226 3227def LSA : LSA_ENC, LSA_DESC; 3228def DLSA : DLSA_ENC, DLSA_DESC; 3229 3230def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3231def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3232 3233def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3234def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3235 3236def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3237def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3238def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3239def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3240 3241def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3242def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3243def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3244def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3245 3246def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3247def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3248def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3249def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3250 3251def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3252def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3253def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3254def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3255 3256def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3257def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3258def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3259def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3260 3261def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3262def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3263def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3264def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3265 3266def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3267def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3268def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3269def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3270 3271def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3272def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3273def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3274def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3275 3276def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3277def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3278def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3279def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3280 3281def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3282def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3283def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3284def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3285 3286def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3287def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3288def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3289def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3290 3291def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3292def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3293def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3294def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3295 3296def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3297def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3298def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3299def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3300 3301def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3302 3303def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3304def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3305 3306def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3307def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3308 3309def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3310def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3311def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3312def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3313 3314def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3315def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3316 3317def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3318def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3319 3320def MULV_B : MULV_B_ENC, MULV_B_DESC; 3321def MULV_H : MULV_H_ENC, MULV_H_DESC; 3322def MULV_W : MULV_W_ENC, MULV_W_DESC; 3323def MULV_D : MULV_D_ENC, MULV_D_DESC; 3324 3325def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3326def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3327def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3328def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3329 3330def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3331def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3332def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3333def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3334 3335def NOR_V : NOR_V_ENC, NOR_V_DESC; 3336def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3337 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3338 MSA128BOpnd:$ws, 3339 MSA128BOpnd:$wt)>; 3340def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3341 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3342 MSA128BOpnd:$ws, 3343 MSA128BOpnd:$wt)>; 3344def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3345 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3346 MSA128BOpnd:$ws, 3347 MSA128BOpnd:$wt)>; 3348 3349def NORI_B : NORI_B_ENC, NORI_B_DESC; 3350 3351def OR_V : OR_V_ENC, OR_V_DESC; 3352def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3353 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3354 MSA128BOpnd:$ws, 3355 MSA128BOpnd:$wt)>; 3356def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3357 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3358 MSA128BOpnd:$ws, 3359 MSA128BOpnd:$wt)>; 3360def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3361 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3362 MSA128BOpnd:$ws, 3363 MSA128BOpnd:$wt)>; 3364 3365def ORI_B : ORI_B_ENC, ORI_B_DESC; 3366 3367def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3368def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3369def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3370def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3371 3372def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3373def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3374def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3375def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3376 3377def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3378def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3379def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3380def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3381 3382def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3383def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3384def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3385def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3386 3387def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3388def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3389def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3390def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3391 3392def SHF_B : SHF_B_ENC, SHF_B_DESC; 3393def SHF_H : SHF_H_ENC, SHF_H_DESC; 3394def SHF_W : SHF_W_ENC, SHF_W_DESC; 3395 3396def SLD_B : SLD_B_ENC, SLD_B_DESC; 3397def SLD_H : SLD_H_ENC, SLD_H_DESC; 3398def SLD_W : SLD_W_ENC, SLD_W_DESC; 3399def SLD_D : SLD_D_ENC, SLD_D_DESC; 3400 3401def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3402def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3403def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3404def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3405 3406def SLL_B : SLL_B_ENC, SLL_B_DESC; 3407def SLL_H : SLL_H_ENC, SLL_H_DESC; 3408def SLL_W : SLL_W_ENC, SLL_W_DESC; 3409def SLL_D : SLL_D_ENC, SLL_D_DESC; 3410 3411def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3412def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3413def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3414def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3415 3416def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3417def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3418def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3419def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3420 3421def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3422def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3423def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3424def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3425 3426def SRA_B : SRA_B_ENC, SRA_B_DESC; 3427def SRA_H : SRA_H_ENC, SRA_H_DESC; 3428def SRA_W : SRA_W_ENC, SRA_W_DESC; 3429def SRA_D : SRA_D_ENC, SRA_D_DESC; 3430 3431def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3432def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3433def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3434def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3435 3436def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3437def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3438def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3439def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3440 3441def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3442def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3443def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3444def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3445 3446def SRL_B : SRL_B_ENC, SRL_B_DESC; 3447def SRL_H : SRL_H_ENC, SRL_H_DESC; 3448def SRL_W : SRL_W_ENC, SRL_W_DESC; 3449def SRL_D : SRL_D_ENC, SRL_D_DESC; 3450 3451def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3452def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3453def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3454def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3455 3456def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3457def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3458def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3459def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3460 3461def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3462def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3463def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3464def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3465 3466def ST_B: ST_B_ENC, ST_B_DESC; 3467def ST_H: ST_H_ENC, ST_H_DESC; 3468def ST_W: ST_W_ENC, ST_W_DESC; 3469def ST_D: ST_D_ENC, ST_D_DESC; 3470 3471def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3472def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3473def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3474def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3475 3476def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3477def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3478def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3479def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3480 3481def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3482def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3483def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3484def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3485 3486def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3487def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3488def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3489def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3490 3491def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3492def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3493def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3494def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3495 3496def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3497def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3498def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3499def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3500 3501def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3502def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3503def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3504def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3505 3506def XOR_V : XOR_V_ENC, XOR_V_DESC; 3507def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3508 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3509 MSA128BOpnd:$ws, 3510 MSA128BOpnd:$wt)>; 3511def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3512 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3513 MSA128BOpnd:$ws, 3514 MSA128BOpnd:$wt)>; 3515def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3516 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3517 MSA128BOpnd:$ws, 3518 MSA128BOpnd:$wt)>; 3519 3520def XORI_B : XORI_B_ENC, XORI_B_DESC; 3521 3522// Patterns. 3523class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3524 Pat<pattern, result>, Requires<pred>; 3525 3526def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3527 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3528 3529def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; 3530def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; 3531def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; 3532 3533def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), 3534 (ST_H MSA128H:$ws, addrimm10:$addr)>; 3535def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), 3536 (ST_W MSA128W:$ws, addrimm10:$addr)>; 3537def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), 3538 (ST_D MSA128D:$ws, addrimm10:$addr)>; 3539 3540class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3541 RegisterOperand ROWS = ROWD, 3542 InstrItinClass itin = NoItinerary> : 3543 MSAPseudo<(outs ROWD:$wd), 3544 (ins ROWS:$ws), 3545 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3546 InstrItinClass Itinerary = itin; 3547} 3548def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3549 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3550 MSA128WOpnd:$ws)>; 3551def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3552 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3553 MSA128DOpnd:$ws)>; 3554 3555class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3556 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3557 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3558 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3559 3560// These are endian-independent because the element size doesnt change 3561def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3562def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3563def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3564def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3565def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3566def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3567 3568// Little endian bitcasts are always no-ops 3569def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3570def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3571def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3572def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3573def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3574def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3575 3576def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3577def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3578def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3579def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3580def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3581 3582def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3583def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3584def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3585def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3586def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3587 3588def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3589def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3590def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3591def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3592def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3593 3594def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3595def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3596def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3597def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3598def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3599 3600def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3601def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3602def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3603def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3604def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3605 3606// Big endian bitcasts expand to shuffle instructions. 3607// This is because bitcast is defined to be a store/load sequence and the 3608// vector store/load instructions are mixed-endian with respect to the vector 3609// as a whole (little endian with respect to element order, but big endian 3610// elements). 3611 3612class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3613 RegisterClass DstRC, MSAInst Insn, 3614 RegisterClass ViaRC> : 3615 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3616 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3617 DstRC), 3618 [HasMSA, IsBE]>; 3619 3620class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3621 RegisterClass DstRC, MSAInst Insn, 3622 RegisterClass ViaRC> : 3623 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3624 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3625 DstRC), 3626 [HasMSA, IsBE]>; 3627 3628class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3629 RegisterClass DstRC> : 3630 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3631 3632class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3633 RegisterClass DstRC> : 3634 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3635 3636class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3637 RegisterClass DstRC> : 3638 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3639 (COPY_TO_REGCLASS 3640 (SHF_W 3641 (COPY_TO_REGCLASS 3642 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3643 MSA128W), 177), 3644 DstRC), 3645 [HasMSA, IsBE]>; 3646 3647class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3648 RegisterClass DstRC> : 3649 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3650 3651class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3652 RegisterClass DstRC> : 3653 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3654 3655class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3656 RegisterClass DstRC> : 3657 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3658 3659def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3660def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3661def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3662def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3663def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3664def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3665 3666def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3667def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3668def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3669def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3670def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3671 3672def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3673def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3674def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3675def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3676def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3677 3678def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3679def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3680def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3681def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3682def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3683 3684def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3685def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3686def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3687def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3688def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3689 3690def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3691def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3692def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3693def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3694def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3695 3696def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3697def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3698def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3699def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3700def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3701 3702// Pseudos used to implement BNZ.df, and BZ.df 3703 3704class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3705 RegisterClass RCWS, 3706 InstrItinClass itin = NoItinerary> : 3707 MipsPseudo<(outs GPR32:$dst), 3708 (ins RCWS:$ws), 3709 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3710 bit usesCustomInserter = 1; 3711} 3712 3713def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3714 MSA128B, NoItinerary>; 3715def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3716 MSA128H, NoItinerary>; 3717def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3718 MSA128W, NoItinerary>; 3719def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3720 MSA128D, NoItinerary>; 3721def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3722 MSA128B, NoItinerary>; 3723 3724def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3725 MSA128B, NoItinerary>; 3726def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3727 MSA128H, NoItinerary>; 3728def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3729 MSA128W, NoItinerary>; 3730def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3731 MSA128D, NoItinerary>; 3732def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3733 MSA128B, NoItinerary>; 3734