MipsRegisterInfo.cpp revision 1d165f1c252d1541b4788bf81092a9299cc764e5
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MIPS implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-reg-info" 15 16#include "MipsRegisterInfo.h" 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsInstrInfo.h" 20#include "MipsSubtarget.h" 21#include "MipsMachineFunction.h" 22#include "llvm/Constants.h" 23#include "llvm/DebugInfo.h" 24#include "llvm/Type.h" 25#include "llvm/Function.h" 26#include "llvm/CodeGen/ValueTypes.h" 27#include "llvm/CodeGen/MachineInstrBuilder.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/Target/TargetFrameLowering.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/Target/TargetInstrInfo.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/STLExtras.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "MipsGenRegisterInfo.inc" 43 44using namespace llvm; 45 46MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, 47 const TargetInstrInfo &tii) 48 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {} 49 50unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 51 52//===----------------------------------------------------------------------===// 53// Callee Saved Registers methods 54//===----------------------------------------------------------------------===// 55 56/// Mips Callee Saved Registers 57const uint16_t* MipsRegisterInfo:: 58getCalleeSavedRegs(const MachineFunction *MF) const { 59 if (Subtarget.isSingleFloat()) 60 return CSR_SingleFloatOnly_SaveList; 61 else if (!Subtarget.hasMips64()) 62 return CSR_O32_SaveList; 63 else if (Subtarget.isABI_N32()) 64 return CSR_N32_SaveList; 65 66 assert(Subtarget.isABI_N64()); 67 return CSR_N64_SaveList; 68} 69 70const uint32_t* 71MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 72 if (Subtarget.isSingleFloat()) 73 return CSR_SingleFloatOnly_RegMask; 74 else if (!Subtarget.hasMips64()) 75 return CSR_O32_RegMask; 76 else if (Subtarget.isABI_N32()) 77 return CSR_N32_RegMask; 78 79 assert(Subtarget.isABI_N64()); 80 return CSR_N64_RegMask; 81} 82 83BitVector MipsRegisterInfo:: 84getReservedRegs(const MachineFunction &MF) const { 85 static const uint16_t ReservedCPURegs[] = { 86 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP 87 }; 88 89 static const uint16_t ReservedCPU64Regs[] = { 90 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 91 }; 92 93 BitVector Reserved(getNumRegs()); 94 typedef TargetRegisterClass::const_iterator RegIter; 95 96 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) 97 Reserved.set(ReservedCPURegs[I]); 98 99 if (Subtarget.hasMips64()) { 100 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) 101 Reserved.set(ReservedCPU64Regs[I]); 102 103 // Reserve all registers in AFGR64. 104 for (RegIter Reg = Mips::AFGR64RegClass.begin(), 105 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 106 Reserved.set(*Reg); 107 } else { 108 // Reserve all registers in CPU64Regs & FGR64. 109 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(), 110 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg) 111 Reserved.set(*Reg); 112 113 for (RegIter Reg = Mips::FGR64RegClass.begin(), 114 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) 115 Reserved.set(*Reg); 116 } 117 118 // Reserve FP if this function should have a dedicated frame pointer register. 119 if (MF.getTarget().getFrameLowering()->hasFP(MF)) { 120 Reserved.set(Mips::FP); 121 Reserved.set(Mips::FP_64); 122 } 123 124 // Reserve hardware registers. 125 Reserved.set(Mips::HWR29); 126 Reserved.set(Mips::HWR29_64); 127 128 // Reserve RA if in mips16 mode. 129 if (Subtarget.inMips16Mode()) { 130 Reserved.set(Mips::RA); 131 Reserved.set(Mips::RA_64); 132 } 133 134 return Reserved; 135} 136 137bool 138MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 139 return true; 140} 141 142bool 143MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 144 return true; 145} 146 147// This function eliminate ADJCALLSTACKDOWN, 148// ADJCALLSTACKUP pseudo instructions 149void MipsRegisterInfo:: 150eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 151 MachineBasicBlock::iterator I) const { 152 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 153 MBB.erase(I); 154} 155 156// FrameIndex represent objects inside a abstract stack. 157// We must replace FrameIndex with an stack/frame pointer 158// direct reference. 159void MipsRegisterInfo:: 160eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 161 RegScavenger *RS) const { 162 MachineInstr &MI = *II; 163 MachineFunction &MF = *MI.getParent()->getParent(); 164 MachineFrameInfo *MFI = MF.getFrameInfo(); 165 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 166 167 unsigned i = 0; 168 while (!MI.getOperand(i).isFI()) { 169 ++i; 170 assert(i < MI.getNumOperands() && 171 "Instr doesn't have FrameIndex operand!"); 172 } 173 174 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n"; 175 errs() << "<--------->\n" << MI); 176 177 int FrameIndex = MI.getOperand(i).getIndex(); 178 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 179 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 180 181 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 182 << "spOffset : " << spOffset << "\n" 183 << "stackSize : " << stackSize << "\n"); 184 185 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 186 int MinCSFI = 0; 187 int MaxCSFI = -1; 188 189 if (CSI.size()) { 190 MinCSFI = CSI[0].getFrameIdx(); 191 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 192 } 193 194 // The following stack frame objects are always referenced relative to $sp: 195 // 1. Outgoing arguments. 196 // 2. Pointer to dynamically allocated stack space. 197 // 3. Locations for callee-saved registers. 198 // Everything else is referenced relative to whatever register 199 // getFrameRegister() returns. 200 unsigned FrameReg; 201 202 if (MipsFI->isOutArgFI(FrameIndex) || 203 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) 204 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 205 else 206 FrameReg = getFrameRegister(MF); 207 208 // Calculate final offset. 209 // - There is no need to change the offset if the frame object is one of the 210 // following: an outgoing argument, pointer to a dynamically allocated 211 // stack space or a $gp restore location, 212 // - If the frame object is any of the following, its offset must be adjusted 213 // by adding the size of the stack: 214 // incoming argument, callee-saved register location or local variable. 215 int64_t Offset; 216 217 if (MipsFI->isOutArgFI(FrameIndex)) 218 Offset = spOffset; 219 else 220 Offset = spOffset + (int64_t)stackSize; 221 222 Offset += MI.getOperand(i+1).getImm(); 223 224 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 225 226 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate 227 // field. 228 if (!MI.isDebugValue() && !isInt<16>(Offset)) { 229 MachineBasicBlock &MBB = *MI.getParent(); 230 DebugLoc DL = II->getDebugLoc(); 231 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 232 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT; 233 MipsAnalyzeImmediate::Inst LastInst(0, 0); 234 235 MipsFI->setEmitNOAT(); 236 Mips::loadImmediate(Offset, Subtarget.isABI_N64(), TII, MBB, II, DL, true, 237 &LastInst); 238 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg); 239 240 FrameReg = ATReg; 241 Offset = SignExtend64<16>(LastInst.ImmOpnd); 242 } 243 244 MI.getOperand(i).ChangeToRegister(FrameReg, false); 245 MI.getOperand(i+1).ChangeToImmediate(Offset); 246} 247 248unsigned MipsRegisterInfo:: 249getFrameRegister(const MachineFunction &MF) const { 250 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 251 bool IsN64 = Subtarget.isABI_N64(); 252 253 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 254 (IsN64 ? Mips::SP_64 : Mips::SP); 255} 256 257unsigned MipsRegisterInfo:: 258getEHExceptionRegister() const { 259 llvm_unreachable("What is the exception register"); 260} 261 262unsigned MipsRegisterInfo:: 263getEHHandlerRegister() const { 264 llvm_unreachable("What is the exception handler register"); 265} 266