MipsRegisterInfo.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MIPS implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-reg-info" 15 16#include "MipsRegisterInfo.h" 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsInstrInfo.h" 20#include "MipsMachineFunction.h" 21#include "MipsSubtarget.h" 22#include "llvm/ADT/BitVector.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/IR/Constants.h" 28#include "llvm/IR/DebugInfo.h" 29#include "llvm/IR/Function.h" 30#include "llvm/IR/Type.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameLowering.h" 36#include "llvm/Target/TargetInstrInfo.h" 37#include "llvm/Target/TargetMachine.h" 38#include "llvm/Target/TargetOptions.h" 39 40#define GET_REGINFO_TARGET_DESC 41#include "MipsGenRegisterInfo.inc" 42 43using namespace llvm; 44 45MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST) 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 47 48unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 49 50const TargetRegisterClass * 51MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, 52 unsigned Kind) const { 53 return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 54} 55 56unsigned 57MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 58 MachineFunction &MF) const { 59 switch (RC->getID()) { 60 default: 61 return 0; 62 case Mips::GPR32RegClassID: 63 case Mips::GPR64RegClassID: 64 case Mips::DSPRRegClassID: { 65 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 66 return 28 - TFI->hasFP(MF); 67 } 68 case Mips::FGR32RegClassID: 69 return 32; 70 case Mips::AFGR64RegClassID: 71 return 16; 72 case Mips::FGR64RegClassID: 73 return 32; 74 } 75} 76 77//===----------------------------------------------------------------------===// 78// Callee Saved Registers methods 79//===----------------------------------------------------------------------===// 80 81/// Mips Callee Saved Registers 82const uint16_t* MipsRegisterInfo:: 83getCalleeSavedRegs(const MachineFunction *MF) const { 84 if (Subtarget.isSingleFloat()) 85 return CSR_SingleFloatOnly_SaveList; 86 87 if (Subtarget.isABI_N64()) 88 return CSR_N64_SaveList; 89 90 if (Subtarget.isABI_N32()) 91 return CSR_N32_SaveList; 92 93 if (Subtarget.isFP64bit()) 94 return CSR_O32_FP64_SaveList; 95 96 return CSR_O32_SaveList; 97} 98 99const uint32_t* 100MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 101 if (Subtarget.isSingleFloat()) 102 return CSR_SingleFloatOnly_RegMask; 103 104 if (Subtarget.isABI_N64()) 105 return CSR_N64_RegMask; 106 107 if (Subtarget.isABI_N32()) 108 return CSR_N32_RegMask; 109 110 if (Subtarget.isFP64bit()) 111 return CSR_O32_FP64_RegMask; 112 113 return CSR_O32_RegMask; 114} 115 116const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() { 117 return CSR_Mips16RetHelper_RegMask; 118} 119 120BitVector MipsRegisterInfo:: 121getReservedRegs(const MachineFunction &MF) const { 122 static const uint16_t ReservedGPR32[] = { 123 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP 124 }; 125 126 static const uint16_t ReservedGPR64[] = { 127 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 128 }; 129 130 BitVector Reserved(getNumRegs()); 131 typedef TargetRegisterClass::const_iterator RegIter; 132 133 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) 134 Reserved.set(ReservedGPR32[I]); 135 136 // Reserve registers for the NaCl sandbox. 137 if (Subtarget.isTargetNaCl()) { 138 Reserved.set(Mips::T6); // Reserved for control flow mask. 139 Reserved.set(Mips::T7); // Reserved for memory access mask. 140 Reserved.set(Mips::T8); // Reserved for thread pointer. 141 } 142 143 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) 144 Reserved.set(ReservedGPR64[I]); 145 146 if (Subtarget.isFP64bit()) { 147 // Reserve all registers in AFGR64. 148 for (RegIter Reg = Mips::AFGR64RegClass.begin(), 149 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 150 Reserved.set(*Reg); 151 } else { 152 // Reserve all registers in FGR64. 153 for (RegIter Reg = Mips::FGR64RegClass.begin(), 154 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) 155 Reserved.set(*Reg); 156 } 157 // Reserve FP if this function should have a dedicated frame pointer register. 158 if (MF.getTarget().getFrameLowering()->hasFP(MF)) { 159 if (Subtarget.inMips16Mode()) 160 Reserved.set(Mips::S0); 161 else { 162 Reserved.set(Mips::FP); 163 Reserved.set(Mips::FP_64); 164 } 165 } 166 167 // Reserve hardware registers. 168 Reserved.set(Mips::HWR29); 169 170 // Reserve DSP control register. 171 Reserved.set(Mips::DSPPos); 172 Reserved.set(Mips::DSPSCount); 173 Reserved.set(Mips::DSPCarry); 174 Reserved.set(Mips::DSPEFI); 175 Reserved.set(Mips::DSPOutFlag); 176 177 // Reserve MSA control registers. 178 Reserved.set(Mips::MSAIR); 179 Reserved.set(Mips::MSACSR); 180 Reserved.set(Mips::MSAAccess); 181 Reserved.set(Mips::MSASave); 182 Reserved.set(Mips::MSAModify); 183 Reserved.set(Mips::MSARequest); 184 Reserved.set(Mips::MSAMap); 185 Reserved.set(Mips::MSAUnmap); 186 187 // Reserve RA if in mips16 mode. 188 if (Subtarget.inMips16Mode()) { 189 const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 190 Reserved.set(Mips::RA); 191 Reserved.set(Mips::RA_64); 192 Reserved.set(Mips::T0); 193 Reserved.set(Mips::T1); 194 if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2()) 195 Reserved.set(Mips::S2); 196 } 197 198 // Reserve GP if small section is used. 199 if (Subtarget.useSmallSection()) { 200 Reserved.set(Mips::GP); 201 Reserved.set(Mips::GP_64); 202 } 203 204 return Reserved; 205} 206 207bool 208MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 209 return true; 210} 211 212bool 213MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 214 return true; 215} 216 217// FrameIndex represent objects inside a abstract stack. 218// We must replace FrameIndex with an stack/frame pointer 219// direct reference. 220void MipsRegisterInfo:: 221eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 222 unsigned FIOperandNum, RegScavenger *RS) const { 223 MachineInstr &MI = *II; 224 MachineFunction &MF = *MI.getParent()->getParent(); 225 226 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; 227 errs() << "<--------->\n" << MI); 228 229 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 230 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 231 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 232 233 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 234 << "spOffset : " << spOffset << "\n" 235 << "stackSize : " << stackSize << "\n"); 236 237 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); 238} 239 240unsigned MipsRegisterInfo:: 241getFrameRegister(const MachineFunction &MF) const { 242 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 243 bool IsN64 = Subtarget.isABI_N64(); 244 245 if (Subtarget.inMips16Mode()) 246 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; 247 else 248 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 249 (IsN64 ? Mips::SP_64 : Mips::SP); 250 251} 252 253