MipsRegisterInfo.cpp revision 46090914b783b632618268f2a5c99aab83732688
15f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 25f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 35f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// The LLVM Compiler Infrastructure 45f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 55f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// This file is distributed under the University of Illinois Open Source 65f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// License. See LICENSE.TXT for details. 75f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 85f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 95f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 105f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// This file contains the MIPS implementation of the TargetRegisterInfo class. 115f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 125f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 135f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 145f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#define DEBUG_TYPE "mips-reg-info" 155f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 165f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "MipsRegisterInfo.h" 175f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "Mips.h" 185f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "MipsAnalyzeImmediate.h" 19464175bba1318bef7905122e9fda20cff926df78Chris Lattner#include "MipsInstrInfo.h" 20464175bba1318bef7905122e9fda20cff926df78Chris Lattner#include "MipsMachineFunction.h" 21464175bba1318bef7905122e9fda20cff926df78Chris Lattner#include "MipsSubtarget.h" 225f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/ADT/BitVector.h" 235f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/ADT/STLExtras.h" 245f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/MachineFrameInfo.h" 255f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/MachineFunction.h" 265f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/MachineInstrBuilder.h" 275f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/ValueTypes.h" 285f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/DebugInfo.h" 295f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/IR/Constants.h" 305f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/IR/Type.h" 315f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Support/CommandLine.h" 325f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Support/Debug.h" 335f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Support/ErrorHandling.h" 345f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Support/raw_ostream.h" 355f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Target/TargetFrameLowering.h" 365f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Target/TargetInstrInfo.h" 375f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Target/TargetMachine.h" 38464175bba1318bef7905122e9fda20cff926df78Chris Lattner#include "llvm/Target/TargetOptions.h" 395f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 405f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#define GET_REGINFO_TARGET_DESC 415f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "MipsGenRegisterInfo.inc" 425f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 435f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerusing namespace llvm; 445f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 455f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerMipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST) 465f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 475f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 485f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerunsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 495f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 505f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 515f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerunsigned 525f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerMipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 535f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer MachineFunction &MF) const { 545f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer switch (RC->getID()) { 555f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer default: 565f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return 0; 575f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer case Mips::CPURegsRegClassID: 585f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer case Mips::CPU64RegsRegClassID: 595f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer case Mips::DSPRegsRegClassID: { 60d2d2a11a91d7ddf468bfb70f66362d24806ed601Chris Lattner const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 61464175bba1318bef7905122e9fda20cff926df78Chris Lattner return 28 - TFI->hasFP(MF); 62464175bba1318bef7905122e9fda20cff926df78Chris Lattner } 63464175bba1318bef7905122e9fda20cff926df78Chris Lattner case Mips::FGR32RegClassID: 64d2d2a11a91d7ddf468bfb70f66362d24806ed601Chris Lattner return 32; 655f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer case Mips::AFGR64RegClassID: 665f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return 16; 675f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer case Mips::FGR64RegClassID: 685f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return 32; 695f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer } 705f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 715f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 725f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 735f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// Callee Saved Registers methods 745f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 755f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 765f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// Mips Callee Saved Registers 775f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerconst uint16_t* MipsRegisterInfo:: 785f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencergetCalleeSavedRegs(const MachineFunction *MF) const { 795f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (Subtarget.isSingleFloat()) 805f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_SingleFloatOnly_SaveList; 815f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else if (!Subtarget.hasMips64()) 825f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_O32_SaveList; 835f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else if (Subtarget.isABI_N32()) 845f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_N32_SaveList; 855f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 865f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer assert(Subtarget.isABI_N64()); 875f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_N64_SaveList; 885f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 895f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 905f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerconst uint32_t* 915f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerMipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 925f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (Subtarget.isSingleFloat()) 935f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_SingleFloatOnly_RegMask; 945f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else if (!Subtarget.hasMips64()) 955f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_O32_RegMask; 965f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else if (Subtarget.isABI_N32()) 975f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_N32_RegMask; 985f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 995f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer assert(Subtarget.isABI_N64()); 1005f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_N64_RegMask; 1015f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 1025f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 1035f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerconst uint32_t *MipsRegisterInfo::getMips16RetHelperMask() { 1045f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return CSR_Mips16RetHelper_RegMask; 1055f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 1065f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 1075f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerBitVector MipsRegisterInfo:: 1088b9023ba35a86838789e2c9034a6128728c547aaChris LattnergetReservedRegs(const MachineFunction &MF) const { 1098b9023ba35a86838789e2c9034a6128728c547aaChris Lattner static const uint16_t ReservedCPURegs[] = { 1108b9023ba35a86838789e2c9034a6128728c547aaChris Lattner Mips::ZERO, Mips::K0, Mips::K1, Mips::SP 1118b9023ba35a86838789e2c9034a6128728c547aaChris Lattner }; 112464175bba1318bef7905122e9fda20cff926df78Chris Lattner 113464175bba1318bef7905122e9fda20cff926df78Chris Lattner static const uint16_t ReservedCPU64Regs[] = { 114464175bba1318bef7905122e9fda20cff926df78Chris Lattner Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 115464175bba1318bef7905122e9fda20cff926df78Chris Lattner }; 116464175bba1318bef7905122e9fda20cff926df78Chris Lattner 117464175bba1318bef7905122e9fda20cff926df78Chris Lattner BitVector Reserved(getNumRegs()); 118464175bba1318bef7905122e9fda20cff926df78Chris Lattner typedef TargetRegisterClass::const_iterator RegIter; 119464175bba1318bef7905122e9fda20cff926df78Chris Lattner 120464175bba1318bef7905122e9fda20cff926df78Chris Lattner for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) 121464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(ReservedCPURegs[I]); 122464175bba1318bef7905122e9fda20cff926df78Chris Lattner 123464175bba1318bef7905122e9fda20cff926df78Chris Lattner for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) 124464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(ReservedCPU64Regs[I]); 125464175bba1318bef7905122e9fda20cff926df78Chris Lattner 126464175bba1318bef7905122e9fda20cff926df78Chris Lattner if (Subtarget.hasMips64()) { 127464175bba1318bef7905122e9fda20cff926df78Chris Lattner // Reserve all registers in AFGR64. 128464175bba1318bef7905122e9fda20cff926df78Chris Lattner for (RegIter Reg = Mips::AFGR64RegClass.begin(), 129464175bba1318bef7905122e9fda20cff926df78Chris Lattner EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 130464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(*Reg); 131464175bba1318bef7905122e9fda20cff926df78Chris Lattner } else { 132464175bba1318bef7905122e9fda20cff926df78Chris Lattner // Reserve all registers in FGR64. 133464175bba1318bef7905122e9fda20cff926df78Chris Lattner for (RegIter Reg = Mips::FGR64RegClass.begin(), 134464175bba1318bef7905122e9fda20cff926df78Chris Lattner EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) 135464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(*Reg); 136464175bba1318bef7905122e9fda20cff926df78Chris Lattner } 137464175bba1318bef7905122e9fda20cff926df78Chris Lattner // Reserve FP if this function should have a dedicated frame pointer register. 138464175bba1318bef7905122e9fda20cff926df78Chris Lattner if (MF.getTarget().getFrameLowering()->hasFP(MF)) { 139464175bba1318bef7905122e9fda20cff926df78Chris Lattner if (Subtarget.inMips16Mode()) 140464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(Mips::S0); 1415f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else { 1425f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::FP); 1435f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::FP_64); 1445f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer } 145464175bba1318bef7905122e9fda20cff926df78Chris Lattner } 146464175bba1318bef7905122e9fda20cff926df78Chris Lattner 147464175bba1318bef7905122e9fda20cff926df78Chris Lattner // Reserve hardware registers. 1485f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::HWR29); 1495f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::HWR29_64); 150464175bba1318bef7905122e9fda20cff926df78Chris Lattner 151464175bba1318bef7905122e9fda20cff926df78Chris Lattner // Reserve DSP control register. 1525f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::DSPPos); 1535f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::DSPSCount); 154464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(Mips::DSPCarry); 155464175bba1318bef7905122e9fda20cff926df78Chris Lattner Reserved.set(Mips::DSPEFI); 1565f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::DSPOutFlag); 1575f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 1585f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // Reserve RA if in mips16 mode. 1595f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (Subtarget.inMips16Mode()) { 1605f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::RA); 1615f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::RA_64); 1625f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer } 1635f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 1645f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // Reserve GP if small section is used. 1655f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (Subtarget.useSmallSection()) { 1665f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::GP); 1675f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer Reserved.set(Mips::GP_64); 1685f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer } 169 170 return Reserved; 171} 172 173bool 174MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 175 return true; 176} 177 178bool 179MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 180 return true; 181} 182 183// FrameIndex represent objects inside a abstract stack. 184// We must replace FrameIndex with an stack/frame pointer 185// direct reference. 186void MipsRegisterInfo:: 187eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 188 unsigned FIOperandNum, RegScavenger *RS) const { 189 MachineInstr &MI = *II; 190 MachineFunction &MF = *MI.getParent()->getParent(); 191 192 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; 193 errs() << "<--------->\n" << MI); 194 195 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 196 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 197 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 198 199 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 200 << "spOffset : " << spOffset << "\n" 201 << "stackSize : " << stackSize << "\n"); 202 203 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); 204} 205 206unsigned MipsRegisterInfo:: 207getFrameRegister(const MachineFunction &MF) const { 208 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 209 bool IsN64 = Subtarget.isABI_N64(); 210 211 if (Subtarget.inMips16Mode()) 212 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; 213 else 214 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 215 (IsN64 ? Mips::SP_64 : Mips::SP); 216 217} 218 219unsigned MipsRegisterInfo:: 220getEHExceptionRegister() const { 221 llvm_unreachable("What is the exception register"); 222} 223 224unsigned MipsRegisterInfo:: 225getEHHandlerRegister() const { 226 llvm_unreachable("What is the exception handler register"); 227} 228