MipsRegisterInfo.cpp revision 71746220d3d1c3e8efba35038ac2ff14b4a4d3ae 
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "MipsRegisterInfo.h"
17#include "Mips.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsInstrInfo.h"
20#include "MipsSubtarget.h"
21#include "MipsMachineFunction.h"
22#include "llvm/Constants.h"
23#include "llvm/DebugInfo.h"
24#include "llvm/Type.h"
25#include "llvm/Function.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/Target/TargetFrameLowering.h"
31#include "llvm/Target/TargetMachine.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/Target/TargetInstrInfo.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/STLExtras.h"
40
41#define GET_REGINFO_TARGET_DESC
42#include "MipsGenRegisterInfo.inc"
43
44using namespace llvm;
45
46MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
47                                   const TargetInstrInfo &tii)
48  : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49
50unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
51
52//===----------------------------------------------------------------------===//
53// Callee Saved Registers methods
54//===----------------------------------------------------------------------===//
55
56/// Mips Callee Saved Registers
57const uint16_t* MipsRegisterInfo::
58getCalleeSavedRegs(const MachineFunction *MF) const {
59  if (Subtarget.isSingleFloat())
60    return CSR_SingleFloatOnly_SaveList;
61  else if (!Subtarget.hasMips64())
62    return CSR_O32_SaveList;
63  else if (Subtarget.isABI_N32())
64    return CSR_N32_SaveList;
65
66  assert(Subtarget.isABI_N64());
67  return CSR_N64_SaveList;
68}
69
70const uint32_t*
71MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
72  if (Subtarget.isSingleFloat())
73    return CSR_SingleFloatOnly_RegMask;
74  else if (!Subtarget.hasMips64())
75    return CSR_O32_RegMask;
76  else if (Subtarget.isABI_N32())
77    return CSR_N32_RegMask;
78
79  assert(Subtarget.isABI_N64());
80  return CSR_N64_RegMask;
81}
82
83BitVector MipsRegisterInfo::
84getReservedRegs(const MachineFunction &MF) const {
85  static const uint16_t ReservedCPURegs[] = {
86    Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP
87  };
88
89  static const uint16_t ReservedCPU64Regs[] = {
90    Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
91  };
92
93  BitVector Reserved(getNumRegs());
94  typedef TargetRegisterClass::const_iterator RegIter;
95
96  for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
97    Reserved.set(ReservedCPURegs[I]);
98
99  if (Subtarget.hasMips64()) {
100    for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
101      Reserved.set(ReservedCPU64Regs[I]);
102
103    // Reserve all registers in AFGR64.
104    for (RegIter Reg = Mips::AFGR64RegClass.begin(),
105         EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
106      Reserved.set(*Reg);
107  } else {
108    // Reserve all registers in CPU64Regs & FGR64.
109    for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
110         EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
111      Reserved.set(*Reg);
112
113    for (RegIter Reg = Mips::FGR64RegClass.begin(),
114         EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
115      Reserved.set(*Reg);
116  }
117
118  // Reserve FP if this function should have a dedicated frame pointer register.
119  if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
120    Reserved.set(Mips::FP);
121    Reserved.set(Mips::FP_64);
122  }
123
124  // Reserve hardware registers.
125  Reserved.set(Mips::HWR29);
126  Reserved.set(Mips::HWR29_64);
127
128  // Reserve RA if in mips16 mode.
129  if (Subtarget.inMips16Mode()) {
130    Reserved.set(Mips::RA);
131    Reserved.set(Mips::RA_64);
132  }
133
134  return Reserved;
135}
136
137bool
138MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
139  return true;
140}
141
142bool
143MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
144  return true;
145}
146
147// FrameIndex represent objects inside a abstract stack.
148// We must replace FrameIndex with an stack/frame pointer
149// direct reference.
150void MipsRegisterInfo::
151eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
152                    RegScavenger *RS) const {
153  MachineInstr &MI = *II;
154  MachineFunction &MF = *MI.getParent()->getParent();
155
156  unsigned i = 0;
157  while (!MI.getOperand(i).isFI()) {
158    ++i;
159    assert(i < MI.getNumOperands() &&
160           "Instr doesn't have FrameIndex operand!");
161  }
162
163  DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
164        errs() << "<--------->\n" << MI);
165
166  int FrameIndex = MI.getOperand(i).getIndex();
167  uint64_t stackSize = MF.getFrameInfo()->getStackSize();
168  int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
169
170  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
171               << "spOffset   : " << spOffset << "\n"
172               << "stackSize  : " << stackSize << "\n");
173
174  eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
175}
176
177unsigned MipsRegisterInfo::
178getFrameRegister(const MachineFunction &MF) const {
179  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
180  bool IsN64 = Subtarget.isABI_N64();
181
182  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
183                          (IsN64 ? Mips::SP_64 : Mips::SP);
184}
185
186unsigned MipsRegisterInfo::
187getEHExceptionRegister() const {
188  llvm_unreachable("What is the exception register");
189}
190
191unsigned MipsRegisterInfo::
192getEHHandlerRegister() const {
193  llvm_unreachable("What is the exception handler register");
194}
195