MipsRegisterInfo.cpp revision f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5 
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "MipsRegisterInfo.h"
17#include "Mips.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsInstrInfo.h"
20#include "MipsSubtarget.h"
21#include "MipsMachineFunction.h"
22#include "llvm/Constants.h"
23#include "llvm/DebugInfo.h"
24#include "llvm/Type.h"
25#include "llvm/CodeGen/ValueTypes.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/Target/TargetFrameLowering.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Target/TargetInstrInfo.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/STLExtras.h"
39
40#define GET_REGINFO_TARGET_DESC
41#include "MipsGenRegisterInfo.inc"
42
43using namespace llvm;
44
45MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46  : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
47
48unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49
50//===----------------------------------------------------------------------===//
51// Callee Saved Registers methods
52//===----------------------------------------------------------------------===//
53
54/// Mips Callee Saved Registers
55const uint16_t* MipsRegisterInfo::
56getCalleeSavedRegs(const MachineFunction *MF) const {
57  if (Subtarget.isSingleFloat())
58    return CSR_SingleFloatOnly_SaveList;
59  else if (!Subtarget.hasMips64())
60    return CSR_O32_SaveList;
61  else if (Subtarget.isABI_N32())
62    return CSR_N32_SaveList;
63
64  assert(Subtarget.isABI_N64());
65  return CSR_N64_SaveList;
66}
67
68const uint32_t*
69MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
70  if (Subtarget.isSingleFloat())
71    return CSR_SingleFloatOnly_RegMask;
72  else if (!Subtarget.hasMips64())
73    return CSR_O32_RegMask;
74  else if (Subtarget.isABI_N32())
75    return CSR_N32_RegMask;
76
77  assert(Subtarget.isABI_N64());
78  return CSR_N64_RegMask;
79}
80
81BitVector MipsRegisterInfo::
82getReservedRegs(const MachineFunction &MF) const {
83  static const uint16_t ReservedCPURegs[] = {
84    Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP
85  };
86
87  static const uint16_t ReservedCPU64Regs[] = {
88    Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
89  };
90
91  BitVector Reserved(getNumRegs());
92  typedef TargetRegisterClass::const_iterator RegIter;
93
94  for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
95    Reserved.set(ReservedCPURegs[I]);
96
97  if (Subtarget.hasMips64()) {
98    for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
99      Reserved.set(ReservedCPU64Regs[I]);
100
101    // Reserve all registers in AFGR64.
102    for (RegIter Reg = Mips::AFGR64RegClass.begin(),
103         EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
104      Reserved.set(*Reg);
105  } else {
106    // Reserve all registers in CPU64Regs & FGR64.
107    for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
108         EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
109      Reserved.set(*Reg);
110
111    for (RegIter Reg = Mips::FGR64RegClass.begin(),
112         EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
113      Reserved.set(*Reg);
114  }
115  // Reserve FP if this function should have a dedicated frame pointer register.
116  if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
117    if (Subtarget.inMips16Mode())
118      Reserved.set(Mips::S0);
119    else {
120      Reserved.set(Mips::FP);
121      Reserved.set(Mips::FP_64);
122    }
123  }
124
125  // Reserve hardware registers.
126  Reserved.set(Mips::HWR29);
127  Reserved.set(Mips::HWR29_64);
128
129  // Reserve DSP control register.
130  Reserved.set(Mips::DSPCtrl);
131
132  // Reserve RA if in mips16 mode.
133  if (Subtarget.inMips16Mode()) {
134    Reserved.set(Mips::RA);
135    Reserved.set(Mips::RA_64);
136  }
137
138  // Reserve GP if small section is used.
139  if (Subtarget.useSmallSection()) {
140    Reserved.set(Mips::GP);
141    Reserved.set(Mips::GP_64);
142  }
143
144  return Reserved;
145}
146
147bool
148MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
149  return true;
150}
151
152bool
153MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
154  return true;
155}
156
157// FrameIndex represent objects inside a abstract stack.
158// We must replace FrameIndex with an stack/frame pointer
159// direct reference.
160void MipsRegisterInfo::
161eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
162                    RegScavenger *RS) const {
163  MachineInstr &MI = *II;
164  MachineFunction &MF = *MI.getParent()->getParent();
165
166  unsigned i = 0;
167  while (!MI.getOperand(i).isFI()) {
168    ++i;
169    assert(i < MI.getNumOperands() &&
170           "Instr doesn't have FrameIndex operand!");
171  }
172
173  DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
174        errs() << "<--------->\n" << MI);
175
176  int FrameIndex = MI.getOperand(i).getIndex();
177  uint64_t stackSize = MF.getFrameInfo()->getStackSize();
178  int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
179
180  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
181               << "spOffset   : " << spOffset << "\n"
182               << "stackSize  : " << stackSize << "\n");
183
184  eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
185}
186
187unsigned MipsRegisterInfo::
188getFrameRegister(const MachineFunction &MF) const {
189  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
190  bool IsN64 = Subtarget.isABI_N64();
191
192  if (Subtarget.inMips16Mode())
193    return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
194  else
195    return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
196                            (IsN64 ? Mips::SP_64 : Mips::SP);
197
198}
199
200unsigned MipsRegisterInfo::
201getEHExceptionRegister() const {
202  llvm_unreachable("What is the exception register");
203}
204
205unsigned MipsRegisterInfo::
206getEHHandlerRegister() const {
207  llvm_unreachable("What is the exception handler register");
208}
209