MipsRegisterInfo.td revision 1024f290d1c81dd23ec452455eff8589a4419032
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_fpeven : SubRegIndex; 15def sub_fpodd : SubRegIndex; 16def sub_32 : SubRegIndex; 17} 18 19// We have banks of 32 registers each. 20class MipsReg<string n> : Register<n> { 21 field bits<5> Num; 22 let Namespace = "Mips"; 23} 24 25class MipsRegWithSubRegs<string n, list<Register> subregs> 26 : RegisterWithSubRegs<n, subregs> { 27 field bits<5> Num; 28 let Namespace = "Mips"; 29} 30 31// Mips CPU Registers 32class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 33 let Num = num; 34} 35 36// Mips 64-bit CPU Registers 37class Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 38 : MipsRegWithSubRegs<n, subregs> { 39 let Num = num; 40 let SubRegIndices = [sub_32]; 41} 42 43// Mips 32-bit FPU Registers 44class FPR<bits<5> num, string n> : MipsReg<n> { 45 let Num = num; 46} 47 48// Mips 64-bit (aliased) FPU Registers 49class AFPR<bits<5> num, string n, list<Register> subregs> 50 : MipsRegWithSubRegs<n, subregs> { 51 let Num = num; 52 let SubRegIndices = [sub_fpeven, sub_fpodd]; 53 let CoveredBySubRegs = 1; 54} 55 56class AFPR64<bits<5> num, string n, list<Register> subregs> 57 : MipsRegWithSubRegs<n, subregs> { 58 let Num = num; 59 let SubRegIndices = [sub_32]; 60} 61 62// Mips Hardware Registers 63class HWR<bits<5> num, string n> : MipsReg<n> { 64 let Num = num; 65} 66 67//===----------------------------------------------------------------------===// 68// Registers 69//===----------------------------------------------------------------------===// 70 71let Namespace = "Mips" in { 72 // General Purpose Registers 73 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 74 def AT : MipsGPRReg< 1, "at">, DwarfRegNum<[1]>; 75 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 76 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 77 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 78 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 79 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 80 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 81 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 82 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 83 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 84 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 85 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 86 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 87 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 88 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 89 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 90 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 91 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 92 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 93 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 94 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 95 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 96 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 97 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 98 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 99 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 100 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 101 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 102 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 103 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 104 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 105 106 // General Purpose 64-bit Registers 107 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 108 def AT_64 : Mips64GPRReg< 1, "at", [AT]>, DwarfRegNum<[1]>; 109 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 110 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 111 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 112 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 113 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 114 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 115 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 116 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 117 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 118 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 119 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 120 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 121 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 122 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 123 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 124 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 125 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 126 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 127 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 128 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 129 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 130 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 131 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 132 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 133 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 134 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 135 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 136 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 137 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 138 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 139 140 /// Mips Single point precision FPU Registers 141 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 142 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 143 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 144 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 145 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 146 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 147 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 148 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 149 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 150 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 151 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 152 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 153 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 154 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 155 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 156 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 157 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 158 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 159 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 160 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 161 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 162 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 163 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 164 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 165 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 166 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 167 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 168 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 169 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 170 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 171 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 172 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 173 174 /// Mips Double point precision FPU Registers (aliased 175 /// with the single precision to hold 64 bit values) 176 def D0 : AFPR< 0, "f0", [F0, F1]>; 177 def D1 : AFPR< 2, "f2", [F2, F3]>; 178 def D2 : AFPR< 4, "f4", [F4, F5]>; 179 def D3 : AFPR< 6, "f6", [F6, F7]>; 180 def D4 : AFPR< 8, "f8", [F8, F9]>; 181 def D5 : AFPR<10, "f10", [F10, F11]>; 182 def D6 : AFPR<12, "f12", [F12, F13]>; 183 def D7 : AFPR<14, "f14", [F14, F15]>; 184 def D8 : AFPR<16, "f16", [F16, F17]>; 185 def D9 : AFPR<18, "f18", [F18, F19]>; 186 def D10 : AFPR<20, "f20", [F20, F21]>; 187 def D11 : AFPR<22, "f22", [F22, F23]>; 188 def D12 : AFPR<24, "f24", [F24, F25]>; 189 def D13 : AFPR<26, "f26", [F26, F27]>; 190 def D14 : AFPR<28, "f28", [F28, F29]>; 191 def D15 : AFPR<30, "f30", [F30, F31]>; 192 193 /// Mips Double point precision FPU Registers in MFP64 mode. 194 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 195 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 196 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 197 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 198 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 199 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 200 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 201 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 202 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 203 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 204 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 205 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 206 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 207 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 208 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 209 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 210 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 211 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 212 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 213 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 214 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 215 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 216 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 217 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 218 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 219 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 220 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 221 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 222 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 223 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 224 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 225 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 226 227 // Hi/Lo registers 228 def HI : Register<"hi">, DwarfRegNum<[64]>; 229 def LO : Register<"lo">, DwarfRegNum<[65]>; 230 231 let SubRegIndices = [sub_32] in { 232 def HI64 : RegisterWithSubRegs<"hi", [HI]>; 233 def LO64 : RegisterWithSubRegs<"lo", [LO]>; 234 } 235 236 // Status flags register 237 def FCR31 : Register<"31">; 238 239 // fcc0 register 240 def FCC0 : Register<"fcc0">; 241 242 // PC register 243 def PC : Register<"pc">; 244 245 // Hardware register $29 246 def HWR29 : Register<"29">; 247 def HWR29_64 : Register<"29">; 248 249 // Accum registers 250 def LO0 : Register<"ac0"> { 251 let Aliases = [LO]; 252 } 253 def HI0 : Register<"hi0"> { 254 let Aliases = [HI]; 255 } 256 def LO1 : Register<"ac1">; 257 def HI1 : Register<"hi1">; 258 def LO2 : Register<"ac2">; 259 def HI2 : Register<"hi2">; 260 def LO3 : Register<"ac3">; 261 def HI3 : Register<"hi3">; 262 263 let SubRegIndices = [sub_32] in { 264 def LO0_64 : RegisterWithSubRegs<"ac0", [LO0]> { 265 let Aliases = [LO64]; 266 } 267 def HI0_64 : RegisterWithSubRegs<"hi0", [HI0]> { 268 let Aliases = [HI64]; 269 } 270 def LO1_64 : RegisterWithSubRegs<"ac1", [LO1]>; 271 def HI1_64 : RegisterWithSubRegs<"hi1", [HI1]>; 272 def LO2_64 : RegisterWithSubRegs<"ac2", [LO2]>; 273 def HI2_64 : RegisterWithSubRegs<"hi2", [HI2]>; 274 def LO3_64 : RegisterWithSubRegs<"ac3", [LO3]>; 275 def HI3_64 : RegisterWithSubRegs<"hi3", [HI3]>; 276 } 277 278 def DSPCtrl : Register<"dspctrl">; 279} 280 281//===----------------------------------------------------------------------===// 282// Register Classes 283//===----------------------------------------------------------------------===// 284 285class CPURegsClass<list<ValueType> regTypes> : 286 RegisterClass<"Mips", regTypes, 32, (add 287 // Reserved 288 ZERO, AT, 289 // Return Values and Arguments 290 V0, V1, A0, A1, A2, A3, 291 // Not preserved across procedure calls 292 T0, T1, T2, T3, T4, T5, T6, T7, 293 // Callee save 294 S0, S1, S2, S3, S4, S5, S6, S7, 295 // Not preserved across procedure calls 296 T8, T9, 297 // Reserved 298 K0, K1, GP, SP, FP, RA)>; 299 300def CPURegs : CPURegsClass<[i32]>; 301def DSPRegs : CPURegsClass<[v4i8, v2i16]>; 302 303def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 304// Reserved 305 ZERO_64, AT_64, 306 // Return Values and Arguments 307 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 308 // Not preserved across procedure calls 309 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 310 // Callee save 311 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 312 // Not preserved across procedure calls 313 T8_64, T9_64, 314 // Reserved 315 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 316 317def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 318 // Return Values and Arguments 319 V0, V1, A0, A1, A2, A3, 320 // Callee save 321 S0, S1)>; 322 323def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; 324 325 326// 64bit fp: 327// * FGR64 - 32 64-bit registers 328// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 329// 330// 32bit fp: 331// * FGR32 - 16 32-bit even registers 332// * FGR32 - 32 32-bit registers (single float only mode) 333def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 334 335def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 336 // Return Values and Arguments 337 D0, D1, 338 // Not preserved across procedure calls 339 D2, D3, D4, D5, 340 // Return Values and Arguments 341 D6, D7, 342 // Not preserved across procedure calls 343 D8, D9, 344 // Callee save 345 D10, D11, D12, D13, D14, D15)>; 346 347def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 348 349// Condition Register for floating point operations 350def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; 351 352// Hi/Lo Registers 353def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 354def HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; 355 356// Hardware registers 357def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 358def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; 359 360// Accum Registers 361def HIRegs : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 362def LORegs : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 363 364def HI64Regs : RegisterClass<"Mips", [i64], 64, (sequence "HI%u_64", 0, 3)>; 365def LO64Regs : RegisterClass<"Mips", [i64], 64, (sequence "LO%u_64", 0, 3)>; 366