MipsRegisterInfo.td revision 23ed37a6b76e79272194fb46597f7280661b828f
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_fpeven : SubRegIndex<32>; 15def sub_fpodd : SubRegIndex<32, 32>; 16def sub_32 : SubRegIndex<32>; 17def sub_lo : SubRegIndex<32>; 18def sub_hi : SubRegIndex<32, 32>; 19def sub_dsp16_19 : SubRegIndex<4, 16>; 20def sub_dsp20 : SubRegIndex<1, 20>; 21def sub_dsp21 : SubRegIndex<1, 21>; 22def sub_dsp22 : SubRegIndex<1, 22>; 23def sub_dsp23 : SubRegIndex<1, 23>; 24} 25 26class Unallocatable { 27 bit isAllocatable = 0; 28} 29 30// We have banks of 32 registers each. 31class MipsReg<bits<16> Enc, string n> : Register<n> { 32 let HWEncoding = Enc; 33 let Namespace = "Mips"; 34} 35 36class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 37 : RegisterWithSubRegs<n, subregs> { 38 let HWEncoding = Enc; 39 let Namespace = "Mips"; 40} 41 42// Mips CPU Registers 43class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 44 45// Mips 64-bit CPU Registers 46class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 47 : MipsRegWithSubRegs<Enc, n, subregs> { 48 let SubRegIndices = [sub_32]; 49} 50 51// Mips 32-bit FPU Registers 52class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 53 54// Mips 64-bit (aliased) FPU Registers 55class AFPR<bits<16> Enc, string n, list<Register> subregs> 56 : MipsRegWithSubRegs<Enc, n, subregs> { 57 let SubRegIndices = [sub_fpeven, sub_fpodd]; 58 let CoveredBySubRegs = 1; 59} 60 61class AFPR64<bits<16> Enc, string n, list<Register> subregs> 62 : MipsRegWithSubRegs<Enc, n, subregs> { 63 let SubRegIndices = [sub_32]; 64} 65 66// Accumulator Registers 67class ACC<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_lo, sub_hi]; 70 let CoveredBySubRegs = 1; 71} 72 73// Mips Hardware Registers 74class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 75 76//===----------------------------------------------------------------------===// 77// Registers 78//===----------------------------------------------------------------------===// 79 80let Namespace = "Mips" in { 81 // General Purpose Registers 82 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 83 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 84 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 85 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 86 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 87 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 88 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 89 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 90 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 91 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 92 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 93 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 94 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 95 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 96 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 97 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 98 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 99 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 100 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 101 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 102 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 103 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 104 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 105 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 106 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 107 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 108 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 109 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 110 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 111 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 112 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 113 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 114 115 // General Purpose 64-bit Registers 116 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 117 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 118 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 119 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 120 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 121 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 122 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 123 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 124 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 125 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 126 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 127 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 128 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 129 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 130 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 131 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 132 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 133 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 134 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 135 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 136 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 137 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 138 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 139 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 140 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 141 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 142 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 143 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 144 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 145 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 146 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 147 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 148 149 /// Mips Single point precision FPU Registers 150 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 151 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 152 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 153 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 154 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 155 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 156 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 157 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 158 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 159 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 160 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 161 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 162 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 163 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 164 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 165 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 166 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 167 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 168 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 169 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 170 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 171 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 172 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 173 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 174 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 175 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 176 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 177 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 178 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 179 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 180 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 181 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 182 183 /// Mips Double point precision FPU Registers (aliased 184 /// with the single precision to hold 64 bit values) 185 def D0 : AFPR< 0, "f0", [F0, F1]>; 186 def D1 : AFPR< 2, "f2", [F2, F3]>; 187 def D2 : AFPR< 4, "f4", [F4, F5]>; 188 def D3 : AFPR< 6, "f6", [F6, F7]>; 189 def D4 : AFPR< 8, "f8", [F8, F9]>; 190 def D5 : AFPR<10, "f10", [F10, F11]>; 191 def D6 : AFPR<12, "f12", [F12, F13]>; 192 def D7 : AFPR<14, "f14", [F14, F15]>; 193 def D8 : AFPR<16, "f16", [F16, F17]>; 194 def D9 : AFPR<18, "f18", [F18, F19]>; 195 def D10 : AFPR<20, "f20", [F20, F21]>; 196 def D11 : AFPR<22, "f22", [F22, F23]>; 197 def D12 : AFPR<24, "f24", [F24, F25]>; 198 def D13 : AFPR<26, "f26", [F26, F27]>; 199 def D14 : AFPR<28, "f28", [F28, F29]>; 200 def D15 : AFPR<30, "f30", [F30, F31]>; 201 202 /// Mips Double point precision FPU Registers in MFP64 mode. 203 def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 204 def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 205 def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 206 def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 207 def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 208 def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 209 def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 210 def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 211 def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 212 def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 213 def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 214 def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 215 def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 216 def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 217 def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 218 def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 219 def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 220 def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 221 def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 222 def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 223 def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 224 def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 225 def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 226 def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 227 def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 228 def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 229 def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 230 def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 231 def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 232 def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 233 def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 234 def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 235 236 // Hi/Lo registers 237 def HI : Register<"ac0">, DwarfRegNum<[64]>; 238 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 239 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 240 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 241 def LO : Register<"ac0">, DwarfRegNum<[65]>; 242 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 243 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 244 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 245 246 let SubRegIndices = [sub_32] in { 247 def HI64 : RegisterWithSubRegs<"hi", [HI]>; 248 def LO64 : RegisterWithSubRegs<"lo", [LO]>; 249 } 250 251 // Status flags register 252 def FCR31 : Register<"31">; 253 254 // fcc0 register 255 def FCC0 : MipsReg<0, "fcc0">; 256 257 // PC register 258 def PC : Register<"pc">; 259 260 // Hardware register $29 261 def HWR29 : MipsReg<29, "29">; 262 def HWR29_64 : MipsReg<29, "29">; 263 264 // Accum registers 265 def AC0 : ACC<0, "ac0", [LO, HI]>; 266 def AC1 : ACC<1, "ac1", [LO1, HI1]>; 267 def AC2 : ACC<2, "ac2", [LO2, HI2]>; 268 def AC3 : ACC<3, "ac3", [LO3, HI3]>; 269 270 def AC0_64 : ACC<0, "ac0", [LO64, HI64]>; 271 272 // DSP-ASE control register fields. 273 def DSPPos : Register<"">; 274 def DSPSCount : Register<"">; 275 def DSPCarry : Register<"">; 276 def DSPEFI : Register<"">; 277 def DSPOutFlag16_19 : Register<"">; 278 def DSPOutFlag20 : Register<"">; 279 def DSPOutFlag21 : Register<"">; 280 def DSPOutFlag22 : Register<"">; 281 def DSPOutFlag23 : Register<"">; 282 def DSPCCond : Register<"">; 283 284 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 285 sub_dsp23] in 286 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 287 DSPOutFlag21, DSPOutFlag22, 288 DSPOutFlag23]>; 289} 290 291//===----------------------------------------------------------------------===// 292// Register Classes 293//===----------------------------------------------------------------------===// 294 295class CPURegsClass<list<ValueType> regTypes> : 296 RegisterClass<"Mips", regTypes, 32, (add 297 // Reserved 298 ZERO, AT, 299 // Return Values and Arguments 300 V0, V1, A0, A1, A2, A3, 301 // Not preserved across procedure calls 302 T0, T1, T2, T3, T4, T5, T6, T7, 303 // Callee save 304 S0, S1, S2, S3, S4, S5, S6, S7, 305 // Not preserved across procedure calls 306 T8, T9, 307 // Reserved 308 K0, K1, GP, SP, FP, RA)>; 309 310def CPURegs : CPURegsClass<[i32]>; 311def DSPRegs : CPURegsClass<[v4i8, v2i16]>; 312 313def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 314// Reserved 315 ZERO_64, AT_64, 316 // Return Values and Arguments 317 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 318 // Not preserved across procedure calls 319 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 320 // Callee save 321 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 322 // Not preserved across procedure calls 323 T8_64, T9_64, 324 // Reserved 325 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 326 327def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 328 // Return Values and Arguments 329 V0, V1, A0, A1, A2, A3, 330 // Callee save 331 S0, S1)>; 332 333def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 334 335def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 336 337// 64bit fp: 338// * FGR64 - 32 64-bit registers 339// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 340// 341// 32bit fp: 342// * FGR32 - 16 32-bit even registers 343// * FGR32 - 32 32-bit registers (single float only mode) 344def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 345 346def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 347 // Return Values and Arguments 348 D0, D1, 349 // Not preserved across procedure calls 350 D2, D3, D4, D5, 351 // Return Values and Arguments 352 D6, D7, 353 // Not preserved across procedure calls 354 D8, D9, 355 // Callee save 356 D10, D11, D12, D13, D14, D15)>; 357 358def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 359 360// Condition Register for floating point operations 361def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable; 362 363// Hi/Lo Registers 364def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; 365def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>; 366def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>; 367def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>; 368def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>; 369def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; 370 371// Hardware registers 372def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 373def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable; 374 375// Accumulator Registers 376def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 377 let Size = 64; 378} 379 380def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 381 let Size = 128; 382} 383 384def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 385 let Size = 64; 386} 387 388def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 389 390// Register Operands. 391def CPURegsAsmOperand : AsmOperandClass { 392 let Name = "CPURegsAsm"; 393 let ParserMethod = "parseCPURegs"; 394} 395 396def CPU64RegsAsmOperand : AsmOperandClass { 397 let Name = "CPU64RegsAsm"; 398 let ParserMethod = "parseCPU64Regs"; 399} 400 401def CCRAsmOperand : AsmOperandClass { 402 let Name = "CCRAsm"; 403 let ParserMethod = "parseCCRRegs"; 404} 405 406def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> { 407 let ParserMatchClass = CPURegsAsmOperand; 408} 409 410def CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> { 411 let ParserMatchClass = CPU64RegsAsmOperand; 412} 413 414def CCROpnd : RegisterOperand<CCR, "printCPURegs"> { 415 let ParserMatchClass = CCRAsmOperand; 416} 417 418def HWRegsAsmOperand : AsmOperandClass { 419 let Name = "HWRegsAsm"; 420 let ParserMethod = "parseHWRegs"; 421} 422 423def HW64RegsAsmOperand : AsmOperandClass { 424 let Name = "HW64RegsAsm"; 425 let ParserMethod = "parseHW64Regs"; 426} 427 428def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { 429 let ParserMatchClass = HWRegsAsmOperand; 430} 431 432def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> { 433 let ParserMatchClass = HW64RegsAsmOperand; 434} 435