MipsRegisterInfo.td revision a6c3a4ee76ef8464d3c83472e15af521ade7eeb4
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_32 : SubRegIndex<32>; 15def sub_64 : SubRegIndex<64>; 16def sub_lo : SubRegIndex<32>; 17def sub_hi : SubRegIndex<32, 32>; 18def sub_dsp16_19 : SubRegIndex<4, 16>; 19def sub_dsp20 : SubRegIndex<1, 20>; 20def sub_dsp21 : SubRegIndex<1, 21>; 21def sub_dsp22 : SubRegIndex<1, 22>; 22def sub_dsp23 : SubRegIndex<1, 23>; 23} 24 25class Unallocatable { 26 bit isAllocatable = 0; 27} 28 29// We have banks of 32 registers each. 30class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33} 34 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39} 40 41// Mips CPU Registers 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44// Mips 64-bit CPU Registers 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48} 49 50// Mips 32-bit FPU Registers 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53// Mips 64-bit (aliased) FPU Registers 54class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58} 59 60class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63 let CoveredBySubRegs = 1; 64} 65 66// Mips 128-bit (aliased) MSA Registers 67class AFPR128<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_64]; 70} 71 72// Accumulator Registers 73class ACCReg<bits<16> Enc, string n, list<Register> subregs> 74 : MipsRegWithSubRegs<Enc, n, subregs> { 75 let SubRegIndices = [sub_lo, sub_hi]; 76 let CoveredBySubRegs = 1; 77} 78 79// Mips Hardware Registers 80class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 81 82//===----------------------------------------------------------------------===// 83// Registers 84//===----------------------------------------------------------------------===// 85 86let Namespace = "Mips" in { 87 // General Purpose Registers 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 120 121 // General Purpose 64-bit Registers 122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 154 155 /// Mips Single point precision FPU Registers 156 foreach I = 0-31 in 157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 158 159 // Higher half of 64-bit FP registers. 160 foreach I = 0-31 in 161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 162 163 /// Mips Double point precision FPU Registers (aliased 164 /// with the single precision to hold 64 bit values) 165 foreach I = 0-15 in 166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 167 [!cast<FPR>("F"#!shl(I, 1)), 168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 169 170 /// Mips Double point precision FPU Registers in MFP64 mode. 171 foreach I = 0-31 in 172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 173 DwarfRegNum<[!add(I, 32)]>; 174 175 /// Mips MSA registers 176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 177 foreach I = 0-31 in 178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 179 DwarfRegNum<[!add(I, 32)]>; 180 181 // Hi/Lo registers 182 def HI0 : Register<"ac0">, DwarfRegNum<[64]>; 183 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 184 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 185 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 186 def LO0 : Register<"ac0">, DwarfRegNum<[65]>; 187 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 188 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 189 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 190 191 let SubRegIndices = [sub_32] in { 192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 194 } 195 196 // FP control registers. 197 foreach I = 0-31 in 198 def FCR#I : MipsReg<#I, ""#I>; 199 200 // FP condition code registers. 201 foreach I = 0-7 in 202 def FCC#I : MipsReg<#I, "fcc"#I>; 203 204 // PC register 205 def PC : Register<"pc">; 206 207 // Hardware register $29 208 def HWR29 : MipsReg<29, "29">; 209 210 // Accum registers 211 foreach I = 0-3 in 212 def AC#I : ACCReg<#I, "ac"#I, 213 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 214 215 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 216 217 // DSP-ASE control register fields. 218 def DSPPos : Register<"">; 219 def DSPSCount : Register<"">; 220 def DSPCarry : Register<"">; 221 def DSPEFI : Register<"">; 222 def DSPOutFlag16_19 : Register<"">; 223 def DSPOutFlag20 : Register<"">; 224 def DSPOutFlag21 : Register<"">; 225 def DSPOutFlag22 : Register<"">; 226 def DSPOutFlag23 : Register<"">; 227 def DSPCCond : Register<"">; 228 229 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 230 sub_dsp23] in 231 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 232 DSPOutFlag21, DSPOutFlag22, 233 DSPOutFlag23]>; 234 235 // MSA-ASE control registers. 236 def MSAIR : Register<"0">; 237 def MSACSR : Register<"1">; 238 def MSAAccess : Register<"2">; 239 def MSASave : Register<"3">; 240 def MSAModify : Register<"4">; 241 def MSARequest : Register<"5">; 242 def MSAMap : Register<"6">; 243 def MSAUnmap : Register<"7">; 244} 245 246//===----------------------------------------------------------------------===// 247// Register Classes 248//===----------------------------------------------------------------------===// 249 250class GPR32Class<list<ValueType> regTypes> : 251 RegisterClass<"Mips", regTypes, 32, (add 252 // Reserved 253 ZERO, AT, 254 // Return Values and Arguments 255 V0, V1, A0, A1, A2, A3, 256 // Not preserved across procedure calls 257 T0, T1, T2, T3, T4, T5, T6, T7, 258 // Callee save 259 S0, S1, S2, S3, S4, S5, S6, S7, 260 // Not preserved across procedure calls 261 T8, T9, 262 // Reserved 263 K0, K1, GP, SP, FP, RA)>; 264 265def GPR32 : GPR32Class<[i32]>; 266def DSPR : GPR32Class<[v4i8, v2i16]>; 267 268def GPR64 : RegisterClass<"Mips", [i64], 64, (add 269// Reserved 270 ZERO_64, AT_64, 271 // Return Values and Arguments 272 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 273 // Not preserved across procedure calls 274 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 275 // Callee save 276 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 277 // Not preserved across procedure calls 278 T8_64, T9_64, 279 // Reserved 280 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 281 282def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 283 // Return Values and Arguments 284 V0, V1, A0, A1, A2, A3, 285 // Callee save 286 S0, S1)>; 287 288def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 289 // Return Values and Arguments 290 V0, V1, A0, A1, A2, A3, 291 // Callee save 292 S0, S1, 293 SP)>; 294 295def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 296 297def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 298 299// 64bit fp: 300// * FGR64 - 32 64-bit registers 301// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 302// 303// 32bit fp: 304// * FGR32 - 16 32-bit even registers 305// * FGR32 - 32 32-bit registers (single float only mode) 306def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 307 308def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, 309 Unallocatable; 310 311def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 312 // Return Values and Arguments 313 D0, D1, 314 // Not preserved across procedure calls 315 D2, D3, D4, D5, 316 // Return Values and Arguments 317 D6, D7, 318 // Not preserved across procedure calls 319 D8, D9, 320 // Callee save 321 D10, D11, D12, D13, D14, D15)>; 322 323def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 324 325// FP control registers. 326def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 327 Unallocatable; 328 329// FP condition code registers. 330def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 331 Unallocatable; 332 333def MSA128B: RegisterClass<"Mips", [v16i8], 128, 334 (sequence "W%u", 0, 31)>; 335def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 336 (sequence "W%u", 0, 31)>; 337def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 338 (sequence "W%u", 0, 31)>; 339def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 340 (sequence "W%u", 0, 31)>; 341 342def MSACtrl: RegisterClass<"Mips", [i32], 32, (add 343 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; 344 345// Hi/Lo Registers 346def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 347def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 348def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 349def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 350def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 351def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 352 353// Hardware registers 354def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 355 356// Accumulator Registers 357def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 358 let Size = 64; 359} 360 361def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 362 let Size = 128; 363} 364 365def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 366 let Size = 64; 367} 368 369def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 370 371// Register Operands. 372 373class MipsAsmRegOperand : AsmOperandClass { 374 let RenderMethod = "addRegAsmOperands"; 375} 376def GPR32AsmOperand : MipsAsmRegOperand { 377 let Name = "GPR32Asm"; 378 let ParserMethod = "parseGPR32"; 379} 380 381def GPR64AsmOperand : MipsAsmRegOperand { 382 let Name = "GPR64Asm"; 383 let ParserMethod = "parseGPR64"; 384} 385 386def ACC64DSPAsmOperand : MipsAsmRegOperand { 387 let Name = "ACC64DSPAsm"; 388 let ParserMethod = "parseACC64DSP"; 389} 390 391def LO32DSPAsmOperand : MipsAsmRegOperand { 392 let Name = "LO32DSPAsm"; 393 let ParserMethod = "parseLO32DSP"; 394} 395 396def HI32DSPAsmOperand : MipsAsmRegOperand { 397 let Name = "HI32DSPAsm"; 398 let ParserMethod = "parseHI32DSP"; 399} 400 401def CCRAsmOperand : MipsAsmRegOperand { 402 let Name = "CCRAsm"; 403 let ParserMethod = "parseCCRRegs"; 404} 405 406def AFGR64AsmOperand : MipsAsmRegOperand { 407 let Name = "AFGR64Asm"; 408 let ParserMethod = "parseAFGR64Regs"; 409} 410 411def FGR64AsmOperand : MipsAsmRegOperand { 412 let Name = "FGR64Asm"; 413 let ParserMethod = "parseFGR64Regs"; 414} 415 416def FGR32AsmOperand : MipsAsmRegOperand { 417 let Name = "FGR32Asm"; 418 let ParserMethod = "parseFGR32Regs"; 419} 420 421def FGRH32AsmOperand : MipsAsmRegOperand { 422 let Name = "FGRH32Asm"; 423 let ParserMethod = "parseFGRH32Regs"; 424} 425 426def FCCRegsAsmOperand : MipsAsmRegOperand { 427 let Name = "FCCRegsAsm"; 428 let ParserMethod = "parseFCCRegs"; 429} 430 431def GPR32Opnd : RegisterOperand<GPR32> { 432 let ParserMatchClass = GPR32AsmOperand; 433} 434 435def GPR64Opnd : RegisterOperand<GPR64> { 436 let ParserMatchClass = GPR64AsmOperand; 437} 438 439def DSPROpnd : RegisterOperand<DSPR> { 440 let ParserMatchClass = GPR32AsmOperand; 441} 442 443def CCROpnd : RegisterOperand<CCR> { 444 let ParserMatchClass = CCRAsmOperand; 445} 446 447def HWRegsAsmOperand : MipsAsmRegOperand { 448 let Name = "HWRegsAsm"; 449 let ParserMethod = "parseHWRegs"; 450} 451 452def HWRegsOpnd : RegisterOperand<HWRegs> { 453 let ParserMatchClass = HWRegsAsmOperand; 454} 455 456def AFGR64Opnd : RegisterOperand<AFGR64> { 457 let ParserMatchClass = AFGR64AsmOperand; 458} 459 460def FGR64Opnd : RegisterOperand<FGR64> { 461 let ParserMatchClass = FGR64AsmOperand; 462} 463 464def FGR32Opnd : RegisterOperand<FGR32> { 465 let ParserMatchClass = FGR32AsmOperand; 466} 467 468def FGRH32Opnd : RegisterOperand<FGRH32> { 469 let ParserMatchClass = FGRH32AsmOperand; 470} 471 472def FCCRegsOpnd : RegisterOperand<FCC> { 473 let ParserMatchClass = FCCRegsAsmOperand; 474} 475 476def LO32DSPOpnd : RegisterOperand<LO32DSP> { 477 let ParserMatchClass = LO32DSPAsmOperand; 478} 479 480def HI32DSPOpnd : RegisterOperand<HI32DSP> { 481 let ParserMatchClass = HI32DSPAsmOperand; 482} 483 484def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 485 let ParserMatchClass = ACC64DSPAsmOperand; 486} 487