MipsRegisterInfo.td revision c73488a38ecb26340604706003e84cff7bd48ddf
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_32 : SubRegIndex<32>; 15def sub_64 : SubRegIndex<64>; 16def sub_lo : SubRegIndex<32>; 17def sub_hi : SubRegIndex<32, 32>; 18def sub_dsp16_19 : SubRegIndex<4, 16>; 19def sub_dsp20 : SubRegIndex<1, 20>; 20def sub_dsp21 : SubRegIndex<1, 21>; 21def sub_dsp22 : SubRegIndex<1, 22>; 22def sub_dsp23 : SubRegIndex<1, 23>; 23} 24 25class Unallocatable { 26 bit isAllocatable = 0; 27} 28 29// We have banks of 32 registers each. 30class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33} 34 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39} 40 41// Mips CPU Registers 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44// Mips 64-bit CPU Registers 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48} 49 50// Mips 32-bit FPU Registers 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53// Mips 64-bit (aliased) FPU Registers 54class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58} 59 60class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63} 64 65// Mips 128-bit (aliased) MSA Registers 66class AFPR128<bits<16> Enc, string n, list<Register> subregs> 67 : MipsRegWithSubRegs<Enc, n, subregs> { 68 let SubRegIndices = [sub_64]; 69} 70 71// Accumulator Registers 72class ACCReg<bits<16> Enc, string n, list<Register> subregs> 73 : MipsRegWithSubRegs<Enc, n, subregs> { 74 let SubRegIndices = [sub_lo, sub_hi]; 75 let CoveredBySubRegs = 1; 76} 77 78// Mips Hardware Registers 79class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 80 81//===----------------------------------------------------------------------===// 82// Registers 83//===----------------------------------------------------------------------===// 84 85let Namespace = "Mips" in { 86 // General Purpose Registers 87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 88 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 90 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 91 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 92 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 93 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 94 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 95 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 96 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 97 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 98 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 99 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 100 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 101 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 102 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 103 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 104 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 105 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 106 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 107 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 108 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 109 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 110 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 111 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 112 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 113 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 114 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 115 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 116 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 117 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 118 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 119 120 // General Purpose 64-bit Registers 121 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 122 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 123 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 124 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 125 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 126 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 127 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 128 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 129 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 130 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 131 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 132 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 133 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 134 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 135 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 136 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 137 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 138 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 139 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 140 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 141 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 142 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 143 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 144 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 145 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 146 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 147 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 148 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 149 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 150 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 151 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 152 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 153 154 /// Mips Single point precision FPU Registers 155 foreach I = 0-31 in 156 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 157 158 // Higher half of 64-bit FP registers. 159 foreach I = 0-31 in 160 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 161 162 /// Mips Double point precision FPU Registers (aliased 163 /// with the single precision to hold 64 bit values) 164 foreach I = 0-15 in 165 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 166 [!cast<FPR>("F"#!shl(I, 1)), 167 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 168 169 /// Mips Double point precision FPU Registers in MFP64 mode. 170 foreach I = 0-31 in 171 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 172 DwarfRegNum<[!add(I, 32)]>; 173 174 /// Mips MSA registers 175 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 176 foreach I = 0-31 in 177 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 178 DwarfRegNum<[!add(I, 32)]>; 179 180 // Hi/Lo registers 181 def HI0 : Register<"ac0">, DwarfRegNum<[64]>; 182 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 183 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 184 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 185 def LO0 : Register<"ac0">, DwarfRegNum<[65]>; 186 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 187 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 188 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 189 190 let SubRegIndices = [sub_32] in { 191 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 192 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 193 } 194 195 // FP control registers. 196 foreach I = 0-31 in 197 def FCR#I : MipsReg<#I, ""#I>; 198 199 // FP condition code registers. 200 foreach I = 0-7 in 201 def FCC#I : MipsReg<#I, "fcc"#I>; 202 203 // PC register 204 def PC : Register<"pc">; 205 206 // Hardware register $29 207 def HWR29 : MipsReg<29, "29">; 208 209 // Accum registers 210 foreach I = 0-3 in 211 def AC#I : ACCReg<#I, "ac"#I, 212 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 213 214 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 215 216 // DSP-ASE control register fields. 217 def DSPPos : Register<"">; 218 def DSPSCount : Register<"">; 219 def DSPCarry : Register<"">; 220 def DSPEFI : Register<"">; 221 def DSPOutFlag16_19 : Register<"">; 222 def DSPOutFlag20 : Register<"">; 223 def DSPOutFlag21 : Register<"">; 224 def DSPOutFlag22 : Register<"">; 225 def DSPOutFlag23 : Register<"">; 226 def DSPCCond : Register<"">; 227 228 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 229 sub_dsp23] in 230 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 231 DSPOutFlag21, DSPOutFlag22, 232 DSPOutFlag23]>; 233} 234 235//===----------------------------------------------------------------------===// 236// Register Classes 237//===----------------------------------------------------------------------===// 238 239class GPR32Class<list<ValueType> regTypes> : 240 RegisterClass<"Mips", regTypes, 32, (add 241 // Reserved 242 ZERO, AT, 243 // Return Values and Arguments 244 V0, V1, A0, A1, A2, A3, 245 // Not preserved across procedure calls 246 T0, T1, T2, T3, T4, T5, T6, T7, 247 // Callee save 248 S0, S1, S2, S3, S4, S5, S6, S7, 249 // Not preserved across procedure calls 250 T8, T9, 251 // Reserved 252 K0, K1, GP, SP, FP, RA)>; 253 254def GPR32 : GPR32Class<[i32]>; 255def DSPR : GPR32Class<[v4i8, v2i16]>; 256 257def GPR64 : RegisterClass<"Mips", [i64], 64, (add 258// Reserved 259 ZERO_64, AT_64, 260 // Return Values and Arguments 261 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 262 // Not preserved across procedure calls 263 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 264 // Callee save 265 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 266 // Not preserved across procedure calls 267 T8_64, T9_64, 268 // Reserved 269 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 270 271def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 272 // Return Values and Arguments 273 V0, V1, A0, A1, A2, A3, 274 // Callee save 275 S0, S1)>; 276 277def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 278 // Return Values and Arguments 279 V0, V1, A0, A1, A2, A3, 280 // Callee save 281 S0, S1, 282 SP)>; 283 284def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 285 286def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 287 288// 64bit fp: 289// * FGR64 - 32 64-bit registers 290// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 291// 292// 32bit fp: 293// * FGR32 - 16 32-bit even registers 294// * FGR32 - 32 32-bit registers (single float only mode) 295def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 296 297def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>; 298 299def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 300 // Return Values and Arguments 301 D0, D1, 302 // Not preserved across procedure calls 303 D2, D3, D4, D5, 304 // Return Values and Arguments 305 D6, D7, 306 // Not preserved across procedure calls 307 D8, D9, 308 // Callee save 309 D10, D11, D12, D13, D14, D15)>; 310 311def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 312 313// FP control registers. 314def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 315 Unallocatable; 316 317// FP condition code registers. 318def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 319 Unallocatable; 320 321def MSA128B: RegisterClass<"Mips", [v16i8], 128, 322 (sequence "W%u", 0, 31)>; 323def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 324 (sequence "W%u", 0, 31)>; 325def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 326 (sequence "W%u", 0, 31)>; 327def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 328 (sequence "W%u", 0, 31)>; 329 330// Hi/Lo Registers 331def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 332def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 333def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 334def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 335def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 336def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 337 338// Hardware registers 339def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 340 341// Accumulator Registers 342def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 343 let Size = 64; 344} 345 346def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 347 let Size = 128; 348} 349 350def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 351 let Size = 64; 352} 353 354def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 355 356// Register Operands. 357 358class MipsAsmRegOperand : AsmOperandClass { 359 let RenderMethod = "addRegAsmOperands"; 360} 361def GPR32AsmOperand : MipsAsmRegOperand { 362 let Name = "GPR32Asm"; 363 let ParserMethod = "parseGPR32"; 364} 365 366def GPR64AsmOperand : MipsAsmRegOperand { 367 let Name = "GPR64Asm"; 368 let ParserMethod = "parseGPR64"; 369} 370 371def ACC64DSPAsmOperand : MipsAsmRegOperand { 372 let Name = "ACC64DSPAsm"; 373 let ParserMethod = "parseACC64DSP"; 374} 375 376def LO32DSPAsmOperand : MipsAsmRegOperand { 377 let Name = "LO32DSPAsm"; 378 let ParserMethod = "parseLO32DSP"; 379} 380 381def HI32DSPAsmOperand : MipsAsmRegOperand { 382 let Name = "HI32DSPAsm"; 383 let ParserMethod = "parseHI32DSP"; 384} 385 386def CCRAsmOperand : MipsAsmRegOperand { 387 let Name = "CCRAsm"; 388 let ParserMethod = "parseCCRRegs"; 389} 390 391def AFGR64AsmOperand : MipsAsmRegOperand { 392 let Name = "AFGR64Asm"; 393 let ParserMethod = "parseAFGR64Regs"; 394} 395 396def FGR64AsmOperand : MipsAsmRegOperand { 397 let Name = "FGR64Asm"; 398 let ParserMethod = "parseFGR64Regs"; 399} 400 401def FGR32AsmOperand : MipsAsmRegOperand { 402 let Name = "FGR32Asm"; 403 let ParserMethod = "parseFGR32Regs"; 404} 405 406def FGRH32AsmOperand : MipsAsmRegOperand { 407 let Name = "FGRH32Asm"; 408 let ParserMethod = "parseFGRH32Regs"; 409} 410 411def FCCRegsAsmOperand : MipsAsmRegOperand { 412 let Name = "FCCRegsAsm"; 413 let ParserMethod = "parseFCCRegs"; 414} 415 416def GPR32Opnd : RegisterOperand<GPR32> { 417 let ParserMatchClass = GPR32AsmOperand; 418} 419 420def GPR64Opnd : RegisterOperand<GPR64> { 421 let ParserMatchClass = GPR64AsmOperand; 422} 423 424def DSPROpnd : RegisterOperand<DSPR> { 425 let ParserMatchClass = GPR32AsmOperand; 426} 427 428def CCROpnd : RegisterOperand<CCR> { 429 let ParserMatchClass = CCRAsmOperand; 430} 431 432def HWRegsAsmOperand : MipsAsmRegOperand { 433 let Name = "HWRegsAsm"; 434 let ParserMethod = "parseHWRegs"; 435} 436 437def HWRegsOpnd : RegisterOperand<HWRegs> { 438 let ParserMatchClass = HWRegsAsmOperand; 439} 440 441def AFGR64Opnd : RegisterOperand<AFGR64> { 442 let ParserMatchClass = AFGR64AsmOperand; 443} 444 445def FGR64Opnd : RegisterOperand<FGR64> { 446 let ParserMatchClass = FGR64AsmOperand; 447} 448 449def FGR32Opnd : RegisterOperand<FGR32> { 450 let ParserMatchClass = FGR32AsmOperand; 451} 452 453def FGRH32Opnd : RegisterOperand<FGRH32> { 454 let ParserMatchClass = FGRH32AsmOperand; 455} 456 457def FCCRegsOpnd : RegisterOperand<FCC> { 458 let ParserMatchClass = FCCRegsAsmOperand; 459} 460 461def LO32DSPOpnd : RegisterOperand<LO32DSP> { 462 let ParserMatchClass = LO32DSPAsmOperand; 463} 464 465def HI32DSPOpnd : RegisterOperand<HI32DSP> { 466 let ParserMatchClass = HI32DSPAsmOperand; 467} 468 469def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 470 let ParserMatchClass = ACC64DSPAsmOperand; 471} 472