MipsRegisterInfo.td revision e2a9376b1bd2204ea6f56a35b762e28e0ef4e35a
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_fpeven : SubRegIndex<32>; 15def sub_fpodd : SubRegIndex<32, 32>; 16def sub_32 : SubRegIndex<32>; 17def sub_64 : SubRegIndex<64>; 18def sub_lo : SubRegIndex<32>; 19def sub_hi : SubRegIndex<32, 32>; 20def sub_dsp16_19 : SubRegIndex<4, 16>; 21def sub_dsp20 : SubRegIndex<1, 20>; 22def sub_dsp21 : SubRegIndex<1, 21>; 23def sub_dsp22 : SubRegIndex<1, 22>; 24def sub_dsp23 : SubRegIndex<1, 23>; 25} 26 27class Unallocatable { 28 bit isAllocatable = 0; 29} 30 31// We have banks of 32 registers each. 32class MipsReg<bits<16> Enc, string n> : Register<n> { 33 let HWEncoding = Enc; 34 let Namespace = "Mips"; 35} 36 37class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 38 : RegisterWithSubRegs<n, subregs> { 39 let HWEncoding = Enc; 40 let Namespace = "Mips"; 41} 42 43// Mips CPU Registers 44class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 45 46// Mips 64-bit CPU Registers 47class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 48 : MipsRegWithSubRegs<Enc, n, subregs> { 49 let SubRegIndices = [sub_32]; 50} 51 52// Mips 32-bit FPU Registers 53class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 54 55// Mips 64-bit (aliased) FPU Registers 56class AFPR<bits<16> Enc, string n, list<Register> subregs> 57 : MipsRegWithSubRegs<Enc, n, subregs> { 58 let SubRegIndices = [sub_fpeven, sub_fpodd]; 59 let CoveredBySubRegs = 1; 60} 61 62class AFPR64<bits<16> Enc, string n, list<Register> subregs> 63 : MipsRegWithSubRegs<Enc, n, subregs> { 64 let SubRegIndices = [sub_32]; 65} 66 67// Mips 128-bit (aliased) MSA Registers 68class AFPR128<bits<16> Enc, string n, list<Register> subregs> 69 : MipsRegWithSubRegs<Enc, n, subregs> { 70 let SubRegIndices = [sub_64]; 71} 72 73// Accumulator Registers 74class ACCReg<bits<16> Enc, string n, list<Register> subregs> 75 : MipsRegWithSubRegs<Enc, n, subregs> { 76 let SubRegIndices = [sub_lo, sub_hi]; 77 let CoveredBySubRegs = 1; 78} 79 80// Mips Hardware Registers 81class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 82 83//===----------------------------------------------------------------------===// 84// Registers 85//===----------------------------------------------------------------------===// 86 87let Namespace = "Mips" in { 88 // General Purpose Registers 89 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 90 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 91 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 92 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 93 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 94 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 95 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 96 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 97 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 98 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 99 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 100 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 101 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 102 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 103 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 104 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 105 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 106 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 107 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 108 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 109 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 110 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 111 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 112 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 113 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 114 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 115 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 116 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 117 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 118 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 119 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 120 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 121 122 // General Purpose 64-bit Registers 123 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 124 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 125 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 126 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 127 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 128 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 129 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 130 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 131 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 132 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 133 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 134 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 135 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 136 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 137 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 138 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 139 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 140 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 141 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 142 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 143 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 144 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 145 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 146 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 147 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 148 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 149 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 150 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 151 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 152 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 153 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 154 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 155 156 /// Mips Single point precision FPU Registers 157 foreach I = 0-31 in 158 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 159 160 /// Mips Double point precision FPU Registers (aliased 161 /// with the single precision to hold 64 bit values) 162 foreach I = 0-15 in 163 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 164 [!cast<FPR>("F"#!shl(I, 1)), 165 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 166 167 /// Mips Double point precision FPU Registers in MFP64 mode. 168 foreach I = 0-31 in 169 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I)]>, 170 DwarfRegNum<[!add(I, 32)]>; 171 172 /// Mips MSA registers 173 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 174 def W0 : AFPR128<0, "w0", [D0_64]>, DwarfRegNum<[32]>; 175 def W1 : AFPR128<1, "w1", [D1_64]>, DwarfRegNum<[33]>; 176 def W2 : AFPR128<2, "w2", [D2_64]>, DwarfRegNum<[34]>; 177 def W3 : AFPR128<3, "w3", [D3_64]>, DwarfRegNum<[35]>; 178 def W4 : AFPR128<4, "w4", [D4_64]>, DwarfRegNum<[36]>; 179 def W5 : AFPR128<5, "w5", [D5_64]>, DwarfRegNum<[37]>; 180 def W6 : AFPR128<6, "w6", [D6_64]>, DwarfRegNum<[38]>; 181 def W7 : AFPR128<7, "w7", [D7_64]>, DwarfRegNum<[39]>; 182 def W8 : AFPR128<8, "w8", [D8_64]>, DwarfRegNum<[40]>; 183 def W9 : AFPR128<9, "w9", [D9_64]>, DwarfRegNum<[41]>; 184 def W10 : AFPR128<10, "w10", [D10_64]>, DwarfRegNum<[42]>; 185 def W11 : AFPR128<11, "w11", [D11_64]>, DwarfRegNum<[43]>; 186 def W12 : AFPR128<12, "w12", [D12_64]>, DwarfRegNum<[44]>; 187 def W13 : AFPR128<13, "w13", [D13_64]>, DwarfRegNum<[45]>; 188 def W14 : AFPR128<14, "w14", [D14_64]>, DwarfRegNum<[46]>; 189 def W15 : AFPR128<15, "w15", [D15_64]>, DwarfRegNum<[47]>; 190 def W16 : AFPR128<16, "w16", [D16_64]>, DwarfRegNum<[48]>; 191 def W17 : AFPR128<17, "w17", [D17_64]>, DwarfRegNum<[49]>; 192 def W18 : AFPR128<18, "w18", [D18_64]>, DwarfRegNum<[50]>; 193 def W19 : AFPR128<19, "w19", [D19_64]>, DwarfRegNum<[51]>; 194 def W20 : AFPR128<20, "w20", [D20_64]>, DwarfRegNum<[52]>; 195 def W21 : AFPR128<21, "w21", [D21_64]>, DwarfRegNum<[53]>; 196 def W22 : AFPR128<22, "w22", [D22_64]>, DwarfRegNum<[54]>; 197 def W23 : AFPR128<23, "w23", [D23_64]>, DwarfRegNum<[55]>; 198 def W24 : AFPR128<24, "w24", [D24_64]>, DwarfRegNum<[56]>; 199 def W25 : AFPR128<25, "w25", [D25_64]>, DwarfRegNum<[57]>; 200 def W26 : AFPR128<26, "w26", [D26_64]>, DwarfRegNum<[58]>; 201 def W27 : AFPR128<27, "w27", [D27_64]>, DwarfRegNum<[59]>; 202 def W28 : AFPR128<28, "w28", [D28_64]>, DwarfRegNum<[60]>; 203 def W29 : AFPR128<29, "w29", [D29_64]>, DwarfRegNum<[61]>; 204 def W30 : AFPR128<30, "w30", [D30_64]>, DwarfRegNum<[62]>; 205 def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>; 206 207 // Hi/Lo registers 208 def HI0 : Register<"ac0">, DwarfRegNum<[64]>; 209 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 210 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 211 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 212 def LO0 : Register<"ac0">, DwarfRegNum<[65]>; 213 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 214 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 215 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 216 217 let SubRegIndices = [sub_32] in { 218 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 219 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 220 } 221 222 // FP control registers. 223 foreach I = 0-31 in 224 def FCR#I : MipsReg<#I, ""#I>; 225 226 // FP condition code registers. 227 foreach I = 0-7 in 228 def FCC#I : MipsReg<#I, "fcc"#I>; 229 230 // PC register 231 def PC : Register<"pc">; 232 233 // Hardware register $29 234 def HWR29 : MipsReg<29, "29">; 235 236 // Accum registers 237 foreach I = 0-3 in 238 def AC#I : ACCReg<#I, "ac"#I, 239 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 240 241 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 242 243 // DSP-ASE control register fields. 244 def DSPPos : Register<"">; 245 def DSPSCount : Register<"">; 246 def DSPCarry : Register<"">; 247 def DSPEFI : Register<"">; 248 def DSPOutFlag16_19 : Register<"">; 249 def DSPOutFlag20 : Register<"">; 250 def DSPOutFlag21 : Register<"">; 251 def DSPOutFlag22 : Register<"">; 252 def DSPOutFlag23 : Register<"">; 253 def DSPCCond : Register<"">; 254 255 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 256 sub_dsp23] in 257 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 258 DSPOutFlag21, DSPOutFlag22, 259 DSPOutFlag23]>; 260} 261 262//===----------------------------------------------------------------------===// 263// Register Classes 264//===----------------------------------------------------------------------===// 265 266class GPR32Class<list<ValueType> regTypes> : 267 RegisterClass<"Mips", regTypes, 32, (add 268 // Reserved 269 ZERO, AT, 270 // Return Values and Arguments 271 V0, V1, A0, A1, A2, A3, 272 // Not preserved across procedure calls 273 T0, T1, T2, T3, T4, T5, T6, T7, 274 // Callee save 275 S0, S1, S2, S3, S4, S5, S6, S7, 276 // Not preserved across procedure calls 277 T8, T9, 278 // Reserved 279 K0, K1, GP, SP, FP, RA)>; 280 281def GPR32 : GPR32Class<[i32]>; 282def DSPR : GPR32Class<[v4i8, v2i16]>; 283 284def GPR64 : RegisterClass<"Mips", [i64], 64, (add 285// Reserved 286 ZERO_64, AT_64, 287 // Return Values and Arguments 288 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 289 // Not preserved across procedure calls 290 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 291 // Callee save 292 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 293 // Not preserved across procedure calls 294 T8_64, T9_64, 295 // Reserved 296 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 297 298def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 299 // Return Values and Arguments 300 V0, V1, A0, A1, A2, A3, 301 // Callee save 302 S0, S1)>; 303 304def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 305 // Return Values and Arguments 306 V0, V1, A0, A1, A2, A3, 307 // Callee save 308 S0, S1, 309 SP)>; 310 311def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 312 313def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 314 315// 64bit fp: 316// * FGR64 - 32 64-bit registers 317// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 318// 319// 32bit fp: 320// * FGR32 - 16 32-bit even registers 321// * FGR32 - 32 32-bit registers (single float only mode) 322def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 323 324def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 325 // Return Values and Arguments 326 D0, D1, 327 // Not preserved across procedure calls 328 D2, D3, D4, D5, 329 // Return Values and Arguments 330 D6, D7, 331 // Not preserved across procedure calls 332 D8, D9, 333 // Callee save 334 D10, D11, D12, D13, D14, D15)>; 335 336def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 337 338// FP control registers. 339def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 340 Unallocatable; 341 342// FP condition code registers. 343def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 344 Unallocatable; 345 346def MSA128: RegisterClass<"Mips", 347 [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 348 128, (sequence "W%u", 0, 31)>; 349 350// Hi/Lo Registers 351def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 352def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 353def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 354def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 355def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 356def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 357 358// Hardware registers 359def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 360 361// Accumulator Registers 362def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 363 let Size = 64; 364} 365 366def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 367 let Size = 128; 368} 369 370def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 371 let Size = 64; 372} 373 374def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 375 376// Register Operands. 377 378class MipsAsmRegOperand : AsmOperandClass { 379 let RenderMethod = "addRegAsmOperands"; 380} 381def GPR32AsmOperand : MipsAsmRegOperand { 382 let Name = "GPR32Asm"; 383 let ParserMethod = "parseGPR32"; 384} 385 386def GPR64AsmOperand : MipsAsmRegOperand { 387 let Name = "GPR64Asm"; 388 let ParserMethod = "parseGPR64"; 389} 390 391def ACC64DSPAsmOperand : MipsAsmRegOperand { 392 let Name = "ACC64DSPAsm"; 393 let ParserMethod = "parseACC64DSP"; 394} 395 396def LO32DSPAsmOperand : MipsAsmRegOperand { 397 let Name = "LO32DSPAsm"; 398 let ParserMethod = "parseLO32DSP"; 399} 400 401def HI32DSPAsmOperand : MipsAsmRegOperand { 402 let Name = "HI32DSPAsm"; 403 let ParserMethod = "parseHI32DSP"; 404} 405 406def CCRAsmOperand : MipsAsmRegOperand { 407 let Name = "CCRAsm"; 408 let ParserMethod = "parseCCRRegs"; 409} 410 411def AFGR64AsmOperand : MipsAsmRegOperand { 412 let Name = "AFGR64Asm"; 413 let ParserMethod = "parseAFGR64Regs"; 414} 415 416def FGR64AsmOperand : MipsAsmRegOperand { 417 let Name = "FGR64Asm"; 418 let ParserMethod = "parseFGR64Regs"; 419} 420 421def FGR32AsmOperand : MipsAsmRegOperand { 422 let Name = "FGR32Asm"; 423 let ParserMethod = "parseFGR32Regs"; 424} 425 426def FCCRegsAsmOperand : MipsAsmRegOperand { 427 let Name = "FCCRegsAsm"; 428 let ParserMethod = "parseFCCRegs"; 429} 430 431def GPR32Opnd : RegisterOperand<GPR32> { 432 let ParserMatchClass = GPR32AsmOperand; 433} 434 435def GPR64Opnd : RegisterOperand<GPR64> { 436 let ParserMatchClass = GPR64AsmOperand; 437} 438 439def DSPROpnd : RegisterOperand<DSPR> { 440 let ParserMatchClass = GPR32AsmOperand; 441} 442 443def CCROpnd : RegisterOperand<CCR> { 444 let ParserMatchClass = CCRAsmOperand; 445} 446 447def HWRegsAsmOperand : MipsAsmRegOperand { 448 let Name = "HWRegsAsm"; 449 let ParserMethod = "parseHWRegs"; 450} 451 452def HWRegsOpnd : RegisterOperand<HWRegs> { 453 let ParserMatchClass = HWRegsAsmOperand; 454} 455 456def AFGR64Opnd : RegisterOperand<AFGR64> { 457 let ParserMatchClass = AFGR64AsmOperand; 458} 459 460def FGR64Opnd : RegisterOperand<FGR64> { 461 let ParserMatchClass = FGR64AsmOperand; 462} 463 464def FGR32Opnd : RegisterOperand<FGR32> { 465 let ParserMatchClass = FGR32AsmOperand; 466} 467 468def FCCRegsOpnd : RegisterOperand<FCC> { 469 let ParserMatchClass = FCCRegsAsmOperand; 470} 471 472def LO32DSPOpnd : RegisterOperand<LO32DSP> { 473 let ParserMatchClass = LO32DSPAsmOperand; 474} 475 476def HI32DSPOpnd : RegisterOperand<HI32DSP> { 477 let ParserMatchClass = HI32DSPAsmOperand; 478} 479 480def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 481 let ParserMatchClass = ACC64DSPAsmOperand; 482} 483