MipsRegisterInfo.td revision e925f7dbbf497412cd0cc3f67b9b96fed0cc3712
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_32 : SubRegIndex<32>; 15def sub_64 : SubRegIndex<64>; 16def sub_lo : SubRegIndex<32>; 17def sub_hi : SubRegIndex<32, 32>; 18def sub_dsp16_19 : SubRegIndex<4, 16>; 19def sub_dsp20 : SubRegIndex<1, 20>; 20def sub_dsp21 : SubRegIndex<1, 21>; 21def sub_dsp22 : SubRegIndex<1, 22>; 22def sub_dsp23 : SubRegIndex<1, 23>; 23} 24 25class Unallocatable { 26 bit isAllocatable = 0; 27} 28 29// We have banks of 32 registers each. 30class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33} 34 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39} 40 41// Mips CPU Registers 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44// Mips 64-bit CPU Registers 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48} 49 50// Mips 32-bit FPU Registers 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53// Mips 64-bit (aliased) FPU Registers 54class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58} 59 60class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63 let CoveredBySubRegs = 1; 64} 65 66// Mips 128-bit (aliased) MSA Registers 67class AFPR128<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_64]; 70} 71 72// Accumulator Registers 73class ACCReg<bits<16> Enc, string n, list<Register> subregs> 74 : MipsRegWithSubRegs<Enc, n, subregs> { 75 let SubRegIndices = [sub_lo, sub_hi]; 76 let CoveredBySubRegs = 1; 77} 78 79// Mips Hardware Registers 80class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 81 82//===----------------------------------------------------------------------===// 83// Registers 84//===----------------------------------------------------------------------===// 85 86let Namespace = "Mips" in { 87 // General Purpose Registers 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 120 121 // General Purpose 64-bit Registers 122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 154 155 /// Mips Single point precision FPU Registers 156 foreach I = 0-31 in 157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 158 159 // Higher half of 64-bit FP registers. 160 foreach I = 0-31 in 161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 162 163 /// Mips Double point precision FPU Registers (aliased 164 /// with the single precision to hold 64 bit values) 165 foreach I = 0-15 in 166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 167 [!cast<FPR>("F"#!shl(I, 1)), 168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 169 170 /// Mips Double point precision FPU Registers in MFP64 mode. 171 foreach I = 0-31 in 172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 173 DwarfRegNum<[!add(I, 32)]>; 174 175 /// Mips MSA registers 176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 177 foreach I = 0-31 in 178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 179 DwarfRegNum<[!add(I, 32)]>; 180 181 // Hi/Lo registers 182 def HI0 : Register<"ac0">, DwarfRegNum<[64]>; 183 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 184 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 185 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 186 def LO0 : Register<"ac0">, DwarfRegNum<[65]>; 187 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 188 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 189 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 190 191 let SubRegIndices = [sub_32] in { 192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 194 } 195 196 // FP control registers. 197 foreach I = 0-31 in 198 def FCR#I : MipsReg<#I, ""#I>; 199 200 // FP condition code registers. 201 foreach I = 0-7 in 202 def FCC#I : MipsReg<#I, "fcc"#I>; 203 204 // COP2 registers. 205 foreach I = 0-31 in 206 def COP2#I : MipsReg<#I, ""#I>; 207 208 // PC register 209 def PC : Register<"pc">; 210 211 // Hardware register $29 212 def HWR29 : MipsReg<29, "29">; 213 214 // Accum registers 215 foreach I = 0-3 in 216 def AC#I : ACCReg<#I, "ac"#I, 217 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 218 219 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 220 221 // DSP-ASE control register fields. 222 def DSPPos : Register<"">; 223 def DSPSCount : Register<"">; 224 def DSPCarry : Register<"">; 225 def DSPEFI : Register<"">; 226 def DSPOutFlag16_19 : Register<"">; 227 def DSPOutFlag20 : Register<"">; 228 def DSPOutFlag21 : Register<"">; 229 def DSPOutFlag22 : Register<"">; 230 def DSPOutFlag23 : Register<"">; 231 def DSPCCond : Register<"">; 232 233 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 234 sub_dsp23] in 235 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 236 DSPOutFlag21, DSPOutFlag22, 237 DSPOutFlag23]>; 238 239 // MSA-ASE control registers. 240 def MSAIR : Register<"0">; 241 def MSACSR : Register<"1">; 242 def MSAAccess : Register<"2">; 243 def MSASave : Register<"3">; 244 def MSAModify : Register<"4">; 245 def MSARequest : Register<"5">; 246 def MSAMap : Register<"6">; 247 def MSAUnmap : Register<"7">; 248} 249 250//===----------------------------------------------------------------------===// 251// Register Classes 252//===----------------------------------------------------------------------===// 253 254class GPR32Class<list<ValueType> regTypes> : 255 RegisterClass<"Mips", regTypes, 32, (add 256 // Reserved 257 ZERO, AT, 258 // Return Values and Arguments 259 V0, V1, A0, A1, A2, A3, 260 // Not preserved across procedure calls 261 T0, T1, T2, T3, T4, T5, T6, T7, 262 // Callee save 263 S0, S1, S2, S3, S4, S5, S6, S7, 264 // Not preserved across procedure calls 265 T8, T9, 266 // Reserved 267 K0, K1, GP, SP, FP, RA)>; 268 269def GPR32 : GPR32Class<[i32]>; 270def DSPR : GPR32Class<[v4i8, v2i16]>; 271 272def GPR64 : RegisterClass<"Mips", [i64], 64, (add 273// Reserved 274 ZERO_64, AT_64, 275 // Return Values and Arguments 276 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 277 // Not preserved across procedure calls 278 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 279 // Callee save 280 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 281 // Not preserved across procedure calls 282 T8_64, T9_64, 283 // Reserved 284 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 285 286def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 287 // Return Values and Arguments 288 V0, V1, A0, A1, A2, A3, 289 // Callee save 290 S0, S1)>; 291 292def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 293 // Return Values and Arguments 294 V0, V1, A0, A1, A2, A3, 295 // Callee save 296 S0, S1, 297 SP)>; 298 299def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 300 301def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 302 303// 64bit fp: 304// * FGR64 - 32 64-bit registers 305// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 306// 307// 32bit fp: 308// * FGR32 - 16 32-bit even registers 309// * FGR32 - 32 32-bit registers (single float only mode) 310def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 311 312def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, 313 Unallocatable; 314 315def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 316 // Return Values and Arguments 317 D0, D1, 318 // Not preserved across procedure calls 319 D2, D3, D4, D5, 320 // Return Values and Arguments 321 D6, D7, 322 // Not preserved across procedure calls 323 D8, D9, 324 // Callee save 325 D10, D11, D12, D13, D14, D15)>; 326 327def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 328 329// FP control registers. 330def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 331 Unallocatable; 332 333// FP condition code registers. 334def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 335 Unallocatable; 336 337def MSA128B: RegisterClass<"Mips", [v16i8], 128, 338 (sequence "W%u", 0, 31)>; 339def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 340 (sequence "W%u", 0, 31)>; 341def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 342 (sequence "W%u", 0, 31)>; 343def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 344 (sequence "W%u", 0, 31)>; 345 346def MSACtrl: RegisterClass<"Mips", [i32], 32, (add 347 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; 348 349// Hi/Lo Registers 350def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 351def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 352def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 353def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 354def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 355def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 356 357// Hardware registers 358def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 359 360// Accumulator Registers 361def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 362 let Size = 64; 363} 364 365def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 366 let Size = 128; 367} 368 369def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 370 let Size = 64; 371} 372 373def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 374 375// Coprocessor 2 registers. 376def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, 377 Unallocatable; 378 379// Register Operands. 380 381class MipsAsmRegOperand : AsmOperandClass { 382 let RenderMethod = "addRegAsmOperands"; 383} 384def GPR32AsmOperand : MipsAsmRegOperand { 385 let Name = "GPR32Asm"; 386 let ParserMethod = "parseGPR32"; 387} 388 389def GPR64AsmOperand : MipsAsmRegOperand { 390 let Name = "GPR64Asm"; 391 let ParserMethod = "parseGPR64"; 392} 393 394def ACC64DSPAsmOperand : MipsAsmRegOperand { 395 let Name = "ACC64DSPAsm"; 396 let ParserMethod = "parseACC64DSP"; 397} 398 399def LO32DSPAsmOperand : MipsAsmRegOperand { 400 let Name = "LO32DSPAsm"; 401 let ParserMethod = "parseLO32DSP"; 402} 403 404def HI32DSPAsmOperand : MipsAsmRegOperand { 405 let Name = "HI32DSPAsm"; 406 let ParserMethod = "parseHI32DSP"; 407} 408 409def CCRAsmOperand : MipsAsmRegOperand { 410 let Name = "CCRAsm"; 411 let ParserMethod = "parseCCRRegs"; 412} 413 414def AFGR64AsmOperand : MipsAsmRegOperand { 415 let Name = "AFGR64Asm"; 416 let ParserMethod = "parseAFGR64Regs"; 417} 418 419def FGR64AsmOperand : MipsAsmRegOperand { 420 let Name = "FGR64Asm"; 421 let ParserMethod = "parseFGR64Regs"; 422} 423 424def FGR32AsmOperand : MipsAsmRegOperand { 425 let Name = "FGR32Asm"; 426 let ParserMethod = "parseFGR32Regs"; 427} 428 429def FGRH32AsmOperand : MipsAsmRegOperand { 430 let Name = "FGRH32Asm"; 431 let ParserMethod = "parseFGRH32Regs"; 432} 433 434def FCCRegsAsmOperand : MipsAsmRegOperand { 435 let Name = "FCCRegsAsm"; 436 let ParserMethod = "parseFCCRegs"; 437} 438 439def GPR32Opnd : RegisterOperand<GPR32> { 440 let ParserMatchClass = GPR32AsmOperand; 441} 442 443def GPR64Opnd : RegisterOperand<GPR64> { 444 let ParserMatchClass = GPR64AsmOperand; 445} 446 447def DSPROpnd : RegisterOperand<DSPR> { 448 let ParserMatchClass = GPR32AsmOperand; 449} 450 451def CCROpnd : RegisterOperand<CCR> { 452 let ParserMatchClass = CCRAsmOperand; 453} 454 455def HWRegsAsmOperand : MipsAsmRegOperand { 456 let Name = "HWRegsAsm"; 457 let ParserMethod = "parseHWRegs"; 458} 459 460def COP2AsmOperand : MipsAsmRegOperand { 461 let Name = "COP2Asm"; 462 let ParserMethod = "parseCOP2"; 463} 464 465def HWRegsOpnd : RegisterOperand<HWRegs> { 466 let ParserMatchClass = HWRegsAsmOperand; 467} 468 469def AFGR64Opnd : RegisterOperand<AFGR64> { 470 let ParserMatchClass = AFGR64AsmOperand; 471} 472 473def FGR64Opnd : RegisterOperand<FGR64> { 474 let ParserMatchClass = FGR64AsmOperand; 475} 476 477def FGR32Opnd : RegisterOperand<FGR32> { 478 let ParserMatchClass = FGR32AsmOperand; 479} 480 481def FGRH32Opnd : RegisterOperand<FGRH32> { 482 let ParserMatchClass = FGRH32AsmOperand; 483} 484 485def FCCRegsOpnd : RegisterOperand<FCC> { 486 let ParserMatchClass = FCCRegsAsmOperand; 487} 488 489def LO32DSPOpnd : RegisterOperand<LO32DSP> { 490 let ParserMatchClass = LO32DSPAsmOperand; 491} 492 493def HI32DSPOpnd : RegisterOperand<HI32DSP> { 494 let ParserMatchClass = HI32DSPAsmOperand; 495} 496 497def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 498 let ParserMatchClass = ACC64DSPAsmOperand; 499} 500 501def COP2Opnd : RegisterOperand<COP2> { 502 let ParserMatchClass = COP2AsmOperand; 503} 504