1//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEFrameLowering.h"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsSEInstrInfo.h"
19#include "MipsSubtarget.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineModuleInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterScavenging.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/Function.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Target/TargetOptions.h"
30
31using namespace llvm;
32
33namespace {
34typedef MachineBasicBlock::iterator Iter;
35
36static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
37  if (Mips::ACC64RegClass.contains(Src))
38    return std::make_pair((unsigned)Mips::PseudoMFHI,
39                          (unsigned)Mips::PseudoMFLO);
40
41  if (Mips::ACC64DSPRegClass.contains(Src))
42    return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
43
44  if (Mips::ACC128RegClass.contains(Src))
45    return std::make_pair((unsigned)Mips::PseudoMFHI64,
46                          (unsigned)Mips::PseudoMFLO64);
47
48  return std::make_pair(0, 0);
49}
50
51/// Helper class to expand pseudos.
52class ExpandPseudo {
53public:
54  ExpandPseudo(MachineFunction &MF);
55  bool expand();
56
57private:
58  bool expandInstr(MachineBasicBlock &MBB, Iter I);
59  void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
60  void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
61  void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62  void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
63                      unsigned MFLoOpc, unsigned RegSize);
64  bool expandCopy(MachineBasicBlock &MBB, Iter I);
65  bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
66                     unsigned MFLoOpc);
67
68  MachineFunction &MF;
69  MachineRegisterInfo &MRI;
70};
71}
72
73ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
74  : MF(MF_), MRI(MF.getRegInfo()) {}
75
76bool ExpandPseudo::expand() {
77  bool Expanded = false;
78
79  for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
80       BB != BBEnd; ++BB)
81    for (Iter I = BB->begin(), End = BB->end(); I != End;)
82      Expanded |= expandInstr(*BB, I++);
83
84  return Expanded;
85}
86
87bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
88  switch(I->getOpcode()) {
89  case Mips::LOAD_CCOND_DSP:
90    expandLoadCCond(MBB, I);
91    break;
92  case Mips::STORE_CCOND_DSP:
93    expandStoreCCond(MBB, I);
94    break;
95  case Mips::LOAD_ACC64:
96  case Mips::LOAD_ACC64DSP:
97    expandLoadACC(MBB, I, 4);
98    break;
99  case Mips::LOAD_ACC128:
100    expandLoadACC(MBB, I, 8);
101    break;
102  case Mips::STORE_ACC64:
103    expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
104    break;
105  case Mips::STORE_ACC64DSP:
106    expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
107    break;
108  case Mips::STORE_ACC128:
109    expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
110    break;
111  case TargetOpcode::COPY:
112    if (!expandCopy(MBB, I))
113      return false;
114    break;
115  default:
116    return false;
117  }
118
119  MBB.erase(I);
120  return true;
121}
122
123void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
124  //  load $vr, FI
125  //  copy ccond, $vr
126
127  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
128
129  const MipsSEInstrInfo &TII =
130    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
131  const MipsRegisterInfo &RegInfo =
132    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
133
134  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
135  unsigned VR = MRI.createVirtualRegister(RC);
136  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
137
138  TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
139  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
140    .addReg(VR, RegState::Kill);
141}
142
143void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
144  //  copy $vr, ccond
145  //  store $vr, FI
146
147  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
148
149  const MipsSEInstrInfo &TII =
150    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
151  const MipsRegisterInfo &RegInfo =
152    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
153
154  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
155  unsigned VR = MRI.createVirtualRegister(RC);
156  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
157
158  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
159    .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
160  TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
161}
162
163void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
164                                 unsigned RegSize) {
165  //  load $vr0, FI
166  //  copy lo, $vr0
167  //  load $vr1, FI + 4
168  //  copy hi, $vr1
169
170  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
171
172  const MipsSEInstrInfo &TII =
173    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
174  const MipsRegisterInfo &RegInfo =
175    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
176
177  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
178  unsigned VR0 = MRI.createVirtualRegister(RC);
179  unsigned VR1 = MRI.createVirtualRegister(RC);
180  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
181  unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
182  unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
183  DebugLoc DL = I->getDebugLoc();
184  const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
185
186  TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
187  BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
188  TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
189  BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
190}
191
192void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
193                                  unsigned MFHiOpc, unsigned MFLoOpc,
194                                  unsigned RegSize) {
195  //  mflo $vr0, src
196  //  store $vr0, FI
197  //  mfhi $vr1, src
198  //  store $vr1, FI + 4
199
200  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
201
202  const MipsSEInstrInfo &TII =
203    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
204  const MipsRegisterInfo &RegInfo =
205    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
206
207  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
208  unsigned VR0 = MRI.createVirtualRegister(RC);
209  unsigned VR1 = MRI.createVirtualRegister(RC);
210  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
211  unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
212  DebugLoc DL = I->getDebugLoc();
213
214  BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
215  TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
216  BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
217  TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
218}
219
220bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
221  unsigned Src = I->getOperand(1).getReg();
222  std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
223
224  if (!Opcodes.first)
225    return false;
226
227  return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
228}
229
230bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
231                                 unsigned MFHiOpc, unsigned MFLoOpc) {
232  //  mflo $vr0, src
233  //  copy dst_lo, $vr0
234  //  mfhi $vr1, src
235  //  copy dst_hi, $vr1
236
237  const MipsSEInstrInfo &TII =
238    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
239  const MipsRegisterInfo &RegInfo =
240    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
241
242  unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
243  unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
244  const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
245  unsigned VR0 = MRI.createVirtualRegister(RC);
246  unsigned VR1 = MRI.createVirtualRegister(RC);
247  unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
248  unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
249  unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
250  DebugLoc DL = I->getDebugLoc();
251
252  BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
253  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
254    .addReg(VR0, RegState::Kill);
255  BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
256  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
257    .addReg(VR1, RegState::Kill);
258  return true;
259}
260
261MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
262    : MipsFrameLowering(STI, STI.stackAlignment()) {}
263
264unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
265  static const unsigned EhDataReg[] = {
266    Mips::A0, Mips::A1, Mips::A2, Mips::A3
267  };
268  static const unsigned EhDataReg64[] = {
269    Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
270  };
271
272  return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
273}
274
275void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
276  MachineBasicBlock &MBB   = MF.front();
277  MachineFrameInfo *MFI    = MF.getFrameInfo();
278  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
279
280  const MipsSEInstrInfo &TII =
281    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
282  const MipsRegisterInfo &RegInfo =
283    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
284
285  MachineBasicBlock::iterator MBBI = MBB.begin();
286  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
287  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
288  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
289  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
290  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
291
292  // First, compute final stack size.
293  uint64_t StackSize = MFI->getStackSize();
294
295  // No need to allocate space on the stack.
296  if (StackSize == 0 && !MFI->adjustsStack()) return;
297
298  MachineModuleInfo &MMI = MF.getMMI();
299  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
300  MachineLocation DstML, SrcML;
301
302  // Adjust stack.
303  TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
304
305  // emit ".cfi_def_cfa_offset StackSize"
306  unsigned CFIIndex = MMI.addFrameInst(
307      MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
308  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
309      .addCFIIndex(CFIIndex);
310
311  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
312
313  if (CSI.size()) {
314    // Find the instruction past the last instruction that saves a callee-saved
315    // register to the stack.
316    for (unsigned i = 0; i < CSI.size(); ++i)
317      ++MBBI;
318
319    // Iterate over list of callee-saved registers and emit .cfi_offset
320    // directives.
321    for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
322           E = CSI.end(); I != E; ++I) {
323      int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
324      unsigned Reg = I->getReg();
325
326      // If Reg is a double precision register, emit two cfa_offsets,
327      // one for each of the paired single precision registers.
328      if (Mips::AFGR64RegClass.contains(Reg)) {
329        unsigned Reg0 =
330            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
331        unsigned Reg1 =
332            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
333
334        if (!STI.isLittle())
335          std::swap(Reg0, Reg1);
336
337        unsigned CFIIndex = MMI.addFrameInst(
338            MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
339        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
340            .addCFIIndex(CFIIndex);
341
342        CFIIndex = MMI.addFrameInst(
343            MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
344        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
345            .addCFIIndex(CFIIndex);
346      } else {
347        // Reg is either in GPR32 or FGR32.
348        unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
349            nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
350        BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
351            .addCFIIndex(CFIIndex);
352      }
353    }
354  }
355
356  if (MipsFI->callsEhReturn()) {
357    const TargetRegisterClass *RC = STI.isABI_N64() ?
358        &Mips::GPR64RegClass : &Mips::GPR32RegClass;
359
360    // Insert instructions that spill eh data registers.
361    for (int I = 0; I < 4; ++I) {
362      if (!MBB.isLiveIn(ehDataReg(I)))
363        MBB.addLiveIn(ehDataReg(I));
364      TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
365                              MipsFI->getEhDataRegFI(I), RC, &RegInfo);
366    }
367
368    // Emit .cfi_offset directives for eh data registers.
369    for (int I = 0; I < 4; ++I) {
370      int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
371      unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
372      unsigned CFIIndex = MMI.addFrameInst(
373          MCCFIInstruction::createOffset(nullptr, Reg, Offset));
374      BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
375          .addCFIIndex(CFIIndex);
376    }
377  }
378
379  // if framepointer enabled, set it to point to the stack pointer.
380  if (hasFP(MF)) {
381    // Insert instruction "move $fp, $sp" at this location.
382    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
383      .setMIFlag(MachineInstr::FrameSetup);
384
385    // emit ".cfi_def_cfa_register $fp"
386    unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
387        nullptr, MRI->getDwarfRegNum(FP, true)));
388    BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
389        .addCFIIndex(CFIIndex);
390  }
391}
392
393void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
394                                       MachineBasicBlock &MBB) const {
395  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
396  MachineFrameInfo *MFI            = MF.getFrameInfo();
397  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
398
399  const MipsSEInstrInfo &TII =
400    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
401  const MipsRegisterInfo &RegInfo =
402    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
403
404  DebugLoc dl = MBBI->getDebugLoc();
405  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
406  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
407  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
408  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
409
410  // if framepointer enabled, restore the stack pointer.
411  if (hasFP(MF)) {
412    // Find the first instruction that restores a callee-saved register.
413    MachineBasicBlock::iterator I = MBBI;
414
415    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
416      --I;
417
418    // Insert instruction "move $sp, $fp" at this location.
419    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
420  }
421
422  if (MipsFI->callsEhReturn()) {
423    const TargetRegisterClass *RC = STI.isABI_N64() ?
424        &Mips::GPR64RegClass : &Mips::GPR32RegClass;
425
426    // Find first instruction that restores a callee-saved register.
427    MachineBasicBlock::iterator I = MBBI;
428    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
429      --I;
430
431    // Insert instructions that restore eh data registers.
432    for (int J = 0; J < 4; ++J) {
433      TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
434                               RC, &RegInfo);
435    }
436  }
437
438  // Get the number of bytes from FrameInfo
439  uint64_t StackSize = MFI->getStackSize();
440
441  if (!StackSize)
442    return;
443
444  // Adjust stack.
445  TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
446}
447
448bool MipsSEFrameLowering::
449spillCalleeSavedRegisters(MachineBasicBlock &MBB,
450                          MachineBasicBlock::iterator MI,
451                          const std::vector<CalleeSavedInfo> &CSI,
452                          const TargetRegisterInfo *TRI) const {
453  MachineFunction *MF = MBB.getParent();
454  MachineBasicBlock *EntryBlock = MF->begin();
455  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
456
457  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
458    // Add the callee-saved register as live-in. Do not add if the register is
459    // RA and return address is taken, because it has already been added in
460    // method MipsTargetLowering::LowerRETURNADDR.
461    // It's killed at the spill, unless the register is RA and return address
462    // is taken.
463    unsigned Reg = CSI[i].getReg();
464    bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
465        && MF->getFrameInfo()->isReturnAddressTaken();
466    if (!IsRAAndRetAddrIsTaken)
467      EntryBlock->addLiveIn(Reg);
468
469    // Insert the spill to the stack frame.
470    bool IsKill = !IsRAAndRetAddrIsTaken;
471    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
472    TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
473                            CSI[i].getFrameIdx(), RC, TRI);
474  }
475
476  return true;
477}
478
479bool
480MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
481  const MachineFrameInfo *MFI = MF.getFrameInfo();
482
483  // Reserve call frame if the size of the maximum call frame fits into 16-bit
484  // immediate field and there are no variable sized objects on the stack.
485  // Make sure the second register scavenger spill slot can be accessed with one
486  // instruction.
487  return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
488    !MFI->hasVarSizedObjects();
489}
490
491// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
492void MipsSEFrameLowering::
493eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
494                              MachineBasicBlock::iterator I) const {
495  const MipsSEInstrInfo &TII =
496    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
497
498  if (!hasReservedCallFrame(MF)) {
499    int64_t Amount = I->getOperand(0).getImm();
500
501    if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
502      Amount = -Amount;
503
504    unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
505    TII.adjustStackPtr(SP, Amount, MBB, I);
506  }
507
508  MBB.erase(I);
509}
510
511void MipsSEFrameLowering::
512processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
513                                     RegScavenger *RS) const {
514  MachineRegisterInfo &MRI = MF.getRegInfo();
515  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
516  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
517
518  // Mark $fp as used if function has dedicated frame pointer.
519  if (hasFP(MF))
520    MRI.setPhysRegUsed(FP);
521
522  // Create spill slots for eh data registers if function calls eh_return.
523  if (MipsFI->callsEhReturn())
524    MipsFI->createEhDataRegsFI();
525
526  // Expand pseudo instructions which load, store or copy accumulators.
527  // Add an emergency spill slot if a pseudo was expanded.
528  if (ExpandPseudo(MF).expand()) {
529    // The spill slot should be half the size of the accumulator. If target is
530    // mips64, it should be 64-bit, otherwise it should be 32-bt.
531    const TargetRegisterClass *RC = STI.hasMips64() ?
532      &Mips::GPR64RegClass : &Mips::GPR32RegClass;
533    int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
534                                                  RC->getAlignment(), false);
535    RS->addScavengingFrameIndex(FI);
536  }
537
538  // Set scavenging frame index if necessary.
539  uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
540    estimateStackSize(MF);
541
542  if (isInt<16>(MaxSPOffset))
543    return;
544
545  const TargetRegisterClass *RC = STI.isABI_N64() ?
546    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
547  int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
548                                                RC->getAlignment(), false);
549  RS->addScavengingFrameIndex(FI);
550}
551
552const MipsFrameLowering *
553llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
554  return new MipsSEFrameLowering(ST);
555}
556