MipsSEFrameLowering.cpp revision a98a486ad194c38293efcc5359d6ed2493f950dc 
1//===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of TargetFrameLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEFrameLowering.h"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsSEInstrInfo.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/RegisterScavenging.h"
25#include "llvm/IR/DataLayout.h"
26#include "llvm/IR/Function.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Target/TargetOptions.h"
29
30using namespace llvm;
31
32namespace {
33typedef MachineBasicBlock::iterator Iter;
34
35/// Helper class to expand pseudos.
36class ExpandPseudo {
37public:
38  ExpandPseudo(MachineFunction &MF);
39  bool expand();
40
41private:
42  bool expandInstr(MachineBasicBlock &MBB, Iter I);
43  void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
44  void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
45  void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
46  void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
47  bool expandCopy(MachineBasicBlock &MBB, Iter I);
48  bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
49                     unsigned Src, unsigned RegSize);
50
51  MachineFunction &MF;
52  MachineRegisterInfo &MRI;
53};
54}
55
56ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
57  : MF(MF_), MRI(MF.getRegInfo()) {}
58
59bool ExpandPseudo::expand() {
60  bool Expanded = false;
61
62  for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
63       BB != BBEnd; ++BB)
64    for (Iter I = BB->begin(), End = BB->end(); I != End;)
65      Expanded |= expandInstr(*BB, I++);
66
67  return Expanded;
68}
69
70bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
71  switch(I->getOpcode()) {
72  case Mips::LOAD_CCOND_DSP:
73    expandLoadCCond(MBB, I);
74    break;
75  case Mips::STORE_CCOND_DSP:
76    expandStoreCCond(MBB, I);
77    break;
78  case Mips::LOAD_ACC64:
79  case Mips::LOAD_ACC64DSP:
80    expandLoadACC(MBB, I, 4);
81    break;
82  case Mips::LOAD_ACC128:
83    expandLoadACC(MBB, I, 8);
84    break;
85  case Mips::STORE_ACC64:
86  case Mips::STORE_ACC64DSP:
87    expandStoreACC(MBB, I, 4);
88    break;
89  case Mips::STORE_ACC128:
90    expandStoreACC(MBB, I, 8);
91    break;
92  case TargetOpcode::COPY:
93    if (!expandCopy(MBB, I))
94      return false;
95    break;
96  default:
97    return false;
98  }
99
100  MBB.erase(I);
101  return true;
102}
103
104void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
105  //  load $vr, FI
106  //  copy ccond, $vr
107
108  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
109
110  const MipsSEInstrInfo &TII =
111    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
112  const MipsRegisterInfo &RegInfo =
113    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
114
115  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
116  unsigned VR = MRI.createVirtualRegister(RC);
117  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
118
119  TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
120  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
121    .addReg(VR, RegState::Kill);
122}
123
124void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
125  //  copy $vr, ccond
126  //  store $vr, FI
127
128  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
129
130  const MipsSEInstrInfo &TII =
131    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
132  const MipsRegisterInfo &RegInfo =
133    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
134
135  const TargetRegisterClass *RC = RegInfo.intRegClass(4);
136  unsigned VR = MRI.createVirtualRegister(RC);
137  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
138
139  BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
140    .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
141  TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
142}
143
144void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
145                                 unsigned RegSize) {
146  //  load $vr0, FI
147  //  copy lo, $vr0
148  //  load $vr1, FI + 4
149  //  copy hi, $vr1
150
151  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
152
153  const MipsSEInstrInfo &TII =
154    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
155  const MipsRegisterInfo &RegInfo =
156    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
157
158  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
159  unsigned VR0 = MRI.createVirtualRegister(RC);
160  unsigned VR1 = MRI.createVirtualRegister(RC);
161  unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
162  unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
163  unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
164  DebugLoc DL = I->getDebugLoc();
165  const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
166
167  TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
168  BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
169  TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
170  BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
171}
172
173void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
174                                  unsigned RegSize) {
175  //  copy $vr0, lo
176  //  store $vr0, FI
177  //  copy $vr1, hi
178  //  store $vr1, FI + 4
179
180  assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
181
182  const MipsSEInstrInfo &TII =
183    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
184  const MipsRegisterInfo &RegInfo =
185    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
186
187  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
188  unsigned VR0 = MRI.createVirtualRegister(RC);
189  unsigned VR1 = MRI.createVirtualRegister(RC);
190  unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
191  unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
192  unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
193  unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
194  DebugLoc DL = I->getDebugLoc();
195
196  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
197  TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
198  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(Hi, SrcKill);
199  TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
200}
201
202bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
203  unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
204
205  if (Mips::ACC64DSPRegClass.contains(Dst, Src))
206    return expandCopyACC(MBB, I, Dst, Src, 4);
207
208  if (Mips::ACC128RegClass.contains(Dst, Src))
209    return expandCopyACC(MBB, I, Dst, Src, 8);
210
211  return false;
212}
213
214bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
215                                 unsigned Src, unsigned RegSize) {
216  //  copy $vr0, src_lo
217  //  copy dst_lo, $vr0
218  //  copy $vr1, src_hi
219  //  copy dst_hi, $vr1
220
221  const MipsSEInstrInfo &TII =
222    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
223  const MipsRegisterInfo &RegInfo =
224    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
225
226  const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
227  unsigned VR0 = MRI.createVirtualRegister(RC);
228  unsigned VR1 = MRI.createVirtualRegister(RC);
229  unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
230  unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
231  unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
232  unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
233  unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
234  DebugLoc DL = I->getDebugLoc();
235
236  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(SrcLo, SrcKill);
237  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
238    .addReg(VR0, RegState::Kill);
239  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
240  BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
241    .addReg(VR1, RegState::Kill);
242  return true;
243}
244
245unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
246  static const unsigned EhDataReg[] = {
247    Mips::A0, Mips::A1, Mips::A2, Mips::A3
248  };
249  static const unsigned EhDataReg64[] = {
250    Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
251  };
252
253  return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
254}
255
256void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
257  MachineBasicBlock &MBB   = MF.front();
258  MachineFrameInfo *MFI    = MF.getFrameInfo();
259  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
260
261  const MipsSEInstrInfo &TII =
262    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
263  const MipsRegisterInfo &RegInfo =
264    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
265
266  MachineBasicBlock::iterator MBBI = MBB.begin();
267  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
268  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
269  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
270  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
271  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
272
273  // First, compute final stack size.
274  uint64_t StackSize = MFI->getStackSize();
275
276  // No need to allocate space on the stack.
277  if (StackSize == 0 && !MFI->adjustsStack()) return;
278
279  MachineModuleInfo &MMI = MF.getMMI();
280  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
281  MachineLocation DstML, SrcML;
282
283  // Adjust stack.
284  TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
285
286  // emit ".cfi_def_cfa_offset StackSize"
287  MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
288  BuildMI(MBB, MBBI, dl,
289          TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
290  MMI.addFrameInst(
291      MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
292
293  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
294
295  if (CSI.size()) {
296    // Find the instruction past the last instruction that saves a callee-saved
297    // register to the stack.
298    for (unsigned i = 0; i < CSI.size(); ++i)
299      ++MBBI;
300
301    // Iterate over list of callee-saved registers and emit .cfi_offset
302    // directives.
303    MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
304    BuildMI(MBB, MBBI, dl,
305            TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
306
307    for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
308           E = CSI.end(); I != E; ++I) {
309      int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
310      unsigned Reg = I->getReg();
311
312      // If Reg is a double precision register, emit two cfa_offsets,
313      // one for each of the paired single precision registers.
314      if (Mips::AFGR64RegClass.contains(Reg)) {
315        unsigned Reg0 =
316            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
317        unsigned Reg1 =
318            MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
319
320        if (!STI.isLittle())
321          std::swap(Reg0, Reg1);
322
323        MMI.addFrameInst(
324            MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
325        MMI.addFrameInst(
326            MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
327      } else {
328        // Reg is either in GPR32 or FGR32.
329        MMI.addFrameInst(MCCFIInstruction::createOffset(
330            CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
331      }
332    }
333  }
334
335  if (MipsFI->callsEhReturn()) {
336    const TargetRegisterClass *RC = STI.isABI_N64() ?
337        &Mips::GPR64RegClass : &Mips::GPR32RegClass;
338
339    // Insert instructions that spill eh data registers.
340    for (int I = 0; I < 4; ++I) {
341      if (!MBB.isLiveIn(ehDataReg(I)))
342        MBB.addLiveIn(ehDataReg(I));
343      TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
344                              MipsFI->getEhDataRegFI(I), RC, &RegInfo);
345    }
346
347    // Emit .cfi_offset directives for eh data registers.
348    MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol();
349    BuildMI(MBB, MBBI, dl,
350            TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
351    for (int I = 0; I < 4; ++I) {
352      int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
353      unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
354      MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
355    }
356  }
357
358  // if framepointer enabled, set it to point to the stack pointer.
359  if (hasFP(MF)) {
360    // Insert instruction "move $fp, $sp" at this location.
361    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
362
363    // emit ".cfi_def_cfa_register $fp"
364    MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
365    BuildMI(MBB, MBBI, dl,
366            TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
367    MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
368        SetFPLabel, MRI->getDwarfRegNum(FP, true)));
369  }
370}
371
372void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
373                                       MachineBasicBlock &MBB) const {
374  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
375  MachineFrameInfo *MFI            = MF.getFrameInfo();
376  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
377
378  const MipsSEInstrInfo &TII =
379    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
380  const MipsRegisterInfo &RegInfo =
381    *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
382
383  DebugLoc dl = MBBI->getDebugLoc();
384  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
385  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
386  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
387  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
388
389  // if framepointer enabled, restore the stack pointer.
390  if (hasFP(MF)) {
391    // Find the first instruction that restores a callee-saved register.
392    MachineBasicBlock::iterator I = MBBI;
393
394    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
395      --I;
396
397    // Insert instruction "move $sp, $fp" at this location.
398    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
399  }
400
401  if (MipsFI->callsEhReturn()) {
402    const TargetRegisterClass *RC = STI.isABI_N64() ?
403        &Mips::GPR64RegClass : &Mips::GPR32RegClass;
404
405    // Find first instruction that restores a callee-saved register.
406    MachineBasicBlock::iterator I = MBBI;
407    for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
408      --I;
409
410    // Insert instructions that restore eh data registers.
411    for (int J = 0; J < 4; ++J) {
412      TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
413                               RC, &RegInfo);
414    }
415  }
416
417  // Get the number of bytes from FrameInfo
418  uint64_t StackSize = MFI->getStackSize();
419
420  if (!StackSize)
421    return;
422
423  // Adjust stack.
424  TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
425}
426
427bool MipsSEFrameLowering::
428spillCalleeSavedRegisters(MachineBasicBlock &MBB,
429                          MachineBasicBlock::iterator MI,
430                          const std::vector<CalleeSavedInfo> &CSI,
431                          const TargetRegisterInfo *TRI) const {
432  MachineFunction *MF = MBB.getParent();
433  MachineBasicBlock *EntryBlock = MF->begin();
434  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
435
436  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
437    // Add the callee-saved register as live-in. Do not add if the register is
438    // RA and return address is taken, because it has already been added in
439    // method MipsTargetLowering::LowerRETURNADDR.
440    // It's killed at the spill, unless the register is RA and return address
441    // is taken.
442    unsigned Reg = CSI[i].getReg();
443    bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
444        && MF->getFrameInfo()->isReturnAddressTaken();
445    if (!IsRAAndRetAddrIsTaken)
446      EntryBlock->addLiveIn(Reg);
447
448    // Insert the spill to the stack frame.
449    bool IsKill = !IsRAAndRetAddrIsTaken;
450    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
451    TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
452                            CSI[i].getFrameIdx(), RC, TRI);
453  }
454
455  return true;
456}
457
458bool
459MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
460  const MachineFrameInfo *MFI = MF.getFrameInfo();
461
462  // Reserve call frame if the size of the maximum call frame fits into 16-bit
463  // immediate field and there are no variable sized objects on the stack.
464  // Make sure the second register scavenger spill slot can be accessed with one
465  // instruction.
466  return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
467    !MFI->hasVarSizedObjects();
468}
469
470// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
471void MipsSEFrameLowering::
472eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
473                              MachineBasicBlock::iterator I) const {
474  const MipsSEInstrInfo &TII =
475    *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
476
477  if (!hasReservedCallFrame(MF)) {
478    int64_t Amount = I->getOperand(0).getImm();
479
480    if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
481      Amount = -Amount;
482
483    unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
484    TII.adjustStackPtr(SP, Amount, MBB, I);
485  }
486
487  MBB.erase(I);
488}
489
490void MipsSEFrameLowering::
491processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
492                                     RegScavenger *RS) const {
493  MachineRegisterInfo &MRI = MF.getRegInfo();
494  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
495  unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
496
497  // Mark $fp as used if function has dedicated frame pointer.
498  if (hasFP(MF))
499    MRI.setPhysRegUsed(FP);
500
501  // Create spill slots for eh data registers if function calls eh_return.
502  if (MipsFI->callsEhReturn())
503    MipsFI->createEhDataRegsFI();
504
505  // Expand pseudo instructions which load, store or copy accumulators.
506  // Add an emergency spill slot if a pseudo was expanded.
507  if (ExpandPseudo(MF).expand()) {
508    // The spill slot should be half the size of the accumulator. If target is
509    // mips64, it should be 64-bit, otherwise it should be 32-bt.
510    const TargetRegisterClass *RC = STI.hasMips64() ?
511      &Mips::GPR64RegClass : &Mips::GPR32RegClass;
512    int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
513                                                  RC->getAlignment(), false);
514    RS->addScavengingFrameIndex(FI);
515  }
516
517  // Set scavenging frame index if necessary.
518  uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
519    estimateStackSize(MF);
520
521  if (isInt<16>(MaxSPOffset))
522    return;
523
524  const TargetRegisterClass *RC = STI.isABI_N64() ?
525    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
526  int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
527                                                RC->getAlignment(), false);
528  RS->addScavengingFrameIndex(FI);
529}
530
531const MipsFrameLowering *
532llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
533  return new MipsSEFrameLowering(ST);
534}
535