MipsSEISelDAGToDAG.cpp revision 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de 
1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsDAGToDAGISel specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "MipsSEISelDAGToDAG.h"
16#include "Mips.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsMachineFunction.h"
20#include "MipsRegisterInfo.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGNodes.h"
27#include "llvm/IR/GlobalValue.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/CFG.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39  if (Subtarget.inMips16Mode())
40    return false;
41  return MipsDAGToDAGISel::runOnMachineFunction(MF);
42}
43
44void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
45                                               MachineFunction &MF) {
46  MachineInstrBuilder MIB(MF, &MI);
47  unsigned Mask = MI.getOperand(1).getImm();
48  unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
49
50  if (Mask & 1)
51    MIB.addReg(Mips::DSPPos, Flag);
52
53  if (Mask & 2)
54    MIB.addReg(Mips::DSPSCount, Flag);
55
56  if (Mask & 4)
57    MIB.addReg(Mips::DSPCarry, Flag);
58
59  if (Mask & 8)
60    MIB.addReg(Mips::DSPOutFlag, Flag);
61
62  if (Mask & 16)
63    MIB.addReg(Mips::DSPCCond, Flag);
64
65  if (Mask & 32)
66    MIB.addReg(Mips::DSPEFI, Flag);
67}
68
69unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
70  switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
71  default:
72    llvm_unreachable("Could not map int to register");
73  case 0: return Mips::MSAIR;
74  case 1: return Mips::MSACSR;
75  case 2: return Mips::MSAAccess;
76  case 3: return Mips::MSASave;
77  case 4: return Mips::MSAModify;
78  case 5: return Mips::MSARequest;
79  case 6: return Mips::MSAMap;
80  case 7: return Mips::MSAUnmap;
81  }
82}
83
84bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
85                                                const MachineInstr& MI) {
86  unsigned DstReg = 0, ZeroReg = 0;
87
88  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
89  if ((MI.getOpcode() == Mips::ADDiu) &&
90      (MI.getOperand(1).getReg() == Mips::ZERO) &&
91      (MI.getOperand(2).getImm() == 0)) {
92    DstReg = MI.getOperand(0).getReg();
93    ZeroReg = Mips::ZERO;
94  } else if ((MI.getOpcode() == Mips::DADDiu) &&
95             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96             (MI.getOperand(2).getImm() == 0)) {
97    DstReg = MI.getOperand(0).getReg();
98    ZeroReg = Mips::ZERO_64;
99  }
100
101  if (!DstReg)
102    return false;
103
104  // Replace uses with ZeroReg.
105  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106       E = MRI->use_end(); U != E;) {
107    MachineOperand &MO = U.getOperand();
108    unsigned OpNo = U.getOperandNo();
109    MachineInstr *MI = MO.getParent();
110    ++U;
111
112    // Do not replace if it is a phi's operand or is tied to def operand.
113    if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114      continue;
115
116    MO.setReg(ZeroReg);
117  }
118
119  return true;
120}
121
122void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
123  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
124
125  if (!MipsFI->globalBaseRegSet())
126    return;
127
128  MachineBasicBlock &MBB = MF.front();
129  MachineBasicBlock::iterator I = MBB.begin();
130  MachineRegisterInfo &RegInfo = MF.getRegInfo();
131  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
132  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134  const TargetRegisterClass *RC;
135
136  if (Subtarget.isABI_N64())
137    RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
138  else
139    RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
140
141  V0 = RegInfo.createVirtualRegister(RC);
142  V1 = RegInfo.createVirtualRegister(RC);
143
144  if (Subtarget.isABI_N64()) {
145    MF.getRegInfo().addLiveIn(Mips::T9_64);
146    MBB.addLiveIn(Mips::T9_64);
147
148    // lui $v0, %hi(%neg(%gp_rel(fname)))
149    // daddu $v1, $v0, $t9
150    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151    const GlobalValue *FName = MF.getFunction();
152    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155      .addReg(Mips::T9_64);
156    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
158    return;
159  }
160
161  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
162    // Set global register to __gnu_local_gp.
163    //
164    // lui   $v0, %hi(__gnu_local_gp)
165    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
166    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
167      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
168    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
169      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
170    return;
171  }
172
173  MF.getRegInfo().addLiveIn(Mips::T9);
174  MBB.addLiveIn(Mips::T9);
175
176  if (Subtarget.isABI_N32()) {
177    // lui $v0, %hi(%neg(%gp_rel(fname)))
178    // addu $v1, $v0, $t9
179    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180    const GlobalValue *FName = MF.getFunction();
181    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
186    return;
187  }
188
189  assert(Subtarget.isABI_O32());
190
191  // For O32 ABI, the following instruction sequence is emitted to initialize
192  // the global base register:
193  //
194  //  0. lui   $2, %hi(_gp_disp)
195  //  1. addiu $2, $2, %lo(_gp_disp)
196  //  2. addu  $globalbasereg, $2, $t9
197  //
198  // We emit only the last instruction here.
199  //
200  // GNU linker requires that the first two instructions appear at the beginning
201  // of a function and no instructions be inserted before or between them.
202  // The two instructions are emitted during lowering to MC layer in order to
203  // avoid any reordering.
204  //
205  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
206  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
207  // reads it.
208  MF.getRegInfo().addLiveIn(Mips::V0);
209  MBB.addLiveIn(Mips::V0);
210  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
211    .addReg(Mips::V0).addReg(Mips::T9);
212}
213
214void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
215  initGlobalBaseReg(MF);
216
217  MachineRegisterInfo *MRI = &MF.getRegInfo();
218
219  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
220       ++MFI)
221    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
222      if (I->getOpcode() == Mips::RDDSP)
223        addDSPCtrlRegOperands(false, *I, MF);
224      else if (I->getOpcode() == Mips::WRDSP)
225        addDSPCtrlRegOperands(true, *I, MF);
226      else
227        replaceUsesWithZeroReg(MRI, *I);
228    }
229}
230
231SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
232                                           SDValue CmpLHS, SDLoc DL,
233                                           SDNode *Node) const {
234  unsigned Opc = InFlag.getOpcode(); (void)Opc;
235
236  assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
237          (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
238         "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239
240  SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
241  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
242  EVT VT = LHS.getValueType();
243
244  SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
245  SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
246                                            SDValue(Carry, 0), RHS);
247  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248                              SDValue(AddCarry, 0));
249}
250
251/// ComplexPattern used on MipsInstrInfo
252/// Used on Mips Load/Store instructions
253bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
254                                          SDValue &Offset) const {
255  EVT ValTy = Addr.getValueType();
256
257  // if Address is FI, get the TargetFrameIndex.
258  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
259    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260    Offset = CurDAG->getTargetConstant(0, ValTy);
261    return true;
262  }
263
264  // on PIC code Load GA
265  if (Addr.getOpcode() == MipsISD::Wrapper) {
266    Base   = Addr.getOperand(0);
267    Offset = Addr.getOperand(1);
268    return true;
269  }
270
271  if (TM.getRelocationModel() != Reloc::PIC_) {
272    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
273        Addr.getOpcode() == ISD::TargetGlobalAddress))
274      return false;
275  }
276
277  // Addresses of the form FI+const or FI|const
278  if (CurDAG->isBaseWithConstantOffset(Addr)) {
279    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
280    if (isInt<16>(CN->getSExtValue())) {
281
282      // If the first operand is a FI, get the TargetFI Node
283      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
284                                  (Addr.getOperand(0)))
285        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
286      else
287        Base = Addr.getOperand(0);
288
289      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
290      return true;
291    }
292  }
293
294  // Operand is a result from an ADD.
295  if (Addr.getOpcode() == ISD::ADD) {
296    // When loading from constant pools, load the lower address part in
297    // the instruction itself. Example, instead of:
298    //  lui $2, %hi($CPI1_0)
299    //  addiu $2, $2, %lo($CPI1_0)
300    //  lwc1 $f0, 0($2)
301    // Generate:
302    //  lui $2, %hi($CPI1_0)
303    //  lwc1 $f0, %lo($CPI1_0)($2)
304    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
305        Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
306      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
307      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
308          isa<JumpTableSDNode>(Opnd0)) {
309        Base = Addr.getOperand(0);
310        Offset = Opnd0;
311        return true;
312      }
313    }
314  }
315
316  return false;
317}
318
319/// ComplexPattern used on MipsInstrInfo
320/// Used on Mips Load/Store instructions
321bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
322                                          SDValue &Offset) const {
323  // Operand is a result from an ADD.
324  if (Addr.getOpcode() == ISD::ADD) {
325    Base = Addr.getOperand(0);
326    Offset = Addr.getOperand(1);
327    return true;
328  }
329
330  return false;
331}
332
333bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
334                                           SDValue &Offset) const {
335  Base = Addr;
336  Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
337  return true;
338}
339
340bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
341                                       SDValue &Offset) const {
342  return selectAddrRegImm(Addr, Base, Offset) ||
343    selectAddrDefault(Addr, Base, Offset);
344}
345
346/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
347bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
348                                            SDValue &Offset) const {
349  EVT ValTy = Addr.getValueType();
350
351  // Addresses of the form FI+const or FI|const
352  if (CurDAG->isBaseWithConstantOffset(Addr)) {
353    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
354    if (isInt<12>(CN->getSExtValue())) {
355
356      // If the first operand is a FI then get the TargetFI Node
357      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
358                                  (Addr.getOperand(0)))
359        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
360      else
361        Base = Addr.getOperand(0);
362
363      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
364      return true;
365    }
366  }
367
368  return false;
369}
370
371bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
372                                         SDValue &Offset) const {
373  return selectAddrRegImm12(Addr, Base, Offset) ||
374    selectAddrDefault(Addr, Base, Offset);
375}
376
377// Select constant vector splats.
378//
379// Returns true and sets Imm if:
380// * MSA is enabled
381// * N is a ISD::BUILD_VECTOR representing a constant splat
382bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
383  if (!Subtarget.hasMSA())
384    return false;
385
386  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
387
388  if (Node == NULL)
389    return false;
390
391  APInt SplatValue, SplatUndef;
392  unsigned SplatBitSize;
393  bool HasAnyUndefs;
394
395  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
396                             HasAnyUndefs, 8,
397                             !Subtarget.isLittle()))
398    return false;
399
400  Imm = SplatValue;
401
402  return true;
403}
404
405// Select constant vector splats.
406//
407// In addition to the requirements of selectVSplat(), this function returns
408// true and sets Imm if:
409// * The splat value is the same width as the elements of the vector
410// * The splat value fits in an integer with the specified signed-ness and
411//   width.
412//
413// This function looks through ISD::BITCAST nodes.
414// TODO: This might not be appropriate for big-endian MSA since BITCAST is
415//       sometimes a shuffle in big-endian mode.
416//
417// It's worth noting that this function is not used as part of the selection
418// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
419// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
420// MipsSEDAGToDAGISel::selectNode.
421bool MipsSEDAGToDAGISel::
422selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
423                   unsigned ImmBitSize) const {
424  APInt ImmValue;
425  EVT EltTy = N->getValueType(0).getVectorElementType();
426
427  if (N->getOpcode() == ISD::BITCAST)
428    N = N->getOperand(0);
429
430  if (selectVSplat (N.getNode(), ImmValue) &&
431      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
432    if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
433        (!Signed && ImmValue.isIntN(ImmBitSize))) {
434      Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
435      return true;
436    }
437  }
438
439  return false;
440}
441
442// Select constant vector splats.
443bool MipsSEDAGToDAGISel::
444selectVSplatUimm1(SDValue N, SDValue &Imm) const {
445  return selectVSplatCommon(N, Imm, false, 1);
446}
447
448bool MipsSEDAGToDAGISel::
449selectVSplatUimm2(SDValue N, SDValue &Imm) const {
450  return selectVSplatCommon(N, Imm, false, 2);
451}
452
453bool MipsSEDAGToDAGISel::
454selectVSplatUimm3(SDValue N, SDValue &Imm) const {
455  return selectVSplatCommon(N, Imm, false, 3);
456}
457
458// Select constant vector splats.
459bool MipsSEDAGToDAGISel::
460selectVSplatUimm4(SDValue N, SDValue &Imm) const {
461  return selectVSplatCommon(N, Imm, false, 4);
462}
463
464// Select constant vector splats.
465bool MipsSEDAGToDAGISel::
466selectVSplatUimm5(SDValue N, SDValue &Imm) const {
467  return selectVSplatCommon(N, Imm, false, 5);
468}
469
470// Select constant vector splats.
471bool MipsSEDAGToDAGISel::
472selectVSplatUimm6(SDValue N, SDValue &Imm) const {
473  return selectVSplatCommon(N, Imm, false, 6);
474}
475
476// Select constant vector splats.
477bool MipsSEDAGToDAGISel::
478selectVSplatUimm8(SDValue N, SDValue &Imm) const {
479  return selectVSplatCommon(N, Imm, false, 8);
480}
481
482// Select constant vector splats.
483bool MipsSEDAGToDAGISel::
484selectVSplatSimm5(SDValue N, SDValue &Imm) const {
485  return selectVSplatCommon(N, Imm, true, 5);
486}
487
488// Select constant vector splats whose value is a power of 2.
489//
490// In addition to the requirements of selectVSplat(), this function returns
491// true and sets Imm if:
492// * The splat value is the same width as the elements of the vector
493// * The splat value is a power of two.
494//
495// This function looks through ISD::BITCAST nodes.
496// TODO: This might not be appropriate for big-endian MSA since BITCAST is
497//       sometimes a shuffle in big-endian mode.
498bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
499  APInt ImmValue;
500  EVT EltTy = N->getValueType(0).getVectorElementType();
501
502  if (N->getOpcode() == ISD::BITCAST)
503    N = N->getOperand(0);
504
505  if (selectVSplat (N.getNode(), ImmValue) &&
506      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
507    int32_t Log2 = ImmValue.exactLogBase2();
508
509    if (Log2 != -1) {
510      Imm = CurDAG->getTargetConstant(Log2, EltTy);
511      return true;
512    }
513  }
514
515  return false;
516}
517
518// Select constant vector splats whose value only has a consecutive sequence
519// of left-most bits set (e.g. 0b11...1100...00).
520//
521// In addition to the requirements of selectVSplat(), this function returns
522// true and sets Imm if:
523// * The splat value is the same width as the elements of the vector
524// * The splat value is a consecutive sequence of left-most bits.
525//
526// This function looks through ISD::BITCAST nodes.
527// TODO: This might not be appropriate for big-endian MSA since BITCAST is
528//       sometimes a shuffle in big-endian mode.
529bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
530  APInt ImmValue;
531  EVT EltTy = N->getValueType(0).getVectorElementType();
532
533  if (N->getOpcode() == ISD::BITCAST)
534    N = N->getOperand(0);
535
536  if (selectVSplat(N.getNode(), ImmValue) &&
537      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
538    // Extract the run of set bits starting with bit zero from the bitwise
539    // inverse of ImmValue, and test that the inverse of this is the same
540    // as the original value.
541    if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
542
543      Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
544      return true;
545    }
546  }
547
548  return false;
549}
550
551// Select constant vector splats whose value only has a consecutive sequence
552// of right-most bits set (e.g. 0b00...0011...11).
553//
554// In addition to the requirements of selectVSplat(), this function returns
555// true and sets Imm if:
556// * The splat value is the same width as the elements of the vector
557// * The splat value is a consecutive sequence of right-most bits.
558//
559// This function looks through ISD::BITCAST nodes.
560// TODO: This might not be appropriate for big-endian MSA since BITCAST is
561//       sometimes a shuffle in big-endian mode.
562bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
563  APInt ImmValue;
564  EVT EltTy = N->getValueType(0).getVectorElementType();
565
566  if (N->getOpcode() == ISD::BITCAST)
567    N = N->getOperand(0);
568
569  if (selectVSplat(N.getNode(), ImmValue) &&
570      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
571    // Extract the run of set bits starting with bit zero, and test that the
572    // result is the same as the original value
573    if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
574      Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
575      return true;
576    }
577  }
578
579  return false;
580}
581
582std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
583  unsigned Opcode = Node->getOpcode();
584  SDLoc DL(Node);
585
586  ///
587  // Instruction Selection not handled by the auto-generated
588  // tablegen selection should be handled here.
589  ///
590  SDNode *Result;
591
592  switch(Opcode) {
593  default: break;
594
595  case ISD::SUBE: {
596    SDValue InFlag = Node->getOperand(2);
597    Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
598    return std::make_pair(true, Result);
599  }
600
601  case ISD::ADDE: {
602    if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
603      break;
604    SDValue InFlag = Node->getOperand(2);
605    Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
606    return std::make_pair(true, Result);
607  }
608
609  case ISD::ConstantFP: {
610    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
611    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
612      if (Subtarget.hasMips64()) {
613        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
614                                              Mips::ZERO_64, MVT::i64);
615        Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
616      } else {
617        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
618                                              Mips::ZERO, MVT::i32);
619        Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
620                                        Zero);
621      }
622
623      return std::make_pair(true, Result);
624    }
625    break;
626  }
627
628  case ISD::Constant: {
629    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
630    unsigned Size = CN->getValueSizeInBits(0);
631
632    if (Size == 32)
633      break;
634
635    MipsAnalyzeImmediate AnalyzeImm;
636    int64_t Imm = CN->getSExtValue();
637
638    const MipsAnalyzeImmediate::InstSeq &Seq =
639      AnalyzeImm.Analyze(Imm, Size, false);
640
641    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
642    SDLoc DL(CN);
643    SDNode *RegOpnd;
644    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
645                                                MVT::i64);
646
647    // The first instruction can be a LUi which is different from other
648    // instructions (ADDiu, ORI and SLL) in that it does not have a register
649    // operand.
650    if (Inst->Opc == Mips::LUi64)
651      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
652    else
653      RegOpnd =
654        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
655                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
656                               ImmOpnd);
657
658    // The remaining instructions in the sequence are handled here.
659    for (++Inst; Inst != Seq.end(); ++Inst) {
660      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
661                                          MVT::i64);
662      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
663                                       SDValue(RegOpnd, 0), ImmOpnd);
664    }
665
666    return std::make_pair(true, RegOpnd);
667  }
668
669  case ISD::INTRINSIC_W_CHAIN: {
670    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
671    default:
672      break;
673
674    case Intrinsic::mips_cfcmsa: {
675      SDValue ChainIn = Node->getOperand(0);
676      SDValue RegIdx = Node->getOperand(2);
677      SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
678                                           getMSACtrlReg(RegIdx), MVT::i32);
679      return std::make_pair(true, Reg.getNode());
680    }
681    }
682    break;
683  }
684
685  case ISD::INTRINSIC_WO_CHAIN: {
686    switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
687    default:
688      break;
689
690    case Intrinsic::mips_move_v:
691      // Like an assignment but will always produce a move.v even if
692      // unnecessary.
693      return std::make_pair(true,
694                            CurDAG->getMachineNode(Mips::MOVE_V, DL,
695                                                   Node->getValueType(0),
696                                                   Node->getOperand(1)));
697    }
698    break;
699  }
700
701  case ISD::INTRINSIC_VOID: {
702    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
703    default:
704      break;
705
706    case Intrinsic::mips_ctcmsa: {
707      SDValue ChainIn = Node->getOperand(0);
708      SDValue RegIdx  = Node->getOperand(2);
709      SDValue Value   = Node->getOperand(3);
710      SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
711                                              getMSACtrlReg(RegIdx), Value);
712      return std::make_pair(true, ChainOut.getNode());
713    }
714    }
715    break;
716  }
717
718  case MipsISD::ThreadPointer: {
719    EVT PtrVT = getTargetLowering()->getPointerTy();
720    unsigned RdhwrOpc, DestReg;
721
722    if (PtrVT == MVT::i32) {
723      RdhwrOpc = Mips::RDHWR;
724      DestReg = Mips::V1;
725    } else {
726      RdhwrOpc = Mips::RDHWR64;
727      DestReg = Mips::V1_64;
728    }
729
730    SDNode *Rdhwr =
731      CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
732                             Node->getValueType(0),
733                             CurDAG->getRegister(Mips::HWR29, MVT::i32));
734    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
735                                         SDValue(Rdhwr, 0));
736    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
737    ReplaceUses(SDValue(Node, 0), ResNode);
738    return std::make_pair(true, ResNode.getNode());
739  }
740
741  case ISD::BUILD_VECTOR: {
742    // Select appropriate ldi.[bhwd] instructions for constant splats of
743    // 128-bit when MSA is enabled. Fixup any register class mismatches that
744    // occur as a result.
745    //
746    // This allows the compiler to use a wider range of immediates than would
747    // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
748    // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
749    // 0x01010101 } without using a constant pool. This would be sub-optimal
750    // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
751    // same set/ of registers. Similarly, ldi.h isn't capable of producing {
752    // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
753
754    BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
755    APInt SplatValue, SplatUndef;
756    unsigned SplatBitSize;
757    bool HasAnyUndefs;
758    unsigned LdiOp;
759    EVT ResVecTy = BVN->getValueType(0);
760    EVT ViaVecTy;
761
762    if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector())
763      return std::make_pair(false, (SDNode*)NULL);
764
765    if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
766                              HasAnyUndefs, 8,
767                              !Subtarget.isLittle()))
768      return std::make_pair(false, (SDNode*)NULL);
769
770    switch (SplatBitSize) {
771    default:
772      return std::make_pair(false, (SDNode*)NULL);
773    case 8:
774      LdiOp = Mips::LDI_B;
775      ViaVecTy = MVT::v16i8;
776      break;
777    case 16:
778      LdiOp = Mips::LDI_H;
779      ViaVecTy = MVT::v8i16;
780      break;
781    case 32:
782      LdiOp = Mips::LDI_W;
783      ViaVecTy = MVT::v4i32;
784      break;
785    case 64:
786      LdiOp = Mips::LDI_D;
787      ViaVecTy = MVT::v2i64;
788      break;
789    }
790
791    if (!SplatValue.isSignedIntN(10))
792      return std::make_pair(false, (SDNode*)NULL);
793
794    SDValue Imm = CurDAG->getTargetConstant(SplatValue,
795                                            ViaVecTy.getVectorElementType());
796
797    SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
798
799    if (ResVecTy != ViaVecTy) {
800      // If LdiOp is writing to a different register class to ResVecTy, then
801      // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
802      // since the source and destination register sets contain the same
803      // registers.
804      const TargetLowering *TLI = getTargetLowering();
805      MVT ResVecTySimple = ResVecTy.getSimpleVT();
806      const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
807      Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
808                                   ResVecTy, SDValue(Res, 0),
809                                   CurDAG->getTargetConstant(RC->getID(),
810                                                             MVT::i32));
811    }
812
813    return std::make_pair(true, Res);
814  }
815
816  }
817
818  return std::make_pair(false, (SDNode*)NULL);
819}
820
821FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
822  return new MipsSEDAGToDAGISel(TM);
823}
824