MipsSEISelDAGToDAG.cpp revision acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 
1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsDAGToDAGISel specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-isel"
15#include "MipsSEISelDAGToDAG.h"
16#include "Mips.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsMachineFunction.h"
20#include "MipsRegisterInfo.h"
21#include "llvm/CodeGen/MachineConstantPool.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGNodes.h"
27#include "llvm/IR/GlobalValue.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/CFG.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
39  if (Subtarget.inMips16Mode())
40    return false;
41  return MipsDAGToDAGISel::runOnMachineFunction(MF);
42}
43
44void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
45                                               MachineFunction &MF) {
46  MachineInstrBuilder MIB(MF, &MI);
47  unsigned Mask = MI.getOperand(1).getImm();
48  unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
49
50  if (Mask & 1)
51    MIB.addReg(Mips::DSPPos, Flag);
52
53  if (Mask & 2)
54    MIB.addReg(Mips::DSPSCount, Flag);
55
56  if (Mask & 4)
57    MIB.addReg(Mips::DSPCarry, Flag);
58
59  if (Mask & 8)
60    MIB.addReg(Mips::DSPOutFlag, Flag);
61
62  if (Mask & 16)
63    MIB.addReg(Mips::DSPCCond, Flag);
64
65  if (Mask & 32)
66    MIB.addReg(Mips::DSPEFI, Flag);
67}
68
69unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
70  switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
71  default:
72    llvm_unreachable("Could not map int to register");
73  case 0: return Mips::MSAIR;
74  case 1: return Mips::MSACSR;
75  case 2: return Mips::MSAAccess;
76  case 3: return Mips::MSASave;
77  case 4: return Mips::MSAModify;
78  case 5: return Mips::MSARequest;
79  case 6: return Mips::MSAMap;
80  case 7: return Mips::MSAUnmap;
81  }
82}
83
84bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
85                                                const MachineInstr& MI) {
86  unsigned DstReg = 0, ZeroReg = 0;
87
88  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
89  if ((MI.getOpcode() == Mips::ADDiu) &&
90      (MI.getOperand(1).getReg() == Mips::ZERO) &&
91      (MI.getOperand(2).getImm() == 0)) {
92    DstReg = MI.getOperand(0).getReg();
93    ZeroReg = Mips::ZERO;
94  } else if ((MI.getOpcode() == Mips::DADDiu) &&
95             (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96             (MI.getOperand(2).getImm() == 0)) {
97    DstReg = MI.getOperand(0).getReg();
98    ZeroReg = Mips::ZERO_64;
99  }
100
101  if (!DstReg)
102    return false;
103
104  // Replace uses with ZeroReg.
105  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106       E = MRI->use_end(); U != E;) {
107    MachineOperand &MO = U.getOperand();
108    unsigned OpNo = U.getOperandNo();
109    MachineInstr *MI = MO.getParent();
110    ++U;
111
112    // Do not replace if it is a phi's operand or is tied to def operand.
113    if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114      continue;
115
116    MO.setReg(ZeroReg);
117  }
118
119  return true;
120}
121
122void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
123  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
124
125  if (!MipsFI->globalBaseRegSet())
126    return;
127
128  MachineBasicBlock &MBB = MF.front();
129  MachineBasicBlock::iterator I = MBB.begin();
130  MachineRegisterInfo &RegInfo = MF.getRegInfo();
131  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
132  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
133  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
134  const TargetRegisterClass *RC;
135
136  if (Subtarget.isABI_N64())
137    RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
138  else
139    RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
140
141  V0 = RegInfo.createVirtualRegister(RC);
142  V1 = RegInfo.createVirtualRegister(RC);
143
144  if (Subtarget.isABI_N64()) {
145    MF.getRegInfo().addLiveIn(Mips::T9_64);
146    MBB.addLiveIn(Mips::T9_64);
147
148    // lui $v0, %hi(%neg(%gp_rel(fname)))
149    // daddu $v1, $v0, $t9
150    // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
151    const GlobalValue *FName = MF.getFunction();
152    BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
153      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
154    BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
155      .addReg(Mips::T9_64);
156    BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
157      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
158    return;
159  }
160
161  if (MF.getTarget().getRelocationModel() == Reloc::Static) {
162    // Set global register to __gnu_local_gp.
163    //
164    // lui   $v0, %hi(__gnu_local_gp)
165    // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
166    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
167      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
168    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
169      .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
170    return;
171  }
172
173  MF.getRegInfo().addLiveIn(Mips::T9);
174  MBB.addLiveIn(Mips::T9);
175
176  if (Subtarget.isABI_N32()) {
177    // lui $v0, %hi(%neg(%gp_rel(fname)))
178    // addu $v1, $v0, $t9
179    // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
180    const GlobalValue *FName = MF.getFunction();
181    BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
182      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
183    BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
184    BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
185      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
186    return;
187  }
188
189  assert(Subtarget.isABI_O32());
190
191  // For O32 ABI, the following instruction sequence is emitted to initialize
192  // the global base register:
193  //
194  //  0. lui   $2, %hi(_gp_disp)
195  //  1. addiu $2, $2, %lo(_gp_disp)
196  //  2. addu  $globalbasereg, $2, $t9
197  //
198  // We emit only the last instruction here.
199  //
200  // GNU linker requires that the first two instructions appear at the beginning
201  // of a function and no instructions be inserted before or between them.
202  // The two instructions are emitted during lowering to MC layer in order to
203  // avoid any reordering.
204  //
205  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
206  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
207  // reads it.
208  MF.getRegInfo().addLiveIn(Mips::V0);
209  MBB.addLiveIn(Mips::V0);
210  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
211    .addReg(Mips::V0).addReg(Mips::T9);
212}
213
214void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
215  initGlobalBaseReg(MF);
216
217  MachineRegisterInfo *MRI = &MF.getRegInfo();
218
219  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
220       ++MFI)
221    for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
222      if (I->getOpcode() == Mips::RDDSP)
223        addDSPCtrlRegOperands(false, *I, MF);
224      else if (I->getOpcode() == Mips::WRDSP)
225        addDSPCtrlRegOperands(true, *I, MF);
226      else
227        replaceUsesWithZeroReg(MRI, *I);
228    }
229}
230
231SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
232                                           SDValue CmpLHS, SDLoc DL,
233                                           SDNode *Node) const {
234  unsigned Opc = InFlag.getOpcode(); (void)Opc;
235
236  assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
237          (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
238         "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
239
240  SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
241  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
242  EVT VT = LHS.getValueType();
243
244  SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
245  SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
246                                            SDValue(Carry, 0), RHS);
247  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
248                              SDValue(AddCarry, 0));
249}
250
251/// ComplexPattern used on MipsInstrInfo
252/// Used on Mips Load/Store instructions
253bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
254                                          SDValue &Offset) const {
255  EVT ValTy = Addr.getValueType();
256
257  // if Address is FI, get the TargetFrameIndex.
258  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
259    Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260    Offset = CurDAG->getTargetConstant(0, ValTy);
261    return true;
262  }
263
264  // on PIC code Load GA
265  if (Addr.getOpcode() == MipsISD::Wrapper) {
266    Base   = Addr.getOperand(0);
267    Offset = Addr.getOperand(1);
268    return true;
269  }
270
271  if (TM.getRelocationModel() != Reloc::PIC_) {
272    if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
273        Addr.getOpcode() == ISD::TargetGlobalAddress))
274      return false;
275  }
276
277  // Addresses of the form FI+const or FI|const
278  if (CurDAG->isBaseWithConstantOffset(Addr)) {
279    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
280    if (isInt<16>(CN->getSExtValue())) {
281
282      // If the first operand is a FI, get the TargetFI Node
283      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
284                                  (Addr.getOperand(0)))
285        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
286      else
287        Base = Addr.getOperand(0);
288
289      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
290      return true;
291    }
292  }
293
294  // Operand is a result from an ADD.
295  if (Addr.getOpcode() == ISD::ADD) {
296    // When loading from constant pools, load the lower address part in
297    // the instruction itself. Example, instead of:
298    //  lui $2, %hi($CPI1_0)
299    //  addiu $2, $2, %lo($CPI1_0)
300    //  lwc1 $f0, 0($2)
301    // Generate:
302    //  lui $2, %hi($CPI1_0)
303    //  lwc1 $f0, %lo($CPI1_0)($2)
304    if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
305        Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
306      SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
307      if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
308          isa<JumpTableSDNode>(Opnd0)) {
309        Base = Addr.getOperand(0);
310        Offset = Opnd0;
311        return true;
312      }
313    }
314  }
315
316  return false;
317}
318
319/// ComplexPattern used on MipsInstrInfo
320/// Used on Mips Load/Store instructions
321bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
322                                          SDValue &Offset) const {
323  // Operand is a result from an ADD.
324  if (Addr.getOpcode() == ISD::ADD) {
325    Base = Addr.getOperand(0);
326    Offset = Addr.getOperand(1);
327    return true;
328  }
329
330  return false;
331}
332
333bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
334                                           SDValue &Offset) const {
335  Base = Addr;
336  Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
337  return true;
338}
339
340bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
341                                       SDValue &Offset) const {
342  return selectAddrRegImm(Addr, Base, Offset) ||
343    selectAddrDefault(Addr, Base, Offset);
344}
345
346/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
347bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
348                                            SDValue &Offset) const {
349  EVT ValTy = Addr.getValueType();
350
351  // Addresses of the form FI+const or FI|const
352  if (CurDAG->isBaseWithConstantOffset(Addr)) {
353    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
354    if (isInt<12>(CN->getSExtValue())) {
355
356      // If the first operand is a FI then get the TargetFI Node
357      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
358                                  (Addr.getOperand(0)))
359        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
360      else
361        Base = Addr.getOperand(0);
362
363      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
364      return true;
365    }
366  }
367
368  return false;
369}
370
371bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
372                                         SDValue &Offset) const {
373  return selectAddrRegImm12(Addr, Base, Offset) ||
374    selectAddrDefault(Addr, Base, Offset);
375}
376
377// Select constant vector splats.
378//
379// Returns true and sets Imm if:
380// * MSA is enabled
381// * N is a ISD::BUILD_VECTOR representing a constant splat
382// * The splat value fits in a signed 32-bit value.
383//
384// That last requirement isn't strictly a requirement of the instruction set
385// but it simplifies the callers by allowing them to assume they don't have to
386// handle 64-bit values. The callers will also be placing stricter requirements
387// on the immediates so this doesn't prohibit selection of legal immediates.
388bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
389  if (!Subtarget.hasMSA())
390    return false;
391
392  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
393
394  if (Node == NULL)
395    return false;
396
397  APInt SplatValue, SplatUndef;
398  unsigned SplatBitSize;
399  bool HasAnyUndefs;
400
401  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
402                             HasAnyUndefs, 8,
403                             !Subtarget.isLittle()))
404    return false;
405
406  // None of the immediate forms can handle more than 32 bits
407  if (!SplatValue.isIntN(32))
408    return false;
409
410  Imm = SplatValue;
411
412  return true;
413}
414
415// Select constant vector splats.
416//
417// In addition to the requirements of selectVSplat(), this function returns
418// true and sets Imm if:
419// * The splat value is the same width as the elements of the vector
420// * The splat value fits in an integer with the specified signed-ness and
421//   width.
422//
423// This function looks through ISD::BITCAST nodes.
424// TODO: This might not be appropriate for big-endian MSA since BITCAST is
425//       sometimes a shuffle in big-endian mode.
426//
427// It's worth noting that this function is not used as part of the selection
428// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
429// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
430// MipsSEDAGToDAGISel::selectNode.
431bool MipsSEDAGToDAGISel::
432selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
433                   unsigned ImmBitSize) const {
434  APInt ImmValue;
435  EVT EltTy = N->getValueType(0).getVectorElementType();
436
437  if (N->getOpcode() == ISD::BITCAST)
438    N = N->getOperand(0);
439
440  if (selectVSplat (N.getNode(), ImmValue) &&
441      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
442    if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
443        (!Signed && ImmValue.isIntN(ImmBitSize))) {
444      Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
445      return true;
446    }
447  }
448
449  return false;
450}
451
452// Select constant vector splats.
453bool MipsSEDAGToDAGISel::
454selectVSplatUimm3(SDValue N, SDValue &Imm) const {
455  return selectVSplatCommon(N, Imm, false, 3);
456}
457
458// Select constant vector splats.
459bool MipsSEDAGToDAGISel::
460selectVSplatUimm4(SDValue N, SDValue &Imm) const {
461  return selectVSplatCommon(N, Imm, false, 4);
462}
463
464// Select constant vector splats.
465bool MipsSEDAGToDAGISel::
466selectVSplatUimm5(SDValue N, SDValue &Imm) const {
467  return selectVSplatCommon(N, Imm, false, 5);
468}
469
470// Select constant vector splats.
471bool MipsSEDAGToDAGISel::
472selectVSplatUimm6(SDValue N, SDValue &Imm) const {
473  return selectVSplatCommon(N, Imm, false, 6);
474}
475
476// Select constant vector splats.
477bool MipsSEDAGToDAGISel::
478selectVSplatUimm8(SDValue N, SDValue &Imm) const {
479  return selectVSplatCommon(N, Imm, false, 8);
480}
481
482// Select constant vector splats.
483bool MipsSEDAGToDAGISel::
484selectVSplatSimm5(SDValue N, SDValue &Imm) const {
485  return selectVSplatCommon(N, Imm, true, 5);
486}
487
488// Select constant vector splats whose value is a power of 2.
489//
490// In addition to the requirements of selectVSplat(), this function returns
491// true and sets Imm if:
492// * The splat value is the same width as the elements of the vector
493// * The splat value is a power of two.
494//
495// This function looks through ISD::BITCAST nodes.
496// TODO: This might not be appropriate for big-endian MSA since BITCAST is
497//       sometimes a shuffle in big-endian mode.
498bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
499  APInt ImmValue;
500  EVT EltTy = N->getValueType(0).getVectorElementType();
501
502  if (N->getOpcode() == ISD::BITCAST)
503    N = N->getOperand(0);
504
505  if (selectVSplat (N.getNode(), ImmValue) &&
506      ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
507    int32_t Log2 = ImmValue.exactLogBase2();
508
509    if (Log2 != -1) {
510      Imm = CurDAG->getTargetConstant(Log2, EltTy);
511      return true;
512    }
513  }
514
515  return false;
516}
517
518std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
519  unsigned Opcode = Node->getOpcode();
520  SDLoc DL(Node);
521
522  ///
523  // Instruction Selection not handled by the auto-generated
524  // tablegen selection should be handled here.
525  ///
526  SDNode *Result;
527
528  switch(Opcode) {
529  default: break;
530
531  case ISD::SUBE: {
532    SDValue InFlag = Node->getOperand(2);
533    Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
534    return std::make_pair(true, Result);
535  }
536
537  case ISD::ADDE: {
538    if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
539      break;
540    SDValue InFlag = Node->getOperand(2);
541    Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
542    return std::make_pair(true, Result);
543  }
544
545  case ISD::ConstantFP: {
546    ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
547    if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
548      if (Subtarget.hasMips64()) {
549        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
550                                              Mips::ZERO_64, MVT::i64);
551        Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
552      } else {
553        SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
554                                              Mips::ZERO, MVT::i32);
555        Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
556                                        Zero);
557      }
558
559      return std::make_pair(true, Result);
560    }
561    break;
562  }
563
564  case ISD::Constant: {
565    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
566    unsigned Size = CN->getValueSizeInBits(0);
567
568    if (Size == 32)
569      break;
570
571    MipsAnalyzeImmediate AnalyzeImm;
572    int64_t Imm = CN->getSExtValue();
573
574    const MipsAnalyzeImmediate::InstSeq &Seq =
575      AnalyzeImm.Analyze(Imm, Size, false);
576
577    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
578    SDLoc DL(CN);
579    SDNode *RegOpnd;
580    SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
581                                                MVT::i64);
582
583    // The first instruction can be a LUi which is different from other
584    // instructions (ADDiu, ORI and SLL) in that it does not have a register
585    // operand.
586    if (Inst->Opc == Mips::LUi64)
587      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
588    else
589      RegOpnd =
590        CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
591                               CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
592                               ImmOpnd);
593
594    // The remaining instructions in the sequence are handled here.
595    for (++Inst; Inst != Seq.end(); ++Inst) {
596      ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
597                                          MVT::i64);
598      RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
599                                       SDValue(RegOpnd, 0), ImmOpnd);
600    }
601
602    return std::make_pair(true, RegOpnd);
603  }
604
605  case ISD::INTRINSIC_W_CHAIN: {
606    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
607    default:
608      break;
609
610    case Intrinsic::mips_cfcmsa: {
611      SDValue ChainIn = Node->getOperand(0);
612      SDValue RegIdx = Node->getOperand(2);
613      SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
614                                           getMSACtrlReg(RegIdx), MVT::i32);
615      return std::make_pair(true, Reg.getNode());
616    }
617    }
618    break;
619  }
620
621  case ISD::INTRINSIC_WO_CHAIN: {
622    switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
623    default:
624      break;
625
626    case Intrinsic::mips_move_v:
627      // Like an assignment but will always produce a move.v even if
628      // unnecessary.
629      return std::make_pair(true,
630                            CurDAG->getMachineNode(Mips::MOVE_V, DL,
631                                                   Node->getValueType(0),
632                                                   Node->getOperand(1)));
633    }
634    break;
635  }
636
637  case ISD::INTRINSIC_VOID: {
638    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
639    default:
640      break;
641
642    case Intrinsic::mips_ctcmsa: {
643      SDValue ChainIn = Node->getOperand(0);
644      SDValue RegIdx  = Node->getOperand(2);
645      SDValue Value   = Node->getOperand(3);
646      SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
647                                              getMSACtrlReg(RegIdx), Value);
648      return std::make_pair(true, ChainOut.getNode());
649    }
650    }
651    break;
652  }
653
654  case MipsISD::ThreadPointer: {
655    EVT PtrVT = getTargetLowering()->getPointerTy();
656    unsigned RdhwrOpc, DestReg;
657
658    if (PtrVT == MVT::i32) {
659      RdhwrOpc = Mips::RDHWR;
660      DestReg = Mips::V1;
661    } else {
662      RdhwrOpc = Mips::RDHWR64;
663      DestReg = Mips::V1_64;
664    }
665
666    SDNode *Rdhwr =
667      CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
668                             Node->getValueType(0),
669                             CurDAG->getRegister(Mips::HWR29, MVT::i32));
670    SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
671                                         SDValue(Rdhwr, 0));
672    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
673    ReplaceUses(SDValue(Node, 0), ResNode);
674    return std::make_pair(true, ResNode.getNode());
675  }
676
677  case MipsISD::InsertLOHI: {
678    unsigned RCID = Subtarget.hasDSP() ? Mips::ACC64DSPRegClassID :
679                                         Mips::ACC64RegClassID;
680    SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
681    SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
682    SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
683    const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
684                            Node->getOperand(1), HiIdx };
685    SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
686                                         MVT::Untyped, Ops);
687    return std::make_pair(true, Res);
688  }
689
690  case ISD::BUILD_VECTOR: {
691    // Select appropriate ldi.[bhwd] instructions for constant splats of
692    // 128-bit when MSA is enabled. Fixup any register class mismatches that
693    // occur as a result.
694    //
695    // This allows the compiler to use a wider range of immediates than would
696    // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
697    // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
698    // 0x01010101 } without using a constant pool. This would be sub-optimal
699    // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
700    // same set/ of registers. Similarly, ldi.h isn't capable of producing {
701    // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
702
703    BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
704    APInt SplatValue, SplatUndef;
705    unsigned SplatBitSize;
706    bool HasAnyUndefs;
707    unsigned LdiOp;
708    EVT ResVecTy = BVN->getValueType(0);
709    EVT ViaVecTy;
710
711    if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector())
712      return std::make_pair(false, (SDNode*)NULL);
713
714    if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
715                              HasAnyUndefs, 8,
716                              !Subtarget.isLittle()))
717      return std::make_pair(false, (SDNode*)NULL);
718
719    switch (SplatBitSize) {
720    default:
721      return std::make_pair(false, (SDNode*)NULL);
722    case 8:
723      LdiOp = Mips::LDI_B;
724      ViaVecTy = MVT::v16i8;
725      break;
726    case 16:
727      LdiOp = Mips::LDI_H;
728      ViaVecTy = MVT::v8i16;
729      break;
730    case 32:
731      LdiOp = Mips::LDI_W;
732      ViaVecTy = MVT::v4i32;
733      break;
734    case 64:
735      LdiOp = Mips::LDI_D;
736      ViaVecTy = MVT::v2i64;
737      break;
738    }
739
740    if (!SplatValue.isSignedIntN(10))
741      return std::make_pair(false, (SDNode*)NULL);
742
743    SDValue Imm = CurDAG->getTargetConstant(SplatValue,
744                                            ViaVecTy.getVectorElementType());
745
746    SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
747
748    if (ResVecTy != ViaVecTy) {
749      // If LdiOp is writing to a different register class to ResVecTy, then
750      // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
751      // since the source and destination register sets contain the same
752      // registers.
753      const TargetLowering *TLI = getTargetLowering();
754      MVT ResVecTySimple = ResVecTy.getSimpleVT();
755      const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
756      Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
757                                   ResVecTy, SDValue(Res, 0),
758                                   CurDAG->getTargetConstant(RC->getID(),
759                                                             MVT::i32));
760    }
761
762    return std::make_pair(true, Res);
763  }
764
765  }
766
767  return std::make_pair(false, (SDNode*)NULL);
768}
769
770FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
771  return new MipsSEDAGToDAGISel(TM);
772}
773