MipsSEISelLowering.cpp revision 38a10ff063971c2f7f7384cceba3253bca32e27a 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93
94    setTargetDAGCombine(ISD::AND);
95    setTargetDAGCombine(ISD::SRA);
96    setTargetDAGCombine(ISD::VSELECT);
97    setTargetDAGCombine(ISD::XOR);
98  }
99
100  if (!Subtarget->mipsSEUsesSoftFloat()) {
101    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
102
103    // When dealing with single precision only, use libcalls
104    if (!Subtarget->isSingleFloat()) {
105      if (Subtarget->isFP64bit())
106        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
107      else
108        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
109    }
110  }
111
112  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
113  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
114  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
115  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
116
117  if (HasMips64) {
118    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
119    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
120    setOperationAction(ISD::MUL,              MVT::i64, Custom);
121  }
122
123  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
124  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
125
126  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
127  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
128  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
129  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
130  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
131  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
132  setOperationAction(ISD::STORE,              MVT::i32, Custom);
133
134  setTargetDAGCombine(ISD::ADDE);
135  setTargetDAGCombine(ISD::SUBE);
136  setTargetDAGCombine(ISD::MUL);
137
138  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
139  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
140  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141
142  if (NoDPLoadStore) {
143    setOperationAction(ISD::LOAD, MVT::f64, Custom);
144    setOperationAction(ISD::STORE, MVT::f64, Custom);
145  }
146
147  computeRegisterProperties();
148}
149
150const MipsTargetLowering *
151llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
152  return new MipsSETargetLowering(TM);
153}
154
155// Enable MSA support for the given integer type and Register class.
156void MipsSETargetLowering::
157addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
158  addRegisterClass(Ty, RC);
159
160  // Expand all builtin opcodes.
161  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
162    setOperationAction(Opc, Ty, Expand);
163
164  setOperationAction(ISD::BITCAST, Ty, Legal);
165  setOperationAction(ISD::LOAD, Ty, Legal);
166  setOperationAction(ISD::STORE, Ty, Legal);
167  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
168  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
169  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
170
171  setOperationAction(ISD::ADD, Ty, Legal);
172  setOperationAction(ISD::AND, Ty, Legal);
173  setOperationAction(ISD::CTLZ, Ty, Legal);
174  setOperationAction(ISD::CTPOP, Ty, Legal);
175  setOperationAction(ISD::MUL, Ty, Legal);
176  setOperationAction(ISD::OR, Ty, Legal);
177  setOperationAction(ISD::SDIV, Ty, Legal);
178  setOperationAction(ISD::SHL, Ty, Legal);
179  setOperationAction(ISD::SRA, Ty, Legal);
180  setOperationAction(ISD::SRL, Ty, Legal);
181  setOperationAction(ISD::SUB, Ty, Legal);
182  setOperationAction(ISD::UDIV, Ty, Legal);
183  setOperationAction(ISD::VSELECT, Ty, Legal);
184  setOperationAction(ISD::XOR, Ty, Legal);
185
186  setOperationAction(ISD::SETCC, Ty, Legal);
187  setCondCodeAction(ISD::SETNE, Ty, Expand);
188  setCondCodeAction(ISD::SETGE, Ty, Expand);
189  setCondCodeAction(ISD::SETGT, Ty, Expand);
190  setCondCodeAction(ISD::SETUGE, Ty, Expand);
191  setCondCodeAction(ISD::SETUGT, Ty, Expand);
192}
193
194// Enable MSA support for the given floating-point type and Register class.
195void MipsSETargetLowering::
196addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
197  addRegisterClass(Ty, RC);
198
199  // Expand all builtin opcodes.
200  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
201    setOperationAction(Opc, Ty, Expand);
202
203  setOperationAction(ISD::LOAD, Ty, Legal);
204  setOperationAction(ISD::STORE, Ty, Legal);
205  setOperationAction(ISD::BITCAST, Ty, Legal);
206  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
207
208  if (Ty != MVT::v8f16) {
209    setOperationAction(ISD::FADD,  Ty, Legal);
210    setOperationAction(ISD::FDIV,  Ty, Legal);
211    setOperationAction(ISD::FLOG2, Ty, Legal);
212    setOperationAction(ISD::FMUL,  Ty, Legal);
213    setOperationAction(ISD::FRINT, Ty, Legal);
214    setOperationAction(ISD::FSQRT, Ty, Legal);
215    setOperationAction(ISD::FSUB,  Ty, Legal);
216    setOperationAction(ISD::VSELECT, Ty, Legal);
217
218    setOperationAction(ISD::SETCC, Ty, Legal);
219    setCondCodeAction(ISD::SETOGE, Ty, Expand);
220    setCondCodeAction(ISD::SETOGT, Ty, Expand);
221    setCondCodeAction(ISD::SETUGE, Ty, Expand);
222    setCondCodeAction(ISD::SETUGT, Ty, Expand);
223    setCondCodeAction(ISD::SETGE,  Ty, Expand);
224    setCondCodeAction(ISD::SETGT,  Ty, Expand);
225  }
226}
227
228bool
229MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
230  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
231
232  switch (SVT) {
233  case MVT::i64:
234  case MVT::i32:
235    if (Fast)
236      *Fast = true;
237    return true;
238  default:
239    return false;
240  }
241}
242
243SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
244                                             SelectionDAG &DAG) const {
245  switch(Op.getOpcode()) {
246  case ISD::LOAD:  return lowerLOAD(Op, DAG);
247  case ISD::STORE: return lowerSTORE(Op, DAG);
248  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
249  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
250  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
251  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
252  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
253  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
254  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
255                                          DAG);
256  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
257  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
258  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
259  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
260  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
261  }
262
263  return MipsTargetLowering::LowerOperation(Op, DAG);
264}
265
266// selectMADD -
267// Transforms a subgraph in CurDAG if the following pattern is found:
268//  (addc multLo, Lo0), (adde multHi, Hi0),
269// where,
270//  multHi/Lo: product of multiplication
271//  Lo0: initial value of Lo register
272//  Hi0: initial value of Hi register
273// Return true if pattern matching was successful.
274static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
275  // ADDENode's second operand must be a flag output of an ADDC node in order
276  // for the matching to be successful.
277  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
278
279  if (ADDCNode->getOpcode() != ISD::ADDC)
280    return false;
281
282  SDValue MultHi = ADDENode->getOperand(0);
283  SDValue MultLo = ADDCNode->getOperand(0);
284  SDNode *MultNode = MultHi.getNode();
285  unsigned MultOpc = MultHi.getOpcode();
286
287  // MultHi and MultLo must be generated by the same node,
288  if (MultLo.getNode() != MultNode)
289    return false;
290
291  // and it must be a multiplication.
292  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
293    return false;
294
295  // MultLo amd MultHi must be the first and second output of MultNode
296  // respectively.
297  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
298    return false;
299
300  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
301  // of the values of MultNode, in which case MultNode will be removed in later
302  // phases.
303  // If there exist users other than ADDENode or ADDCNode, this function returns
304  // here, which will result in MultNode being mapped to a single MULT
305  // instruction node rather than a pair of MULT and MADD instructions being
306  // produced.
307  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
308    return false;
309
310  SDLoc DL(ADDENode);
311
312  // Initialize accumulator.
313  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
314                                  ADDCNode->getOperand(1),
315                                  ADDENode->getOperand(1));
316
317  // create MipsMAdd(u) node
318  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
319
320  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
321                                 MultNode->getOperand(0),// Factor 0
322                                 MultNode->getOperand(1),// Factor 1
323                                 ACCIn);
324
325  // replace uses of adde and addc here
326  if (!SDValue(ADDCNode, 0).use_empty()) {
327    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
328    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
329                                    LoIdx);
330    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
331  }
332  if (!SDValue(ADDENode, 0).use_empty()) {
333    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
334    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
335                                    HiIdx);
336    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
337  }
338
339  return true;
340}
341
342// selectMSUB -
343// Transforms a subgraph in CurDAG if the following pattern is found:
344//  (addc Lo0, multLo), (sube Hi0, multHi),
345// where,
346//  multHi/Lo: product of multiplication
347//  Lo0: initial value of Lo register
348//  Hi0: initial value of Hi register
349// Return true if pattern matching was successful.
350static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
351  // SUBENode's second operand must be a flag output of an SUBC node in order
352  // for the matching to be successful.
353  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
354
355  if (SUBCNode->getOpcode() != ISD::SUBC)
356    return false;
357
358  SDValue MultHi = SUBENode->getOperand(1);
359  SDValue MultLo = SUBCNode->getOperand(1);
360  SDNode *MultNode = MultHi.getNode();
361  unsigned MultOpc = MultHi.getOpcode();
362
363  // MultHi and MultLo must be generated by the same node,
364  if (MultLo.getNode() != MultNode)
365    return false;
366
367  // and it must be a multiplication.
368  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
369    return false;
370
371  // MultLo amd MultHi must be the first and second output of MultNode
372  // respectively.
373  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
374    return false;
375
376  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
377  // of the values of MultNode, in which case MultNode will be removed in later
378  // phases.
379  // If there exist users other than SUBENode or SUBCNode, this function returns
380  // here, which will result in MultNode being mapped to a single MULT
381  // instruction node rather than a pair of MULT and MSUB instructions being
382  // produced.
383  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
384    return false;
385
386  SDLoc DL(SUBENode);
387
388  // Initialize accumulator.
389  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
390                                  SUBCNode->getOperand(0),
391                                  SUBENode->getOperand(0));
392
393  // create MipsSub(u) node
394  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
395
396  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
397                                 MultNode->getOperand(0),// Factor 0
398                                 MultNode->getOperand(1),// Factor 1
399                                 ACCIn);
400
401  // replace uses of sube and subc here
402  if (!SDValue(SUBCNode, 0).use_empty()) {
403    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
404    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
405                                    LoIdx);
406    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
407  }
408  if (!SDValue(SUBENode, 0).use_empty()) {
409    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
410    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
411                                    HiIdx);
412    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
413  }
414
415  return true;
416}
417
418static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
419                                  TargetLowering::DAGCombinerInfo &DCI,
420                                  const MipsSubtarget *Subtarget) {
421  if (DCI.isBeforeLegalize())
422    return SDValue();
423
424  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
425      selectMADD(N, &DAG))
426    return SDValue(N, 0);
427
428  return SDValue();
429}
430
431// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
432//
433// Performs the following transformations:
434// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
435//   sign/zero-extension is completely overwritten by the new one performed by
436//   the ISD::AND.
437// - Removes redundant zero extensions performed by an ISD::AND.
438static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
439                                 TargetLowering::DAGCombinerInfo &DCI,
440                                 const MipsSubtarget *Subtarget) {
441  if (!Subtarget->hasMSA())
442    return SDValue();
443
444  SDValue Op0 = N->getOperand(0);
445  SDValue Op1 = N->getOperand(1);
446  unsigned Op0Opcode = Op0->getOpcode();
447
448  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
449  // where $d + 1 == 2^n and n == 32
450  // or    $d + 1 == 2^n and n <= 32 and ZExt
451  // -> (MipsVExtractZExt $a, $b, $c)
452  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
453      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
454    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
455
456    if (!Mask)
457      return SDValue();
458
459    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
460
461    if (Log2IfPositive <= 0)
462      return SDValue(); // Mask+1 is not a power of 2
463
464    SDValue Op0Op2 = Op0->getOperand(2);
465    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
466    unsigned ExtendTySize = ExtendTy.getSizeInBits();
467    unsigned Log2 = Log2IfPositive;
468
469    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
470        Log2 == ExtendTySize) {
471      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
472      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
473                      Op0->getVTList(), Ops, Op0->getNumOperands());
474      return Op0;
475    }
476  }
477
478  return SDValue();
479}
480
481static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
482                                  TargetLowering::DAGCombinerInfo &DCI,
483                                  const MipsSubtarget *Subtarget) {
484  if (DCI.isBeforeLegalize())
485    return SDValue();
486
487  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
488      selectMSUB(N, &DAG))
489    return SDValue(N, 0);
490
491  return SDValue();
492}
493
494static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
495                            EVT ShiftTy, SelectionDAG &DAG) {
496  // Clear the upper (64 - VT.sizeInBits) bits.
497  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
498
499  // Return 0.
500  if (C == 0)
501    return DAG.getConstant(0, VT);
502
503  // Return x.
504  if (C == 1)
505    return X;
506
507  // If c is power of 2, return (shl x, log2(c)).
508  if (isPowerOf2_64(C))
509    return DAG.getNode(ISD::SHL, DL, VT, X,
510                       DAG.getConstant(Log2_64(C), ShiftTy));
511
512  unsigned Log2Ceil = Log2_64_Ceil(C);
513  uint64_t Floor = 1LL << Log2_64(C);
514  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
515
516  // If |c - floor_c| <= |c - ceil_c|,
517  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
518  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
519  if (C - Floor <= Ceil - C) {
520    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
521    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
522    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
523  }
524
525  // If |c - floor_c| > |c - ceil_c|,
526  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
527  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
528  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
529  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
530}
531
532static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
533                                 const TargetLowering::DAGCombinerInfo &DCI,
534                                 const MipsSETargetLowering *TL) {
535  EVT VT = N->getValueType(0);
536
537  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
538    if (!VT.isVector())
539      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
540                          VT, TL->getScalarShiftAmountTy(VT), DAG);
541
542  return SDValue(N, 0);
543}
544
545static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
546                                      SelectionDAG &DAG,
547                                      const MipsSubtarget *Subtarget) {
548  // See if this is a vector splat immediate node.
549  APInt SplatValue, SplatUndef;
550  unsigned SplatBitSize;
551  bool HasAnyUndefs;
552  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
553  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
554
555  if (!BV ||
556      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
557                           EltSize, !Subtarget->isLittle()) ||
558      (SplatBitSize != EltSize) ||
559      (SplatValue.getZExtValue() >= EltSize))
560    return SDValue();
561
562  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
563                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
564}
565
566static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
567                                 TargetLowering::DAGCombinerInfo &DCI,
568                                 const MipsSubtarget *Subtarget) {
569  EVT Ty = N->getValueType(0);
570
571  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
572    return SDValue();
573
574  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
575}
576
577// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
578// constant splats into MipsISD::SHRA_DSP for DSPr2.
579//
580// Performs the following transformations:
581// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
582//   sign/zero-extension is completely overwritten by the new one performed by
583//   the ISD::SRA and ISD::SHL nodes.
584// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
585//   sequence.
586//
587// See performDSPShiftCombine for more information about the transformation
588// used for DSPr2.
589static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
590                                 TargetLowering::DAGCombinerInfo &DCI,
591                                 const MipsSubtarget *Subtarget) {
592  EVT Ty = N->getValueType(0);
593
594  if (Subtarget->hasMSA()) {
595    SDValue Op0 = N->getOperand(0);
596    SDValue Op1 = N->getOperand(1);
597
598    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
599    // where $d + sizeof($c) == 32
600    // or    $d + sizeof($c) <= 32 and SExt
601    // -> (MipsVExtractSExt $a, $b, $c)
602    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
603      SDValue Op0Op0 = Op0->getOperand(0);
604      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
605
606      if (!ShAmount)
607        return SDValue();
608
609      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
610      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
611
612      if (TotalBits == 32 ||
613          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
614           TotalBits <= 32)) {
615        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
616                          Op0Op0->getOperand(2) };
617        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
618                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
619        return Op0Op0;
620      }
621    }
622  }
623
624  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
625    return SDValue();
626
627  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
628}
629
630
631static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
632                                 TargetLowering::DAGCombinerInfo &DCI,
633                                 const MipsSubtarget *Subtarget) {
634  EVT Ty = N->getValueType(0);
635
636  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
637    return SDValue();
638
639  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
640}
641
642static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
643  bool IsV216 = (Ty == MVT::v2i16);
644
645  switch (CC) {
646  case ISD::SETEQ:
647  case ISD::SETNE:  return true;
648  case ISD::SETLT:
649  case ISD::SETLE:
650  case ISD::SETGT:
651  case ISD::SETGE:  return IsV216;
652  case ISD::SETULT:
653  case ISD::SETULE:
654  case ISD::SETUGT:
655  case ISD::SETUGE: return !IsV216;
656  default:          return false;
657  }
658}
659
660static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
661  EVT Ty = N->getValueType(0);
662
663  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
664    return SDValue();
665
666  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
667    return SDValue();
668
669  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
670                     N->getOperand(1), N->getOperand(2));
671}
672
673static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
674  EVT Ty = N->getValueType(0);
675
676  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
677    return SDValue();
678
679  SDValue SetCC = N->getOperand(0);
680
681  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
682    return SDValue();
683
684  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
685                     SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
686                     N->getOperand(2), SetCC.getOperand(2));
687}
688
689static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
690                                 const MipsSubtarget *Subtarget) {
691  EVT Ty = N->getValueType(0);
692
693  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
694    // Try the following combines:
695    //   (xor (or $a, $b), (build_vector allones))
696    //   (xor (or $a, $b), (bitcast (build_vector allones)))
697    SDValue Op0 = N->getOperand(0);
698    SDValue Op1 = N->getOperand(1);
699    SDValue NotOp;
700    ConstantSDNode *Const;
701
702    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
703      NotOp = Op1;
704    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
705      NotOp = Op0;
706    else if ((Op0->getOpcode() == MipsISD::VSPLAT ||
707              Op0->getOpcode() == MipsISD::VSPLATD) &&
708             (Const = dyn_cast<ConstantSDNode>(Op0->getOperand(0))) &&
709             Const->isAllOnesValue())
710      NotOp = Op1;
711    else if ((Op1->getOpcode() == MipsISD::VSPLAT ||
712              Op1->getOpcode() == MipsISD::VSPLATD) &&
713             (Const = dyn_cast<ConstantSDNode>(Op1->getOperand(0))) &&
714             Const->isAllOnesValue())
715      NotOp = Op0;
716    else
717      return SDValue();
718
719    if (NotOp->getOpcode() == ISD::OR)
720      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
721                         NotOp->getOperand(1));
722  }
723
724  return SDValue();
725}
726
727SDValue
728MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
729  SelectionDAG &DAG = DCI.DAG;
730  SDValue Val;
731
732  switch (N->getOpcode()) {
733  case ISD::ADDE:
734    return performADDECombine(N, DAG, DCI, Subtarget);
735  case ISD::AND:
736    Val = performANDCombine(N, DAG, DCI, Subtarget);
737    break;
738  case ISD::SUBE:
739    return performSUBECombine(N, DAG, DCI, Subtarget);
740  case ISD::MUL:
741    return performMULCombine(N, DAG, DCI, this);
742  case ISD::SHL:
743    return performSHLCombine(N, DAG, DCI, Subtarget);
744  case ISD::SRA:
745    return performSRACombine(N, DAG, DCI, Subtarget);
746  case ISD::SRL:
747    return performSRLCombine(N, DAG, DCI, Subtarget);
748  case ISD::VSELECT:
749    return performVSELECTCombine(N, DAG);
750  case ISD::XOR:
751    Val = performXORCombine(N, DAG, Subtarget);
752    break;
753  case ISD::SETCC:
754    Val = performSETCCCombine(N, DAG);
755    break;
756  }
757
758  if (Val.getNode())
759    return Val;
760
761  return MipsTargetLowering::PerformDAGCombine(N, DCI);
762}
763
764MachineBasicBlock *
765MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
766                                                  MachineBasicBlock *BB) const {
767  switch (MI->getOpcode()) {
768  default:
769    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
770  case Mips::BPOSGE32_PSEUDO:
771    return emitBPOSGE32(MI, BB);
772  case Mips::SNZ_B_PSEUDO:
773    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
774  case Mips::SNZ_H_PSEUDO:
775    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
776  case Mips::SNZ_W_PSEUDO:
777    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
778  case Mips::SNZ_D_PSEUDO:
779    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
780  case Mips::SNZ_V_PSEUDO:
781    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
782  case Mips::SZ_B_PSEUDO:
783    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
784  case Mips::SZ_H_PSEUDO:
785    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
786  case Mips::SZ_W_PSEUDO:
787    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
788  case Mips::SZ_D_PSEUDO:
789    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
790  case Mips::SZ_V_PSEUDO:
791    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
792  }
793}
794
795bool MipsSETargetLowering::
796isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
797                                  unsigned NextStackOffset,
798                                  const MipsFunctionInfo& FI) const {
799  if (!EnableMipsTailCalls)
800    return false;
801
802  // Return false if either the callee or caller has a byval argument.
803  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
804    return false;
805
806  // Return true if the callee's argument area is no larger than the
807  // caller's.
808  return NextStackOffset <= FI.getIncomingArgSize();
809}
810
811void MipsSETargetLowering::
812getOpndList(SmallVectorImpl<SDValue> &Ops,
813            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
814            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
815            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
816  // T9 should contain the address of the callee function if
817  // -reloction-model=pic or it is an indirect call.
818  if (IsPICCall || !GlobalOrExternal) {
819    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
820    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
821  } else
822    Ops.push_back(Callee);
823
824  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
825                                  InternalLinkage, CLI, Callee, Chain);
826}
827
828SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
829  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
830
831  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
832    return MipsTargetLowering::lowerLOAD(Op, DAG);
833
834  // Replace a double precision load with two i32 loads and a buildpair64.
835  SDLoc DL(Op);
836  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
837  EVT PtrVT = Ptr.getValueType();
838
839  // i32 load from lower address.
840  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
841                           MachinePointerInfo(), Nd.isVolatile(),
842                           Nd.isNonTemporal(), Nd.isInvariant(),
843                           Nd.getAlignment());
844
845  // i32 load from higher address.
846  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
847  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
848                           MachinePointerInfo(), Nd.isVolatile(),
849                           Nd.isNonTemporal(), Nd.isInvariant(),
850                           std::min(Nd.getAlignment(), 4U));
851
852  if (!Subtarget->isLittle())
853    std::swap(Lo, Hi);
854
855  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
856  SDValue Ops[2] = {BP, Hi.getValue(1)};
857  return DAG.getMergeValues(Ops, 2, DL);
858}
859
860SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
861  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
862
863  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
864    return MipsTargetLowering::lowerSTORE(Op, DAG);
865
866  // Replace a double precision store with two extractelement64s and i32 stores.
867  SDLoc DL(Op);
868  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
869  EVT PtrVT = Ptr.getValueType();
870  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
871                           Val, DAG.getConstant(0, MVT::i32));
872  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
873                           Val, DAG.getConstant(1, MVT::i32));
874
875  if (!Subtarget->isLittle())
876    std::swap(Lo, Hi);
877
878  // i32 store to lower address.
879  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
880                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
881                       Nd.getTBAAInfo());
882
883  // i32 store to higher address.
884  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
885  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
886                      Nd.isVolatile(), Nd.isNonTemporal(),
887                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
888}
889
890SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
891                                          bool HasLo, bool HasHi,
892                                          SelectionDAG &DAG) const {
893  EVT Ty = Op.getOperand(0).getValueType();
894  SDLoc DL(Op);
895  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
896                             Op.getOperand(0), Op.getOperand(1));
897  SDValue Lo, Hi;
898
899  if (HasLo)
900    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
901                     DAG.getConstant(Mips::sub_lo, MVT::i32));
902  if (HasHi)
903    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
904                     DAG.getConstant(Mips::sub_hi, MVT::i32));
905
906  if (!HasLo || !HasHi)
907    return HasLo ? Lo : Hi;
908
909  SDValue Vals[] = { Lo, Hi };
910  return DAG.getMergeValues(Vals, 2, DL);
911}
912
913
914static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
915  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
916                             DAG.getConstant(0, MVT::i32));
917  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
918                             DAG.getConstant(1, MVT::i32));
919  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
920}
921
922static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
923  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
924                           DAG.getConstant(Mips::sub_lo, MVT::i32));
925  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
926                           DAG.getConstant(Mips::sub_hi, MVT::i32));
927  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
928}
929
930// This function expands mips intrinsic nodes which have 64-bit input operands
931// or output values.
932//
933// out64 = intrinsic-node in64
934// =>
935// lo = copy (extract-element (in64, 0))
936// hi = copy (extract-element (in64, 1))
937// mips-specific-node
938// v0 = copy lo
939// v1 = copy hi
940// out64 = merge-values (v0, v1)
941//
942static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
943  SDLoc DL(Op);
944  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
945  SmallVector<SDValue, 3> Ops;
946  unsigned OpNo = 0;
947
948  // See if Op has a chain input.
949  if (HasChainIn)
950    Ops.push_back(Op->getOperand(OpNo++));
951
952  // The next operand is the intrinsic opcode.
953  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
954
955  // See if the next operand has type i64.
956  SDValue Opnd = Op->getOperand(++OpNo), In64;
957
958  if (Opnd.getValueType() == MVT::i64)
959    In64 = initAccumulator(Opnd, DL, DAG);
960  else
961    Ops.push_back(Opnd);
962
963  // Push the remaining operands.
964  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
965    Ops.push_back(Op->getOperand(OpNo));
966
967  // Add In64 to the end of the list.
968  if (In64.getNode())
969    Ops.push_back(In64);
970
971  // Scan output.
972  SmallVector<EVT, 2> ResTys;
973
974  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
975       I != E; ++I)
976    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
977
978  // Create node.
979  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
980  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
981
982  if (!HasChainIn)
983    return Out;
984
985  assert(Val->getValueType(1) == MVT::Other);
986  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
987  return DAG.getMergeValues(Vals, 2, DL);
988}
989
990static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
991  SDLoc DL(Op);
992  SDValue LHS = Op->getOperand(1);
993  SDValue RHS = Op->getOperand(2);
994  EVT ResTy = Op->getValueType(0);
995
996  SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
997
998  return Result;
999}
1000
1001static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
1002                                     unsigned Opc, SDValue RHS) {
1003  SDValue LHS = Op->getOperand(1);
1004  EVT ResTy = Op->getValueType(0);
1005
1006  return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
1007}
1008
1009static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1010  SDLoc DL(Op);
1011  SDValue Value = Op->getOperand(1);
1012  EVT ResTy = Op->getValueType(0);
1013
1014  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1015
1016  return Result;
1017}
1018
1019// Lower an MSA copy intrinsic into the specified SelectionDAG node
1020static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1021  SDLoc DL(Op);
1022  SDValue Vec = Op->getOperand(1);
1023  SDValue Idx = Op->getOperand(2);
1024  EVT ResTy = Op->getValueType(0);
1025  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1026
1027  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1028                               DAG.getValueType(EltTy));
1029
1030  return Result;
1031}
1032
1033// Lower an MSA insert intrinsic into the specified SelectionDAG node
1034static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1035  SDLoc DL(Op);
1036  SDValue Op0 = Op->getOperand(1);
1037  SDValue Op1 = Op->getOperand(2);
1038  SDValue Op2 = Op->getOperand(3);
1039  EVT ResTy = Op->getValueType(0);
1040
1041  SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
1042
1043  return Result;
1044}
1045
1046static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1047  EVT ResTy = Op->getValueType(0);
1048
1049  unsigned SplatOp = MipsISD::VSPLAT;
1050  if (ResTy == MVT::v2i64)
1051    SplatOp = MipsISD::VSPLATD;
1052
1053  return DAG.getNode(SplatOp, SDLoc(Op), ResTy, Op->getOperand(ImmOp));
1054}
1055
1056static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1057  SDLoc DL(Op);
1058  SDValue Value = Op->getOperand(1);
1059  EVT ResTy = Op->getValueType(0);
1060
1061  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1062
1063  return Result;
1064}
1065
1066SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1067                                                      SelectionDAG &DAG) const {
1068  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1069  default:
1070    return SDValue();
1071  case Intrinsic::mips_shilo:
1072    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1073  case Intrinsic::mips_dpau_h_qbl:
1074    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1075  case Intrinsic::mips_dpau_h_qbr:
1076    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1077  case Intrinsic::mips_dpsu_h_qbl:
1078    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1079  case Intrinsic::mips_dpsu_h_qbr:
1080    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1081  case Intrinsic::mips_dpa_w_ph:
1082    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1083  case Intrinsic::mips_dps_w_ph:
1084    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1085  case Intrinsic::mips_dpax_w_ph:
1086    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1087  case Intrinsic::mips_dpsx_w_ph:
1088    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1089  case Intrinsic::mips_mulsa_w_ph:
1090    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1091  case Intrinsic::mips_mult:
1092    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1093  case Intrinsic::mips_multu:
1094    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1095  case Intrinsic::mips_madd:
1096    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1097  case Intrinsic::mips_maddu:
1098    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1099  case Intrinsic::mips_msub:
1100    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1101  case Intrinsic::mips_msubu:
1102    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1103  case Intrinsic::mips_addv_b:
1104  case Intrinsic::mips_addv_h:
1105  case Intrinsic::mips_addv_w:
1106  case Intrinsic::mips_addv_d:
1107    return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
1108  case Intrinsic::mips_addvi_b:
1109  case Intrinsic::mips_addvi_h:
1110  case Intrinsic::mips_addvi_w:
1111  case Intrinsic::mips_addvi_d:
1112    return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
1113                                 lowerMSASplatImm(Op, 2, DAG));
1114  case Intrinsic::mips_and_v:
1115    return lowerMSABinaryIntr(Op, DAG, ISD::AND);
1116  case Intrinsic::mips_bnz_b:
1117  case Intrinsic::mips_bnz_h:
1118  case Intrinsic::mips_bnz_w:
1119  case Intrinsic::mips_bnz_d:
1120    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
1121  case Intrinsic::mips_bnz_v:
1122    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
1123  case Intrinsic::mips_bsel_v:
1124    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1125                       Op->getOperand(1), Op->getOperand(2),
1126                       Op->getOperand(3));
1127  case Intrinsic::mips_bseli_b:
1128    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1129                       Op->getOperand(1), Op->getOperand(2),
1130                       lowerMSASplatImm(Op, 3, DAG));
1131  case Intrinsic::mips_bz_b:
1132  case Intrinsic::mips_bz_h:
1133  case Intrinsic::mips_bz_w:
1134  case Intrinsic::mips_bz_d:
1135    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
1136  case Intrinsic::mips_bz_v:
1137    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
1138  case Intrinsic::mips_ceq_b:
1139  case Intrinsic::mips_ceq_h:
1140  case Intrinsic::mips_ceq_w:
1141  case Intrinsic::mips_ceq_d:
1142    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1143                        Op->getOperand(2), ISD::SETEQ);
1144  case Intrinsic::mips_ceqi_b:
1145  case Intrinsic::mips_ceqi_h:
1146  case Intrinsic::mips_ceqi_w:
1147  case Intrinsic::mips_ceqi_d:
1148    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1149                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1150  case Intrinsic::mips_cle_s_b:
1151  case Intrinsic::mips_cle_s_h:
1152  case Intrinsic::mips_cle_s_w:
1153  case Intrinsic::mips_cle_s_d:
1154    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1155                        Op->getOperand(2), ISD::SETLE);
1156  case Intrinsic::mips_clei_s_b:
1157  case Intrinsic::mips_clei_s_h:
1158  case Intrinsic::mips_clei_s_w:
1159  case Intrinsic::mips_clei_s_d:
1160    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1161                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1162  case Intrinsic::mips_cle_u_b:
1163  case Intrinsic::mips_cle_u_h:
1164  case Intrinsic::mips_cle_u_w:
1165  case Intrinsic::mips_cle_u_d:
1166    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1167                        Op->getOperand(2), ISD::SETULE);
1168  case Intrinsic::mips_clei_u_b:
1169  case Intrinsic::mips_clei_u_h:
1170  case Intrinsic::mips_clei_u_w:
1171  case Intrinsic::mips_clei_u_d:
1172    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1173                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1174  case Intrinsic::mips_clt_s_b:
1175  case Intrinsic::mips_clt_s_h:
1176  case Intrinsic::mips_clt_s_w:
1177  case Intrinsic::mips_clt_s_d:
1178    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1179                        Op->getOperand(2), ISD::SETLT);
1180  case Intrinsic::mips_clti_s_b:
1181  case Intrinsic::mips_clti_s_h:
1182  case Intrinsic::mips_clti_s_w:
1183  case Intrinsic::mips_clti_s_d:
1184    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1185                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1186  case Intrinsic::mips_clt_u_b:
1187  case Intrinsic::mips_clt_u_h:
1188  case Intrinsic::mips_clt_u_w:
1189  case Intrinsic::mips_clt_u_d:
1190    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1191                        Op->getOperand(2), ISD::SETULT);
1192  case Intrinsic::mips_clti_u_b:
1193  case Intrinsic::mips_clti_u_h:
1194  case Intrinsic::mips_clti_u_w:
1195  case Intrinsic::mips_clti_u_d:
1196    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1197                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1198  case Intrinsic::mips_copy_s_b:
1199  case Intrinsic::mips_copy_s_h:
1200  case Intrinsic::mips_copy_s_w:
1201    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1202  case Intrinsic::mips_copy_u_b:
1203  case Intrinsic::mips_copy_u_h:
1204  case Intrinsic::mips_copy_u_w:
1205    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1206  case Intrinsic::mips_div_s_b:
1207  case Intrinsic::mips_div_s_h:
1208  case Intrinsic::mips_div_s_w:
1209  case Intrinsic::mips_div_s_d:
1210    return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
1211  case Intrinsic::mips_div_u_b:
1212  case Intrinsic::mips_div_u_h:
1213  case Intrinsic::mips_div_u_w:
1214  case Intrinsic::mips_div_u_d:
1215    return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
1216  case Intrinsic::mips_fadd_w:
1217  case Intrinsic::mips_fadd_d:
1218    return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
1219  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1220  case Intrinsic::mips_fceq_w:
1221  case Intrinsic::mips_fceq_d:
1222    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1223                        Op->getOperand(2), ISD::SETOEQ);
1224  case Intrinsic::mips_fcle_w:
1225  case Intrinsic::mips_fcle_d:
1226    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1227                        Op->getOperand(2), ISD::SETOLE);
1228  case Intrinsic::mips_fclt_w:
1229  case Intrinsic::mips_fclt_d:
1230    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1231                        Op->getOperand(2), ISD::SETOLT);
1232  case Intrinsic::mips_fcne_w:
1233  case Intrinsic::mips_fcne_d:
1234    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1235                        Op->getOperand(2), ISD::SETONE);
1236  case Intrinsic::mips_fcor_w:
1237  case Intrinsic::mips_fcor_d:
1238    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1239                        Op->getOperand(2), ISD::SETO);
1240  case Intrinsic::mips_fcueq_w:
1241  case Intrinsic::mips_fcueq_d:
1242    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1243                        Op->getOperand(2), ISD::SETUEQ);
1244  case Intrinsic::mips_fcule_w:
1245  case Intrinsic::mips_fcule_d:
1246    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1247                        Op->getOperand(2), ISD::SETULE);
1248  case Intrinsic::mips_fcult_w:
1249  case Intrinsic::mips_fcult_d:
1250    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1251                        Op->getOperand(2), ISD::SETULT);
1252  case Intrinsic::mips_fcun_w:
1253  case Intrinsic::mips_fcun_d:
1254    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1255                        Op->getOperand(2), ISD::SETUO);
1256  case Intrinsic::mips_fcune_w:
1257  case Intrinsic::mips_fcune_d:
1258    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1259                        Op->getOperand(2), ISD::SETUNE);
1260  case Intrinsic::mips_fdiv_w:
1261  case Intrinsic::mips_fdiv_d:
1262    return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
1263  case Intrinsic::mips_fill_b:
1264  case Intrinsic::mips_fill_h:
1265  case Intrinsic::mips_fill_w:
1266    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1267  case Intrinsic::mips_flog2_w:
1268  case Intrinsic::mips_flog2_d:
1269    return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
1270  case Intrinsic::mips_fmul_w:
1271  case Intrinsic::mips_fmul_d:
1272    return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
1273  case Intrinsic::mips_frint_w:
1274  case Intrinsic::mips_frint_d:
1275    return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
1276  case Intrinsic::mips_fsqrt_w:
1277  case Intrinsic::mips_fsqrt_d:
1278    return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
1279  case Intrinsic::mips_fsub_w:
1280  case Intrinsic::mips_fsub_d:
1281    return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
1282  case Intrinsic::mips_insert_b:
1283  case Intrinsic::mips_insert_h:
1284  case Intrinsic::mips_insert_w:
1285    return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
1286  case Intrinsic::mips_ldi_b:
1287  case Intrinsic::mips_ldi_h:
1288  case Intrinsic::mips_ldi_w:
1289  case Intrinsic::mips_ldi_d:
1290    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1291  case Intrinsic::mips_mulv_b:
1292  case Intrinsic::mips_mulv_h:
1293  case Intrinsic::mips_mulv_w:
1294  case Intrinsic::mips_mulv_d:
1295    return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
1296  case Intrinsic::mips_nlzc_b:
1297  case Intrinsic::mips_nlzc_h:
1298  case Intrinsic::mips_nlzc_w:
1299  case Intrinsic::mips_nlzc_d:
1300    return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
1301  case Intrinsic::mips_nor_v: {
1302    SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
1303    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1304  }
1305  case Intrinsic::mips_or_v:
1306    return lowerMSABinaryIntr(Op, DAG, ISD::OR);
1307  case Intrinsic::mips_pcnt_b:
1308  case Intrinsic::mips_pcnt_h:
1309  case Intrinsic::mips_pcnt_w:
1310  case Intrinsic::mips_pcnt_d:
1311    return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
1312  case Intrinsic::mips_sll_b:
1313  case Intrinsic::mips_sll_h:
1314  case Intrinsic::mips_sll_w:
1315  case Intrinsic::mips_sll_d:
1316    return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
1317  case Intrinsic::mips_slli_b:
1318  case Intrinsic::mips_slli_h:
1319  case Intrinsic::mips_slli_w:
1320  case Intrinsic::mips_slli_d:
1321    return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
1322                                 lowerMSASplatImm(Op, 2, DAG));
1323  case Intrinsic::mips_sra_b:
1324  case Intrinsic::mips_sra_h:
1325  case Intrinsic::mips_sra_w:
1326  case Intrinsic::mips_sra_d:
1327    return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
1328  case Intrinsic::mips_srai_b:
1329  case Intrinsic::mips_srai_h:
1330  case Intrinsic::mips_srai_w:
1331  case Intrinsic::mips_srai_d:
1332    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
1333                                 lowerMSASplatImm(Op, 2, DAG));
1334  case Intrinsic::mips_srl_b:
1335  case Intrinsic::mips_srl_h:
1336  case Intrinsic::mips_srl_w:
1337  case Intrinsic::mips_srl_d:
1338    return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
1339  case Intrinsic::mips_srli_b:
1340  case Intrinsic::mips_srli_h:
1341  case Intrinsic::mips_srli_w:
1342  case Intrinsic::mips_srli_d:
1343    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
1344                                 lowerMSASplatImm(Op, 2, DAG));
1345  case Intrinsic::mips_subv_b:
1346  case Intrinsic::mips_subv_h:
1347  case Intrinsic::mips_subv_w:
1348  case Intrinsic::mips_subv_d:
1349    return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
1350  case Intrinsic::mips_subvi_b:
1351  case Intrinsic::mips_subvi_h:
1352  case Intrinsic::mips_subvi_w:
1353  case Intrinsic::mips_subvi_d:
1354    return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
1355                                 lowerMSASplatImm(Op, 2, DAG));
1356  case Intrinsic::mips_xor_v:
1357    return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
1358  }
1359}
1360
1361static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1362  SDLoc DL(Op);
1363  SDValue ChainIn = Op->getOperand(0);
1364  SDValue Address = Op->getOperand(2);
1365  SDValue Offset  = Op->getOperand(3);
1366  EVT ResTy = Op->getValueType(0);
1367  EVT PtrTy = Address->getValueType(0);
1368
1369  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1370
1371  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1372                     false, false, 16);
1373}
1374
1375SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1376                                                     SelectionDAG &DAG) const {
1377  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1378  switch (Intr) {
1379  default:
1380    return SDValue();
1381  case Intrinsic::mips_extp:
1382    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1383  case Intrinsic::mips_extpdp:
1384    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1385  case Intrinsic::mips_extr_w:
1386    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1387  case Intrinsic::mips_extr_r_w:
1388    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1389  case Intrinsic::mips_extr_rs_w:
1390    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1391  case Intrinsic::mips_extr_s_h:
1392    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1393  case Intrinsic::mips_mthlip:
1394    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1395  case Intrinsic::mips_mulsaq_s_w_ph:
1396    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1397  case Intrinsic::mips_maq_s_w_phl:
1398    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1399  case Intrinsic::mips_maq_s_w_phr:
1400    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1401  case Intrinsic::mips_maq_sa_w_phl:
1402    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1403  case Intrinsic::mips_maq_sa_w_phr:
1404    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1405  case Intrinsic::mips_dpaq_s_w_ph:
1406    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1407  case Intrinsic::mips_dpsq_s_w_ph:
1408    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1409  case Intrinsic::mips_dpaq_sa_l_w:
1410    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1411  case Intrinsic::mips_dpsq_sa_l_w:
1412    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1413  case Intrinsic::mips_dpaqx_s_w_ph:
1414    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1415  case Intrinsic::mips_dpaqx_sa_w_ph:
1416    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1417  case Intrinsic::mips_dpsqx_s_w_ph:
1418    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1419  case Intrinsic::mips_dpsqx_sa_w_ph:
1420    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1421  case Intrinsic::mips_ld_b:
1422  case Intrinsic::mips_ld_h:
1423  case Intrinsic::mips_ld_w:
1424  case Intrinsic::mips_ld_d:
1425  case Intrinsic::mips_ldx_b:
1426  case Intrinsic::mips_ldx_h:
1427  case Intrinsic::mips_ldx_w:
1428  case Intrinsic::mips_ldx_d:
1429   return lowerMSALoadIntr(Op, DAG, Intr);
1430  }
1431}
1432
1433static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1434  SDLoc DL(Op);
1435  SDValue ChainIn = Op->getOperand(0);
1436  SDValue Value   = Op->getOperand(2);
1437  SDValue Address = Op->getOperand(3);
1438  SDValue Offset  = Op->getOperand(4);
1439  EVT PtrTy = Address->getValueType(0);
1440
1441  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1442
1443  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1444                      false, 16);
1445}
1446
1447SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1448                                                  SelectionDAG &DAG) const {
1449  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1450  switch (Intr) {
1451  default:
1452    return SDValue();
1453  case Intrinsic::mips_st_b:
1454  case Intrinsic::mips_st_h:
1455  case Intrinsic::mips_st_w:
1456  case Intrinsic::mips_st_d:
1457  case Intrinsic::mips_stx_b:
1458  case Intrinsic::mips_stx_h:
1459  case Intrinsic::mips_stx_w:
1460  case Intrinsic::mips_stx_d:
1461    return lowerMSAStoreIntr(Op, DAG, Intr);
1462  }
1463}
1464
1465/// \brief Check if the given BuildVectorSDNode is a splat.
1466/// This method currently relies on DAG nodes being reused when equivalent,
1467/// so it's possible for this to return false even when isConstantSplat returns
1468/// true.
1469static bool isSplatVector(const BuildVectorSDNode *N) {
1470  unsigned int nOps = N->getNumOperands();
1471  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1472
1473  SDValue Operand0 = N->getOperand(0);
1474
1475  for (unsigned int i = 1; i < nOps; ++i) {
1476    if (N->getOperand(i) != Operand0)
1477      return false;
1478  }
1479
1480  return true;
1481}
1482
1483// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1484//
1485// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1486// choose to sign-extend but we could have equally chosen zero-extend. The
1487// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1488// result into this node later (possibly changing it to a zero-extend in the
1489// process).
1490SDValue MipsSETargetLowering::
1491lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1492  SDLoc DL(Op);
1493  EVT ResTy = Op->getValueType(0);
1494  SDValue Op0 = Op->getOperand(0);
1495  SDValue Op1 = Op->getOperand(1);
1496  EVT EltTy = Op0->getValueType(0).getVectorElementType();
1497  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1498                     DAG.getValueType(EltTy));
1499}
1500
1501// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1502// backend.
1503//
1504// Lowers according to the following rules:
1505// - Vectors of 128-bits may be legal subject to the other rules. Other sizes
1506//   are not legal.
1507// - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
1508// - Constant splats with an element size of 32-bits or less are legal and are
1509//   lowered to MipsISD::VSPLAT.
1510// - Constant splats with an element size of 64-bits but whose value would fit
1511//   within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
1512// - All other ISD::BUILD_VECTORS are not legal
1513SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1514                                                SelectionDAG &DAG) const {
1515  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1516  EVT ResTy = Op->getValueType(0);
1517  SDLoc DL(Op);
1518  APInt SplatValue, SplatUndef;
1519  unsigned SplatBitSize;
1520  bool HasAnyUndefs;
1521
1522  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1523    return SDValue();
1524
1525  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1526                            HasAnyUndefs, 8,
1527                            !Subtarget->isLittle())) {
1528    SDValue Result;
1529    EVT TmpVecTy;
1530    EVT ConstTy = MVT::i32;
1531    unsigned SplatOp = MipsISD::VSPLAT;
1532
1533    switch (SplatBitSize) {
1534    default:
1535      return SDValue();
1536    case 64:
1537      TmpVecTy = MVT::v2i64;
1538
1539      // i64 is an illegal type on Mips32, but if it the constant fits into a
1540      // signed 10-bit value then we can still handle it using VSPLATD and an
1541      // i32 constant
1542      if (HasMips64)
1543        ConstTy = MVT::i64;
1544      else if (isInt<10>(SplatValue.getSExtValue())) {
1545        SplatValue = SplatValue.trunc(32);
1546        SplatOp = MipsISD::VSPLATD;
1547      } else
1548        return SDValue();
1549      break;
1550    case 32:
1551      TmpVecTy = MVT::v4i32;
1552      break;
1553    case 16:
1554      TmpVecTy = MVT::v8i16;
1555      SplatValue = SplatValue.sext(32);
1556      break;
1557    case 8:
1558      TmpVecTy = MVT::v16i8;
1559      SplatValue = SplatValue.sext(32);
1560      break;
1561    }
1562
1563    Result = DAG.getNode(SplatOp, DL, TmpVecTy,
1564                         DAG.getConstant(SplatValue, ConstTy));
1565    if (ResTy != Result.getValueType())
1566      Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1567
1568    return Result;
1569  }
1570  else if (isSplatVector(Node))
1571    return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
1572
1573  return SDValue();
1574}
1575
1576MachineBasicBlock * MipsSETargetLowering::
1577emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1578  // $bb:
1579  //  bposge32_pseudo $vr0
1580  //  =>
1581  // $bb:
1582  //  bposge32 $tbb
1583  // $fbb:
1584  //  li $vr2, 0
1585  //  b $sink
1586  // $tbb:
1587  //  li $vr1, 1
1588  // $sink:
1589  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1590
1591  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1592  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1593  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1594  DebugLoc DL = MI->getDebugLoc();
1595  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1596  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1597  MachineFunction *F = BB->getParent();
1598  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1599  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1600  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1601  F->insert(It, FBB);
1602  F->insert(It, TBB);
1603  F->insert(It, Sink);
1604
1605  // Transfer the remainder of BB and its successor edges to Sink.
1606  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1607               BB->end());
1608  Sink->transferSuccessorsAndUpdatePHIs(BB);
1609
1610  // Add successors.
1611  BB->addSuccessor(FBB);
1612  BB->addSuccessor(TBB);
1613  FBB->addSuccessor(Sink);
1614  TBB->addSuccessor(Sink);
1615
1616  // Insert the real bposge32 instruction to $BB.
1617  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1618
1619  // Fill $FBB.
1620  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1621  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1622    .addReg(Mips::ZERO).addImm(0);
1623  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1624
1625  // Fill $TBB.
1626  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1627  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1628    .addReg(Mips::ZERO).addImm(1);
1629
1630  // Insert phi function to $Sink.
1631  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1632          MI->getOperand(0).getReg())
1633    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1634
1635  MI->eraseFromParent();   // The pseudo instruction is gone now.
1636  return Sink;
1637}
1638
1639MachineBasicBlock * MipsSETargetLowering::
1640emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1641                     unsigned BranchOp) const{
1642  // $bb:
1643  //  vany_nonzero $rd, $ws
1644  //  =>
1645  // $bb:
1646  //  bnz.b $ws, $tbb
1647  //  b $fbb
1648  // $fbb:
1649  //  li $rd1, 0
1650  //  b $sink
1651  // $tbb:
1652  //  li $rd2, 1
1653  // $sink:
1654  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1655
1656  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1657  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1658  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1659  DebugLoc DL = MI->getDebugLoc();
1660  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1661  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1662  MachineFunction *F = BB->getParent();
1663  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1664  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1665  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1666  F->insert(It, FBB);
1667  F->insert(It, TBB);
1668  F->insert(It, Sink);
1669
1670  // Transfer the remainder of BB and its successor edges to Sink.
1671  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1672               BB->end());
1673  Sink->transferSuccessorsAndUpdatePHIs(BB);
1674
1675  // Add successors.
1676  BB->addSuccessor(FBB);
1677  BB->addSuccessor(TBB);
1678  FBB->addSuccessor(Sink);
1679  TBB->addSuccessor(Sink);
1680
1681  // Insert the real bnz.b instruction to $BB.
1682  BuildMI(BB, DL, TII->get(BranchOp))
1683    .addReg(MI->getOperand(1).getReg())
1684    .addMBB(TBB);
1685
1686  // Fill $FBB.
1687  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1688  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1689    .addReg(Mips::ZERO).addImm(0);
1690  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1691
1692  // Fill $TBB.
1693  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1694  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1695    .addReg(Mips::ZERO).addImm(1);
1696
1697  // Insert phi function to $Sink.
1698  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1699          MI->getOperand(0).getReg())
1700    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1701
1702  MI->eraseFromParent();   // The pseudo instruction is gone now.
1703  return Sink;
1704}
1705