MipsSEISelLowering.cpp revision 4d835f1cbe5d8c5f6cea4040bea9b180927a1c05
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips32/64. 11// 12//===----------------------------------------------------------------------===// 13#include "MipsSEISelLowering.h" 14#include "MipsRegisterInfo.h" 15#include "MipsTargetMachine.h" 16#include "llvm/CodeGen/MachineInstrBuilder.h" 17#include "llvm/CodeGen/MachineRegisterInfo.h" 18#include "llvm/IR/Intrinsics.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22using namespace llvm; 23 24static cl::opt<bool> 25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 26 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 27 28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 29 cl::desc("Expand double precision loads and " 30 "stores to their single precision " 31 "counterparts")); 32 33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) 34 : MipsTargetLowering(TM) { 35 // Set up the register classes 36 37 clearRegisterClasses(); 38 39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 40 41 if (HasMips64) 42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 43 44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) { 45 // Expand all truncating stores and extending loads. 46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 48 49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { 50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) 51 setTruncStoreAction((MVT::SimpleValueType)VT0, 52 (MVT::SimpleValueType)VT1, Expand); 53 54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); 57 } 58 } 59 60 if (Subtarget->hasDSP()) { 61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 62 63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 65 66 // Expand all builtin opcodes. 67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 68 setOperationAction(Opc, VecTys[i], Expand); 69 70 setOperationAction(ISD::ADD, VecTys[i], Legal); 71 setOperationAction(ISD::SUB, VecTys[i], Legal); 72 setOperationAction(ISD::LOAD, VecTys[i], Legal); 73 setOperationAction(ISD::STORE, VecTys[i], Legal); 74 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 75 } 76 77 setTargetDAGCombine(ISD::SHL); 78 setTargetDAGCombine(ISD::SRA); 79 setTargetDAGCombine(ISD::SRL); 80 setTargetDAGCombine(ISD::SETCC); 81 setTargetDAGCombine(ISD::VSELECT); 82 } 83 84 if (Subtarget->hasDSPR2()) 85 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 86 87 if (Subtarget->hasMSA()) { 88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 95 96 setTargetDAGCombine(ISD::AND); 97 setTargetDAGCombine(ISD::SRA); 98 setTargetDAGCombine(ISD::VSELECT); 99 setTargetDAGCombine(ISD::XOR); 100 } 101 102 if (!Subtarget->mipsSEUsesSoftFloat()) { 103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 104 105 // When dealing with single precision only, use libcalls 106 if (!Subtarget->isSingleFloat()) { 107 if (Subtarget->isFP64bit()) 108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 109 else 110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 111 } 112 } 113 114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 116 setOperationAction(ISD::MULHS, MVT::i32, Custom); 117 setOperationAction(ISD::MULHU, MVT::i32, Custom); 118 119 if (HasMips64) { 120 setOperationAction(ISD::MULHS, MVT::i64, Custom); 121 setOperationAction(ISD::MULHU, MVT::i64, Custom); 122 setOperationAction(ISD::MUL, MVT::i64, Custom); 123 } 124 125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 126 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 127 128 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 129 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 131 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 132 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 133 setOperationAction(ISD::LOAD, MVT::i32, Custom); 134 setOperationAction(ISD::STORE, MVT::i32, Custom); 135 136 setTargetDAGCombine(ISD::ADDE); 137 setTargetDAGCombine(ISD::SUBE); 138 setTargetDAGCombine(ISD::MUL); 139 140 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 141 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 142 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 143 144 if (NoDPLoadStore) { 145 setOperationAction(ISD::LOAD, MVT::f64, Custom); 146 setOperationAction(ISD::STORE, MVT::f64, Custom); 147 } 148 149 computeRegisterProperties(); 150} 151 152const MipsTargetLowering * 153llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { 154 return new MipsSETargetLowering(TM); 155} 156 157// Enable MSA support for the given integer type and Register class. 158void MipsSETargetLowering:: 159addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 160 addRegisterClass(Ty, RC); 161 162 // Expand all builtin opcodes. 163 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 164 setOperationAction(Opc, Ty, Expand); 165 166 setOperationAction(ISD::BITCAST, Ty, Legal); 167 setOperationAction(ISD::LOAD, Ty, Legal); 168 setOperationAction(ISD::STORE, Ty, Legal); 169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 170 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 171 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 172 173 setOperationAction(ISD::ADD, Ty, Legal); 174 setOperationAction(ISD::AND, Ty, Legal); 175 setOperationAction(ISD::CTLZ, Ty, Legal); 176 setOperationAction(ISD::CTPOP, Ty, Legal); 177 setOperationAction(ISD::MUL, Ty, Legal); 178 setOperationAction(ISD::OR, Ty, Legal); 179 setOperationAction(ISD::SDIV, Ty, Legal); 180 setOperationAction(ISD::SHL, Ty, Legal); 181 setOperationAction(ISD::SRA, Ty, Legal); 182 setOperationAction(ISD::SRL, Ty, Legal); 183 setOperationAction(ISD::SUB, Ty, Legal); 184 setOperationAction(ISD::UDIV, Ty, Legal); 185 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 186 setOperationAction(ISD::VSELECT, Ty, Legal); 187 setOperationAction(ISD::XOR, Ty, Legal); 188 189 setOperationAction(ISD::SETCC, Ty, Legal); 190 setCondCodeAction(ISD::SETNE, Ty, Expand); 191 setCondCodeAction(ISD::SETGE, Ty, Expand); 192 setCondCodeAction(ISD::SETGT, Ty, Expand); 193 setCondCodeAction(ISD::SETUGE, Ty, Expand); 194 setCondCodeAction(ISD::SETUGT, Ty, Expand); 195} 196 197// Enable MSA support for the given floating-point type and Register class. 198void MipsSETargetLowering:: 199addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 200 addRegisterClass(Ty, RC); 201 202 // Expand all builtin opcodes. 203 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 204 setOperationAction(Opc, Ty, Expand); 205 206 setOperationAction(ISD::LOAD, Ty, Legal); 207 setOperationAction(ISD::STORE, Ty, Legal); 208 setOperationAction(ISD::BITCAST, Ty, Legal); 209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 210 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 211 212 if (Ty != MVT::v8f16) { 213 setOperationAction(ISD::FABS, Ty, Legal); 214 setOperationAction(ISD::FADD, Ty, Legal); 215 setOperationAction(ISD::FDIV, Ty, Legal); 216 setOperationAction(ISD::FLOG2, Ty, Legal); 217 setOperationAction(ISD::FMUL, Ty, Legal); 218 setOperationAction(ISD::FRINT, Ty, Legal); 219 setOperationAction(ISD::FSQRT, Ty, Legal); 220 setOperationAction(ISD::FSUB, Ty, Legal); 221 setOperationAction(ISD::VSELECT, Ty, Legal); 222 223 setOperationAction(ISD::SETCC, Ty, Legal); 224 setCondCodeAction(ISD::SETOGE, Ty, Expand); 225 setCondCodeAction(ISD::SETOGT, Ty, Expand); 226 setCondCodeAction(ISD::SETUGE, Ty, Expand); 227 setCondCodeAction(ISD::SETUGT, Ty, Expand); 228 setCondCodeAction(ISD::SETGE, Ty, Expand); 229 setCondCodeAction(ISD::SETGT, Ty, Expand); 230 } 231} 232 233bool 234MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 235 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 236 237 switch (SVT) { 238 case MVT::i64: 239 case MVT::i32: 240 if (Fast) 241 *Fast = true; 242 return true; 243 default: 244 return false; 245 } 246} 247 248SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 249 SelectionDAG &DAG) const { 250 switch(Op.getOpcode()) { 251 case ISD::LOAD: return lowerLOAD(Op, DAG); 252 case ISD::STORE: return lowerSTORE(Op, DAG); 253 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 254 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 255 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 256 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 257 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 258 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 259 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 260 DAG); 261 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 262 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 263 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 264 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 265 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 266 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 267 } 268 269 return MipsTargetLowering::LowerOperation(Op, DAG); 270} 271 272// selectMADD - 273// Transforms a subgraph in CurDAG if the following pattern is found: 274// (addc multLo, Lo0), (adde multHi, Hi0), 275// where, 276// multHi/Lo: product of multiplication 277// Lo0: initial value of Lo register 278// Hi0: initial value of Hi register 279// Return true if pattern matching was successful. 280static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 281 // ADDENode's second operand must be a flag output of an ADDC node in order 282 // for the matching to be successful. 283 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 284 285 if (ADDCNode->getOpcode() != ISD::ADDC) 286 return false; 287 288 SDValue MultHi = ADDENode->getOperand(0); 289 SDValue MultLo = ADDCNode->getOperand(0); 290 SDNode *MultNode = MultHi.getNode(); 291 unsigned MultOpc = MultHi.getOpcode(); 292 293 // MultHi and MultLo must be generated by the same node, 294 if (MultLo.getNode() != MultNode) 295 return false; 296 297 // and it must be a multiplication. 298 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 299 return false; 300 301 // MultLo amd MultHi must be the first and second output of MultNode 302 // respectively. 303 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 304 return false; 305 306 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 307 // of the values of MultNode, in which case MultNode will be removed in later 308 // phases. 309 // If there exist users other than ADDENode or ADDCNode, this function returns 310 // here, which will result in MultNode being mapped to a single MULT 311 // instruction node rather than a pair of MULT and MADD instructions being 312 // produced. 313 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 314 return false; 315 316 SDLoc DL(ADDENode); 317 318 // Initialize accumulator. 319 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, 320 ADDCNode->getOperand(1), 321 ADDENode->getOperand(1)); 322 323 // create MipsMAdd(u) node 324 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 325 326 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 327 MultNode->getOperand(0),// Factor 0 328 MultNode->getOperand(1),// Factor 1 329 ACCIn); 330 331 // replace uses of adde and addc here 332 if (!SDValue(ADDCNode, 0).use_empty()) { 333 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32); 334 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd, 335 LoIdx); 336 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 337 } 338 if (!SDValue(ADDENode, 0).use_empty()) { 339 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32); 340 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd, 341 HiIdx); 342 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 343 } 344 345 return true; 346} 347 348// selectMSUB - 349// Transforms a subgraph in CurDAG if the following pattern is found: 350// (addc Lo0, multLo), (sube Hi0, multHi), 351// where, 352// multHi/Lo: product of multiplication 353// Lo0: initial value of Lo register 354// Hi0: initial value of Hi register 355// Return true if pattern matching was successful. 356static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 357 // SUBENode's second operand must be a flag output of an SUBC node in order 358 // for the matching to be successful. 359 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 360 361 if (SUBCNode->getOpcode() != ISD::SUBC) 362 return false; 363 364 SDValue MultHi = SUBENode->getOperand(1); 365 SDValue MultLo = SUBCNode->getOperand(1); 366 SDNode *MultNode = MultHi.getNode(); 367 unsigned MultOpc = MultHi.getOpcode(); 368 369 // MultHi and MultLo must be generated by the same node, 370 if (MultLo.getNode() != MultNode) 371 return false; 372 373 // and it must be a multiplication. 374 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 375 return false; 376 377 // MultLo amd MultHi must be the first and second output of MultNode 378 // respectively. 379 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 380 return false; 381 382 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 383 // of the values of MultNode, in which case MultNode will be removed in later 384 // phases. 385 // If there exist users other than SUBENode or SUBCNode, this function returns 386 // here, which will result in MultNode being mapped to a single MULT 387 // instruction node rather than a pair of MULT and MSUB instructions being 388 // produced. 389 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 390 return false; 391 392 SDLoc DL(SUBENode); 393 394 // Initialize accumulator. 395 SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, 396 SUBCNode->getOperand(0), 397 SUBENode->getOperand(0)); 398 399 // create MipsSub(u) node 400 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 401 402 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 403 MultNode->getOperand(0),// Factor 0 404 MultNode->getOperand(1),// Factor 1 405 ACCIn); 406 407 // replace uses of sube and subc here 408 if (!SDValue(SUBCNode, 0).use_empty()) { 409 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32); 410 SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub, 411 LoIdx); 412 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 413 } 414 if (!SDValue(SUBENode, 0).use_empty()) { 415 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32); 416 SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub, 417 HiIdx); 418 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 419 } 420 421 return true; 422} 423 424static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 425 TargetLowering::DAGCombinerInfo &DCI, 426 const MipsSubtarget *Subtarget) { 427 if (DCI.isBeforeLegalize()) 428 return SDValue(); 429 430 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 431 selectMADD(N, &DAG)) 432 return SDValue(N, 0); 433 434 return SDValue(); 435} 436 437// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 438// 439// Performs the following transformations: 440// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 441// sign/zero-extension is completely overwritten by the new one performed by 442// the ISD::AND. 443// - Removes redundant zero extensions performed by an ISD::AND. 444static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 445 TargetLowering::DAGCombinerInfo &DCI, 446 const MipsSubtarget *Subtarget) { 447 if (!Subtarget->hasMSA()) 448 return SDValue(); 449 450 SDValue Op0 = N->getOperand(0); 451 SDValue Op1 = N->getOperand(1); 452 unsigned Op0Opcode = Op0->getOpcode(); 453 454 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 455 // where $d + 1 == 2^n and n == 32 456 // or $d + 1 == 2^n and n <= 32 and ZExt 457 // -> (MipsVExtractZExt $a, $b, $c) 458 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 459 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 460 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 461 462 if (!Mask) 463 return SDValue(); 464 465 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 466 467 if (Log2IfPositive <= 0) 468 return SDValue(); // Mask+1 is not a power of 2 469 470 SDValue Op0Op2 = Op0->getOperand(2); 471 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 472 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 473 unsigned Log2 = Log2IfPositive; 474 475 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 476 Log2 == ExtendTySize) { 477 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 478 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 479 Op0->getVTList(), Ops, Op0->getNumOperands()); 480 return Op0; 481 } 482 } 483 484 return SDValue(); 485} 486 487static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 488 TargetLowering::DAGCombinerInfo &DCI, 489 const MipsSubtarget *Subtarget) { 490 if (DCI.isBeforeLegalize()) 491 return SDValue(); 492 493 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 494 selectMSUB(N, &DAG)) 495 return SDValue(N, 0); 496 497 return SDValue(); 498} 499 500static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 501 EVT ShiftTy, SelectionDAG &DAG) { 502 // Clear the upper (64 - VT.sizeInBits) bits. 503 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 504 505 // Return 0. 506 if (C == 0) 507 return DAG.getConstant(0, VT); 508 509 // Return x. 510 if (C == 1) 511 return X; 512 513 // If c is power of 2, return (shl x, log2(c)). 514 if (isPowerOf2_64(C)) 515 return DAG.getNode(ISD::SHL, DL, VT, X, 516 DAG.getConstant(Log2_64(C), ShiftTy)); 517 518 unsigned Log2Ceil = Log2_64_Ceil(C); 519 uint64_t Floor = 1LL << Log2_64(C); 520 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 521 522 // If |c - floor_c| <= |c - ceil_c|, 523 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 524 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 525 if (C - Floor <= Ceil - C) { 526 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 527 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 528 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 529 } 530 531 // If |c - floor_c| > |c - ceil_c|, 532 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 533 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 534 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 535 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 536} 537 538static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 539 const TargetLowering::DAGCombinerInfo &DCI, 540 const MipsSETargetLowering *TL) { 541 EVT VT = N->getValueType(0); 542 543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 544 if (!VT.isVector()) 545 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 546 VT, TL->getScalarShiftAmountTy(VT), DAG); 547 548 return SDValue(N, 0); 549} 550 551static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 552 SelectionDAG &DAG, 553 const MipsSubtarget *Subtarget) { 554 // See if this is a vector splat immediate node. 555 APInt SplatValue, SplatUndef; 556 unsigned SplatBitSize; 557 bool HasAnyUndefs; 558 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 559 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 560 561 if (!BV || 562 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 563 EltSize, !Subtarget->isLittle()) || 564 (SplatBitSize != EltSize) || 565 (SplatValue.getZExtValue() >= EltSize)) 566 return SDValue(); 567 568 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 569 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 570} 571 572static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 573 TargetLowering::DAGCombinerInfo &DCI, 574 const MipsSubtarget *Subtarget) { 575 EVT Ty = N->getValueType(0); 576 577 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 578 return SDValue(); 579 580 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 581} 582 583// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 584// constant splats into MipsISD::SHRA_DSP for DSPr2. 585// 586// Performs the following transformations: 587// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 588// sign/zero-extension is completely overwritten by the new one performed by 589// the ISD::SRA and ISD::SHL nodes. 590// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 591// sequence. 592// 593// See performDSPShiftCombine for more information about the transformation 594// used for DSPr2. 595static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 596 TargetLowering::DAGCombinerInfo &DCI, 597 const MipsSubtarget *Subtarget) { 598 EVT Ty = N->getValueType(0); 599 600 if (Subtarget->hasMSA()) { 601 SDValue Op0 = N->getOperand(0); 602 SDValue Op1 = N->getOperand(1); 603 604 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 605 // where $d + sizeof($c) == 32 606 // or $d + sizeof($c) <= 32 and SExt 607 // -> (MipsVExtractSExt $a, $b, $c) 608 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 609 SDValue Op0Op0 = Op0->getOperand(0); 610 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 611 612 if (!ShAmount) 613 return SDValue(); 614 615 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 616 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 617 return SDValue(); 618 619 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 620 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 621 622 if (TotalBits == 32 || 623 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 624 TotalBits <= 32)) { 625 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 626 Op0Op0->getOperand(2) }; 627 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, 628 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands()); 629 return Op0Op0; 630 } 631 } 632 } 633 634 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) 635 return SDValue(); 636 637 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 638} 639 640 641static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 642 TargetLowering::DAGCombinerInfo &DCI, 643 const MipsSubtarget *Subtarget) { 644 EVT Ty = N->getValueType(0); 645 646 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) 647 return SDValue(); 648 649 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 650} 651 652static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 653 bool IsV216 = (Ty == MVT::v2i16); 654 655 switch (CC) { 656 case ISD::SETEQ: 657 case ISD::SETNE: return true; 658 case ISD::SETLT: 659 case ISD::SETLE: 660 case ISD::SETGT: 661 case ISD::SETGE: return IsV216; 662 case ISD::SETULT: 663 case ISD::SETULE: 664 case ISD::SETUGT: 665 case ISD::SETUGE: return !IsV216; 666 default: return false; 667 } 668} 669 670static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 671 EVT Ty = N->getValueType(0); 672 673 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 674 return SDValue(); 675 676 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 677 return SDValue(); 678 679 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 680 N->getOperand(1), N->getOperand(2)); 681} 682 683static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 684 EVT Ty = N->getValueType(0); 685 686 if (Ty.is128BitVector() && Ty.isInteger()) { 687 // Try the following combines: 688 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 689 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 690 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 691 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 692 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 693 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 694 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 695 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 696 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 697 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 698 // legalizer. 699 SDValue Op0 = N->getOperand(0); 700 701 if (Op0->getOpcode() != ISD::SETCC) 702 return SDValue(); 703 704 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 705 bool Signed; 706 707 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 708 Signed = true; 709 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 710 Signed = false; 711 else 712 return SDValue(); 713 714 SDValue Op1 = N->getOperand(1); 715 SDValue Op2 = N->getOperand(2); 716 SDValue Op0Op0 = Op0->getOperand(0); 717 SDValue Op0Op1 = Op0->getOperand(1); 718 719 if (Op1 == Op0Op0 && Op2 == Op0Op1) 720 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 721 Ty, Op1, Op2); 722 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 723 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 724 Ty, Op1, Op2); 725 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 726 SDValue SetCC = N->getOperand(0); 727 728 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 729 return SDValue(); 730 731 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 732 SetCC.getOperand(0), SetCC.getOperand(1), 733 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 734 } 735 736 return SDValue(); 737} 738 739static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 740 const MipsSubtarget *Subtarget) { 741 EVT Ty = N->getValueType(0); 742 743 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 744 // Try the following combines: 745 // (xor (or $a, $b), (build_vector allones)) 746 // (xor (or $a, $b), (bitcast (build_vector allones))) 747 SDValue Op0 = N->getOperand(0); 748 SDValue Op1 = N->getOperand(1); 749 SDValue NotOp; 750 751 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 752 NotOp = Op1; 753 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 754 NotOp = Op0; 755 else 756 return SDValue(); 757 758 if (NotOp->getOpcode() == ISD::OR) 759 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 760 NotOp->getOperand(1)); 761 } 762 763 return SDValue(); 764} 765 766SDValue 767MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 768 SelectionDAG &DAG = DCI.DAG; 769 SDValue Val; 770 771 switch (N->getOpcode()) { 772 case ISD::ADDE: 773 return performADDECombine(N, DAG, DCI, Subtarget); 774 case ISD::AND: 775 Val = performANDCombine(N, DAG, DCI, Subtarget); 776 break; 777 case ISD::SUBE: 778 return performSUBECombine(N, DAG, DCI, Subtarget); 779 case ISD::MUL: 780 return performMULCombine(N, DAG, DCI, this); 781 case ISD::SHL: 782 return performSHLCombine(N, DAG, DCI, Subtarget); 783 case ISD::SRA: 784 return performSRACombine(N, DAG, DCI, Subtarget); 785 case ISD::SRL: 786 return performSRLCombine(N, DAG, DCI, Subtarget); 787 case ISD::VSELECT: 788 return performVSELECTCombine(N, DAG); 789 case ISD::XOR: 790 Val = performXORCombine(N, DAG, Subtarget); 791 break; 792 case ISD::SETCC: 793 Val = performSETCCCombine(N, DAG); 794 break; 795 } 796 797 if (Val.getNode()) 798 return Val; 799 800 return MipsTargetLowering::PerformDAGCombine(N, DCI); 801} 802 803MachineBasicBlock * 804MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 805 MachineBasicBlock *BB) const { 806 switch (MI->getOpcode()) { 807 default: 808 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 809 case Mips::BPOSGE32_PSEUDO: 810 return emitBPOSGE32(MI, BB); 811 case Mips::SNZ_B_PSEUDO: 812 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 813 case Mips::SNZ_H_PSEUDO: 814 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 815 case Mips::SNZ_W_PSEUDO: 816 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 817 case Mips::SNZ_D_PSEUDO: 818 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 819 case Mips::SNZ_V_PSEUDO: 820 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 821 case Mips::SZ_B_PSEUDO: 822 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 823 case Mips::SZ_H_PSEUDO: 824 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 825 case Mips::SZ_W_PSEUDO: 826 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 827 case Mips::SZ_D_PSEUDO: 828 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 829 case Mips::SZ_V_PSEUDO: 830 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 831 case Mips::COPY_FW_PSEUDO: 832 return emitCOPY_FW(MI, BB); 833 case Mips::COPY_FD_PSEUDO: 834 return emitCOPY_FD(MI, BB); 835 case Mips::INSERT_FW_PSEUDO: 836 return emitINSERT_FW(MI, BB); 837 case Mips::INSERT_FD_PSEUDO: 838 return emitINSERT_FD(MI, BB); 839 } 840} 841 842bool MipsSETargetLowering:: 843isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 844 unsigned NextStackOffset, 845 const MipsFunctionInfo& FI) const { 846 if (!EnableMipsTailCalls) 847 return false; 848 849 // Return false if either the callee or caller has a byval argument. 850 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 851 return false; 852 853 // Return true if the callee's argument area is no larger than the 854 // caller's. 855 return NextStackOffset <= FI.getIncomingArgSize(); 856} 857 858void MipsSETargetLowering:: 859getOpndList(SmallVectorImpl<SDValue> &Ops, 860 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 861 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 862 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 863 // T9 should contain the address of the callee function if 864 // -reloction-model=pic or it is an indirect call. 865 if (IsPICCall || !GlobalOrExternal) { 866 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 867 RegsToPass.push_front(std::make_pair(T9Reg, Callee)); 868 } else 869 Ops.push_back(Callee); 870 871 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 872 InternalLinkage, CLI, Callee, Chain); 873} 874 875SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 876 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 877 878 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 879 return MipsTargetLowering::lowerLOAD(Op, DAG); 880 881 // Replace a double precision load with two i32 loads and a buildpair64. 882 SDLoc DL(Op); 883 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 884 EVT PtrVT = Ptr.getValueType(); 885 886 // i32 load from lower address. 887 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 888 MachinePointerInfo(), Nd.isVolatile(), 889 Nd.isNonTemporal(), Nd.isInvariant(), 890 Nd.getAlignment()); 891 892 // i32 load from higher address. 893 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 894 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 895 MachinePointerInfo(), Nd.isVolatile(), 896 Nd.isNonTemporal(), Nd.isInvariant(), 897 std::min(Nd.getAlignment(), 4U)); 898 899 if (!Subtarget->isLittle()) 900 std::swap(Lo, Hi); 901 902 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 903 SDValue Ops[2] = {BP, Hi.getValue(1)}; 904 return DAG.getMergeValues(Ops, 2, DL); 905} 906 907SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 908 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 909 910 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 911 return MipsTargetLowering::lowerSTORE(Op, DAG); 912 913 // Replace a double precision store with two extractelement64s and i32 stores. 914 SDLoc DL(Op); 915 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 916 EVT PtrVT = Ptr.getValueType(); 917 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 918 Val, DAG.getConstant(0, MVT::i32)); 919 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 920 Val, DAG.getConstant(1, MVT::i32)); 921 922 if (!Subtarget->isLittle()) 923 std::swap(Lo, Hi); 924 925 // i32 store to lower address. 926 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 927 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 928 Nd.getTBAAInfo()); 929 930 // i32 store to higher address. 931 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 932 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 933 Nd.isVolatile(), Nd.isNonTemporal(), 934 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); 935} 936 937SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 938 bool HasLo, bool HasHi, 939 SelectionDAG &DAG) const { 940 EVT Ty = Op.getOperand(0).getValueType(); 941 SDLoc DL(Op); 942 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 943 Op.getOperand(0), Op.getOperand(1)); 944 SDValue Lo, Hi; 945 946 if (HasLo) 947 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult, 948 DAG.getConstant(Mips::sub_lo, MVT::i32)); 949 if (HasHi) 950 Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult, 951 DAG.getConstant(Mips::sub_hi, MVT::i32)); 952 953 if (!HasLo || !HasHi) 954 return HasLo ? Lo : Hi; 955 956 SDValue Vals[] = { Lo, Hi }; 957 return DAG.getMergeValues(Vals, 2, DL); 958} 959 960 961static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 962 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 963 DAG.getConstant(0, MVT::i32)); 964 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 965 DAG.getConstant(1, MVT::i32)); 966 return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi); 967} 968 969static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 970 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op, 971 DAG.getConstant(Mips::sub_lo, MVT::i32)); 972 SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op, 973 DAG.getConstant(Mips::sub_hi, MVT::i32)); 974 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 975} 976 977// This function expands mips intrinsic nodes which have 64-bit input operands 978// or output values. 979// 980// out64 = intrinsic-node in64 981// => 982// lo = copy (extract-element (in64, 0)) 983// hi = copy (extract-element (in64, 1)) 984// mips-specific-node 985// v0 = copy lo 986// v1 = copy hi 987// out64 = merge-values (v0, v1) 988// 989static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 990 SDLoc DL(Op); 991 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 992 SmallVector<SDValue, 3> Ops; 993 unsigned OpNo = 0; 994 995 // See if Op has a chain input. 996 if (HasChainIn) 997 Ops.push_back(Op->getOperand(OpNo++)); 998 999 // The next operand is the intrinsic opcode. 1000 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1001 1002 // See if the next operand has type i64. 1003 SDValue Opnd = Op->getOperand(++OpNo), In64; 1004 1005 if (Opnd.getValueType() == MVT::i64) 1006 In64 = initAccumulator(Opnd, DL, DAG); 1007 else 1008 Ops.push_back(Opnd); 1009 1010 // Push the remaining operands. 1011 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1012 Ops.push_back(Op->getOperand(OpNo)); 1013 1014 // Add In64 to the end of the list. 1015 if (In64.getNode()) 1016 Ops.push_back(In64); 1017 1018 // Scan output. 1019 SmallVector<EVT, 2> ResTys; 1020 1021 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1022 I != E; ++I) 1023 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1024 1025 // Create node. 1026 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); 1027 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1028 1029 if (!HasChainIn) 1030 return Out; 1031 1032 assert(Val->getValueType(1) == MVT::Other); 1033 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1034 return DAG.getMergeValues(Vals, 2, DL); 1035} 1036 1037// Lower an MSA copy intrinsic into the specified SelectionDAG node 1038static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1039 SDLoc DL(Op); 1040 SDValue Vec = Op->getOperand(1); 1041 SDValue Idx = Op->getOperand(2); 1042 EVT ResTy = Op->getValueType(0); 1043 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1044 1045 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1046 DAG.getValueType(EltTy)); 1047 1048 return Result; 1049} 1050 1051static SDValue 1052lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) { 1053 EVT ViaVecTy = ResTy; 1054 SmallVector<SDValue, 16> Ops; 1055 SDValue ImmHiOp; 1056 1057 if (ViaVecTy == MVT::v2i64) { 1058 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp, 1059 DAG.getConstant(31, MVT::i32)); 1060 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) { 1061 Ops.push_back(ImmHiOp); 1062 Ops.push_back(ImmOp); 1063 } 1064 ViaVecTy = MVT::v4i32; 1065 } else { 1066 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1067 Ops.push_back(ImmOp); 1068 } 1069 1070 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0], 1071 Ops.size()); 1072 1073 if (ResTy != ViaVecTy) 1074 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result); 1075 1076 return Result; 1077} 1078 1079static SDValue 1080lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1081 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0), 1082 Op->getOperand(ImmOp), DAG); 1083} 1084 1085SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1086 SelectionDAG &DAG) const { 1087 SDLoc DL(Op); 1088 1089 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1090 default: 1091 return SDValue(); 1092 case Intrinsic::mips_shilo: 1093 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1094 case Intrinsic::mips_dpau_h_qbl: 1095 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1096 case Intrinsic::mips_dpau_h_qbr: 1097 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1098 case Intrinsic::mips_dpsu_h_qbl: 1099 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1100 case Intrinsic::mips_dpsu_h_qbr: 1101 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1102 case Intrinsic::mips_dpa_w_ph: 1103 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1104 case Intrinsic::mips_dps_w_ph: 1105 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1106 case Intrinsic::mips_dpax_w_ph: 1107 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1108 case Intrinsic::mips_dpsx_w_ph: 1109 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1110 case Intrinsic::mips_mulsa_w_ph: 1111 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1112 case Intrinsic::mips_mult: 1113 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1114 case Intrinsic::mips_multu: 1115 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1116 case Intrinsic::mips_madd: 1117 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1118 case Intrinsic::mips_maddu: 1119 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1120 case Intrinsic::mips_msub: 1121 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1122 case Intrinsic::mips_msubu: 1123 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1124 case Intrinsic::mips_addv_b: 1125 case Intrinsic::mips_addv_h: 1126 case Intrinsic::mips_addv_w: 1127 case Intrinsic::mips_addv_d: 1128 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1129 Op->getOperand(2)); 1130 case Intrinsic::mips_addvi_b: 1131 case Intrinsic::mips_addvi_h: 1132 case Intrinsic::mips_addvi_w: 1133 case Intrinsic::mips_addvi_d: 1134 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1135 lowerMSASplatImm(Op, 2, DAG)); 1136 case Intrinsic::mips_and_v: 1137 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1138 Op->getOperand(2)); 1139 case Intrinsic::mips_andi_b: 1140 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1141 lowerMSASplatImm(Op, 2, DAG)); 1142 case Intrinsic::mips_bnz_b: 1143 case Intrinsic::mips_bnz_h: 1144 case Intrinsic::mips_bnz_w: 1145 case Intrinsic::mips_bnz_d: 1146 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1147 Op->getOperand(1)); 1148 case Intrinsic::mips_bnz_v: 1149 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1150 Op->getOperand(1)); 1151 case Intrinsic::mips_bsel_v: 1152 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1153 Op->getOperand(1), Op->getOperand(2), 1154 Op->getOperand(3)); 1155 case Intrinsic::mips_bseli_b: 1156 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1157 Op->getOperand(1), Op->getOperand(2), 1158 lowerMSASplatImm(Op, 3, DAG)); 1159 case Intrinsic::mips_bz_b: 1160 case Intrinsic::mips_bz_h: 1161 case Intrinsic::mips_bz_w: 1162 case Intrinsic::mips_bz_d: 1163 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1164 Op->getOperand(1)); 1165 case Intrinsic::mips_bz_v: 1166 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1167 Op->getOperand(1)); 1168 case Intrinsic::mips_ceq_b: 1169 case Intrinsic::mips_ceq_h: 1170 case Intrinsic::mips_ceq_w: 1171 case Intrinsic::mips_ceq_d: 1172 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1173 Op->getOperand(2), ISD::SETEQ); 1174 case Intrinsic::mips_ceqi_b: 1175 case Intrinsic::mips_ceqi_h: 1176 case Intrinsic::mips_ceqi_w: 1177 case Intrinsic::mips_ceqi_d: 1178 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1179 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1180 case Intrinsic::mips_cle_s_b: 1181 case Intrinsic::mips_cle_s_h: 1182 case Intrinsic::mips_cle_s_w: 1183 case Intrinsic::mips_cle_s_d: 1184 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1185 Op->getOperand(2), ISD::SETLE); 1186 case Intrinsic::mips_clei_s_b: 1187 case Intrinsic::mips_clei_s_h: 1188 case Intrinsic::mips_clei_s_w: 1189 case Intrinsic::mips_clei_s_d: 1190 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1191 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1192 case Intrinsic::mips_cle_u_b: 1193 case Intrinsic::mips_cle_u_h: 1194 case Intrinsic::mips_cle_u_w: 1195 case Intrinsic::mips_cle_u_d: 1196 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1197 Op->getOperand(2), ISD::SETULE); 1198 case Intrinsic::mips_clei_u_b: 1199 case Intrinsic::mips_clei_u_h: 1200 case Intrinsic::mips_clei_u_w: 1201 case Intrinsic::mips_clei_u_d: 1202 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1203 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1204 case Intrinsic::mips_clt_s_b: 1205 case Intrinsic::mips_clt_s_h: 1206 case Intrinsic::mips_clt_s_w: 1207 case Intrinsic::mips_clt_s_d: 1208 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1209 Op->getOperand(2), ISD::SETLT); 1210 case Intrinsic::mips_clti_s_b: 1211 case Intrinsic::mips_clti_s_h: 1212 case Intrinsic::mips_clti_s_w: 1213 case Intrinsic::mips_clti_s_d: 1214 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1215 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1216 case Intrinsic::mips_clt_u_b: 1217 case Intrinsic::mips_clt_u_h: 1218 case Intrinsic::mips_clt_u_w: 1219 case Intrinsic::mips_clt_u_d: 1220 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1221 Op->getOperand(2), ISD::SETULT); 1222 case Intrinsic::mips_clti_u_b: 1223 case Intrinsic::mips_clti_u_h: 1224 case Intrinsic::mips_clti_u_w: 1225 case Intrinsic::mips_clti_u_d: 1226 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1227 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1228 case Intrinsic::mips_copy_s_b: 1229 case Intrinsic::mips_copy_s_h: 1230 case Intrinsic::mips_copy_s_w: 1231 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1232 case Intrinsic::mips_copy_s_d: 1233 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal. 1234 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1235 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1237 Op->getOperand(1), Op->getOperand(2)); 1238 case Intrinsic::mips_copy_u_b: 1239 case Intrinsic::mips_copy_u_h: 1240 case Intrinsic::mips_copy_u_w: 1241 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1242 case Intrinsic::mips_copy_u_d: 1243 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal. 1244 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1245 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1246 // 1247 // Note: When i64 is illegal, this results in copy_s.w instructions instead 1248 // of copy_u.w instructions. This makes no difference to the behaviour 1249 // since i64 is only illegal when the register file is 32-bit. 1250 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1251 Op->getOperand(1), Op->getOperand(2)); 1252 case Intrinsic::mips_div_s_b: 1253 case Intrinsic::mips_div_s_h: 1254 case Intrinsic::mips_div_s_w: 1255 case Intrinsic::mips_div_s_d: 1256 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1257 Op->getOperand(2)); 1258 case Intrinsic::mips_div_u_b: 1259 case Intrinsic::mips_div_u_h: 1260 case Intrinsic::mips_div_u_w: 1261 case Intrinsic::mips_div_u_d: 1262 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1263 Op->getOperand(2)); 1264 case Intrinsic::mips_fadd_w: 1265 case Intrinsic::mips_fadd_d: 1266 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1267 Op->getOperand(2)); 1268 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1269 case Intrinsic::mips_fceq_w: 1270 case Intrinsic::mips_fceq_d: 1271 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1272 Op->getOperand(2), ISD::SETOEQ); 1273 case Intrinsic::mips_fcle_w: 1274 case Intrinsic::mips_fcle_d: 1275 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1276 Op->getOperand(2), ISD::SETOLE); 1277 case Intrinsic::mips_fclt_w: 1278 case Intrinsic::mips_fclt_d: 1279 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1280 Op->getOperand(2), ISD::SETOLT); 1281 case Intrinsic::mips_fcne_w: 1282 case Intrinsic::mips_fcne_d: 1283 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1284 Op->getOperand(2), ISD::SETONE); 1285 case Intrinsic::mips_fcor_w: 1286 case Intrinsic::mips_fcor_d: 1287 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1288 Op->getOperand(2), ISD::SETO); 1289 case Intrinsic::mips_fcueq_w: 1290 case Intrinsic::mips_fcueq_d: 1291 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1292 Op->getOperand(2), ISD::SETUEQ); 1293 case Intrinsic::mips_fcule_w: 1294 case Intrinsic::mips_fcule_d: 1295 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1296 Op->getOperand(2), ISD::SETULE); 1297 case Intrinsic::mips_fcult_w: 1298 case Intrinsic::mips_fcult_d: 1299 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1300 Op->getOperand(2), ISD::SETULT); 1301 case Intrinsic::mips_fcun_w: 1302 case Intrinsic::mips_fcun_d: 1303 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1304 Op->getOperand(2), ISD::SETUO); 1305 case Intrinsic::mips_fcune_w: 1306 case Intrinsic::mips_fcune_d: 1307 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1308 Op->getOperand(2), ISD::SETUNE); 1309 case Intrinsic::mips_fdiv_w: 1310 case Intrinsic::mips_fdiv_d: 1311 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1312 Op->getOperand(2)); 1313 case Intrinsic::mips_fill_b: 1314 case Intrinsic::mips_fill_h: 1315 case Intrinsic::mips_fill_w: 1316 case Intrinsic::mips_fill_d: { 1317 SmallVector<SDValue, 16> Ops; 1318 EVT ResTy = Op->getValueType(0); 1319 1320 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1321 Ops.push_back(Op->getOperand(1)); 1322 1323 // If ResTy is v2i64 then the type legalizer will break this node down into 1324 // an equivalent v4i32. 1325 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); 1326 } 1327 case Intrinsic::mips_flog2_w: 1328 case Intrinsic::mips_flog2_d: 1329 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1330 case Intrinsic::mips_fmul_w: 1331 case Intrinsic::mips_fmul_d: 1332 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1333 Op->getOperand(2)); 1334 case Intrinsic::mips_frint_w: 1335 case Intrinsic::mips_frint_d: 1336 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1337 case Intrinsic::mips_fsqrt_w: 1338 case Intrinsic::mips_fsqrt_d: 1339 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1340 case Intrinsic::mips_fsub_w: 1341 case Intrinsic::mips_fsub_d: 1342 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1343 Op->getOperand(2)); 1344 case Intrinsic::mips_ilvev_b: 1345 case Intrinsic::mips_ilvev_h: 1346 case Intrinsic::mips_ilvev_w: 1347 case Intrinsic::mips_ilvev_d: 1348 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1349 Op->getOperand(1), Op->getOperand(2)); 1350 case Intrinsic::mips_ilvl_b: 1351 case Intrinsic::mips_ilvl_h: 1352 case Intrinsic::mips_ilvl_w: 1353 case Intrinsic::mips_ilvl_d: 1354 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1355 Op->getOperand(1), Op->getOperand(2)); 1356 case Intrinsic::mips_ilvod_b: 1357 case Intrinsic::mips_ilvod_h: 1358 case Intrinsic::mips_ilvod_w: 1359 case Intrinsic::mips_ilvod_d: 1360 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1361 Op->getOperand(1), Op->getOperand(2)); 1362 case Intrinsic::mips_ilvr_b: 1363 case Intrinsic::mips_ilvr_h: 1364 case Intrinsic::mips_ilvr_w: 1365 case Intrinsic::mips_ilvr_d: 1366 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1367 Op->getOperand(1), Op->getOperand(2)); 1368 case Intrinsic::mips_insert_b: 1369 case Intrinsic::mips_insert_h: 1370 case Intrinsic::mips_insert_w: 1371 case Intrinsic::mips_insert_d: 1372 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1373 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1374 case Intrinsic::mips_ldi_b: 1375 case Intrinsic::mips_ldi_h: 1376 case Intrinsic::mips_ldi_w: 1377 case Intrinsic::mips_ldi_d: 1378 return lowerMSASplatImm(Op, 1, DAG); 1379 case Intrinsic::mips_max_s_b: 1380 case Intrinsic::mips_max_s_h: 1381 case Intrinsic::mips_max_s_w: 1382 case Intrinsic::mips_max_s_d: 1383 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1384 Op->getOperand(1), Op->getOperand(2)); 1385 case Intrinsic::mips_max_u_b: 1386 case Intrinsic::mips_max_u_h: 1387 case Intrinsic::mips_max_u_w: 1388 case Intrinsic::mips_max_u_d: 1389 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1390 Op->getOperand(1), Op->getOperand(2)); 1391 case Intrinsic::mips_maxi_s_b: 1392 case Intrinsic::mips_maxi_s_h: 1393 case Intrinsic::mips_maxi_s_w: 1394 case Intrinsic::mips_maxi_s_d: 1395 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1396 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1397 case Intrinsic::mips_maxi_u_b: 1398 case Intrinsic::mips_maxi_u_h: 1399 case Intrinsic::mips_maxi_u_w: 1400 case Intrinsic::mips_maxi_u_d: 1401 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1402 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1403 case Intrinsic::mips_min_s_b: 1404 case Intrinsic::mips_min_s_h: 1405 case Intrinsic::mips_min_s_w: 1406 case Intrinsic::mips_min_s_d: 1407 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1408 Op->getOperand(1), Op->getOperand(2)); 1409 case Intrinsic::mips_min_u_b: 1410 case Intrinsic::mips_min_u_h: 1411 case Intrinsic::mips_min_u_w: 1412 case Intrinsic::mips_min_u_d: 1413 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1414 Op->getOperand(1), Op->getOperand(2)); 1415 case Intrinsic::mips_mini_s_b: 1416 case Intrinsic::mips_mini_s_h: 1417 case Intrinsic::mips_mini_s_w: 1418 case Intrinsic::mips_mini_s_d: 1419 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1420 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1421 case Intrinsic::mips_mini_u_b: 1422 case Intrinsic::mips_mini_u_h: 1423 case Intrinsic::mips_mini_u_w: 1424 case Intrinsic::mips_mini_u_d: 1425 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1426 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1427 case Intrinsic::mips_mulv_b: 1428 case Intrinsic::mips_mulv_h: 1429 case Intrinsic::mips_mulv_w: 1430 case Intrinsic::mips_mulv_d: 1431 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 1432 Op->getOperand(2)); 1433 case Intrinsic::mips_nlzc_b: 1434 case Intrinsic::mips_nlzc_h: 1435 case Intrinsic::mips_nlzc_w: 1436 case Intrinsic::mips_nlzc_d: 1437 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 1438 case Intrinsic::mips_nor_v: { 1439 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1440 Op->getOperand(1), Op->getOperand(2)); 1441 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1442 } 1443 case Intrinsic::mips_nori_b: { 1444 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1445 Op->getOperand(1), 1446 lowerMSASplatImm(Op, 2, DAG)); 1447 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1448 } 1449 case Intrinsic::mips_or_v: 1450 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 1451 Op->getOperand(2)); 1452 case Intrinsic::mips_ori_b: 1453 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1454 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1455 case Intrinsic::mips_pckev_b: 1456 case Intrinsic::mips_pckev_h: 1457 case Intrinsic::mips_pckev_w: 1458 case Intrinsic::mips_pckev_d: 1459 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 1460 Op->getOperand(1), Op->getOperand(2)); 1461 case Intrinsic::mips_pckod_b: 1462 case Intrinsic::mips_pckod_h: 1463 case Intrinsic::mips_pckod_w: 1464 case Intrinsic::mips_pckod_d: 1465 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 1466 Op->getOperand(1), Op->getOperand(2)); 1467 case Intrinsic::mips_pcnt_b: 1468 case Intrinsic::mips_pcnt_h: 1469 case Intrinsic::mips_pcnt_w: 1470 case Intrinsic::mips_pcnt_d: 1471 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 1472 case Intrinsic::mips_shf_b: 1473 case Intrinsic::mips_shf_h: 1474 case Intrinsic::mips_shf_w: 1475 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 1476 Op->getOperand(2), Op->getOperand(1)); 1477 case Intrinsic::mips_sll_b: 1478 case Intrinsic::mips_sll_h: 1479 case Intrinsic::mips_sll_w: 1480 case Intrinsic::mips_sll_d: 1481 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 1482 Op->getOperand(2)); 1483 case Intrinsic::mips_slli_b: 1484 case Intrinsic::mips_slli_h: 1485 case Intrinsic::mips_slli_w: 1486 case Intrinsic::mips_slli_d: 1487 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 1488 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1489 case Intrinsic::mips_splati_b: 1490 case Intrinsic::mips_splati_h: 1491 case Intrinsic::mips_splati_w: 1492 case Intrinsic::mips_splati_d: 1493 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1494 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1495 Op->getOperand(1)); 1496 case Intrinsic::mips_sra_b: 1497 case Intrinsic::mips_sra_h: 1498 case Intrinsic::mips_sra_w: 1499 case Intrinsic::mips_sra_d: 1500 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 1501 Op->getOperand(2)); 1502 case Intrinsic::mips_srai_b: 1503 case Intrinsic::mips_srai_h: 1504 case Intrinsic::mips_srai_w: 1505 case Intrinsic::mips_srai_d: 1506 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 1507 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1508 case Intrinsic::mips_srl_b: 1509 case Intrinsic::mips_srl_h: 1510 case Intrinsic::mips_srl_w: 1511 case Intrinsic::mips_srl_d: 1512 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 1513 Op->getOperand(2)); 1514 case Intrinsic::mips_srli_b: 1515 case Intrinsic::mips_srli_h: 1516 case Intrinsic::mips_srli_w: 1517 case Intrinsic::mips_srli_d: 1518 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 1519 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1520 case Intrinsic::mips_subv_b: 1521 case Intrinsic::mips_subv_h: 1522 case Intrinsic::mips_subv_w: 1523 case Intrinsic::mips_subv_d: 1524 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 1525 Op->getOperand(2)); 1526 case Intrinsic::mips_subvi_b: 1527 case Intrinsic::mips_subvi_h: 1528 case Intrinsic::mips_subvi_w: 1529 case Intrinsic::mips_subvi_d: 1530 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 1531 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1532 case Intrinsic::mips_vshf_b: 1533 case Intrinsic::mips_vshf_h: 1534 case Intrinsic::mips_vshf_w: 1535 case Intrinsic::mips_vshf_d: 1536 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1537 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1538 case Intrinsic::mips_xor_v: 1539 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 1540 Op->getOperand(2)); 1541 case Intrinsic::mips_xori_b: 1542 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 1543 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1544 } 1545} 1546 1547static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1548 SDLoc DL(Op); 1549 SDValue ChainIn = Op->getOperand(0); 1550 SDValue Address = Op->getOperand(2); 1551 SDValue Offset = Op->getOperand(3); 1552 EVT ResTy = Op->getValueType(0); 1553 EVT PtrTy = Address->getValueType(0); 1554 1555 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1556 1557 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 1558 false, false, 16); 1559} 1560 1561SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 1562 SelectionDAG &DAG) const { 1563 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1564 switch (Intr) { 1565 default: 1566 return SDValue(); 1567 case Intrinsic::mips_extp: 1568 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 1569 case Intrinsic::mips_extpdp: 1570 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 1571 case Intrinsic::mips_extr_w: 1572 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 1573 case Intrinsic::mips_extr_r_w: 1574 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 1575 case Intrinsic::mips_extr_rs_w: 1576 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 1577 case Intrinsic::mips_extr_s_h: 1578 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 1579 case Intrinsic::mips_mthlip: 1580 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 1581 case Intrinsic::mips_mulsaq_s_w_ph: 1582 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 1583 case Intrinsic::mips_maq_s_w_phl: 1584 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 1585 case Intrinsic::mips_maq_s_w_phr: 1586 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 1587 case Intrinsic::mips_maq_sa_w_phl: 1588 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 1589 case Intrinsic::mips_maq_sa_w_phr: 1590 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 1591 case Intrinsic::mips_dpaq_s_w_ph: 1592 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 1593 case Intrinsic::mips_dpsq_s_w_ph: 1594 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 1595 case Intrinsic::mips_dpaq_sa_l_w: 1596 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 1597 case Intrinsic::mips_dpsq_sa_l_w: 1598 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 1599 case Intrinsic::mips_dpaqx_s_w_ph: 1600 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 1601 case Intrinsic::mips_dpaqx_sa_w_ph: 1602 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 1603 case Intrinsic::mips_dpsqx_s_w_ph: 1604 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 1605 case Intrinsic::mips_dpsqx_sa_w_ph: 1606 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 1607 case Intrinsic::mips_ld_b: 1608 case Intrinsic::mips_ld_h: 1609 case Intrinsic::mips_ld_w: 1610 case Intrinsic::mips_ld_d: 1611 case Intrinsic::mips_ldx_b: 1612 case Intrinsic::mips_ldx_h: 1613 case Intrinsic::mips_ldx_w: 1614 case Intrinsic::mips_ldx_d: 1615 return lowerMSALoadIntr(Op, DAG, Intr); 1616 } 1617} 1618 1619static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1620 SDLoc DL(Op); 1621 SDValue ChainIn = Op->getOperand(0); 1622 SDValue Value = Op->getOperand(2); 1623 SDValue Address = Op->getOperand(3); 1624 SDValue Offset = Op->getOperand(4); 1625 EVT PtrTy = Address->getValueType(0); 1626 1627 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1628 1629 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 1630 false, 16); 1631} 1632 1633SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 1634 SelectionDAG &DAG) const { 1635 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1636 switch (Intr) { 1637 default: 1638 return SDValue(); 1639 case Intrinsic::mips_st_b: 1640 case Intrinsic::mips_st_h: 1641 case Intrinsic::mips_st_w: 1642 case Intrinsic::mips_st_d: 1643 case Intrinsic::mips_stx_b: 1644 case Intrinsic::mips_stx_h: 1645 case Intrinsic::mips_stx_w: 1646 case Intrinsic::mips_stx_d: 1647 return lowerMSAStoreIntr(Op, DAG, Intr); 1648 } 1649} 1650 1651/// \brief Check if the given BuildVectorSDNode is a splat. 1652/// This method currently relies on DAG nodes being reused when equivalent, 1653/// so it's possible for this to return false even when isConstantSplat returns 1654/// true. 1655static bool isSplatVector(const BuildVectorSDNode *N) { 1656 unsigned int nOps = N->getNumOperands(); 1657 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector"); 1658 1659 SDValue Operand0 = N->getOperand(0); 1660 1661 for (unsigned int i = 1; i < nOps; ++i) { 1662 if (N->getOperand(i) != Operand0) 1663 return false; 1664 } 1665 1666 return true; 1667} 1668 1669// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 1670// 1671// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 1672// choose to sign-extend but we could have equally chosen zero-extend. The 1673// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 1674// result into this node later (possibly changing it to a zero-extend in the 1675// process). 1676SDValue MipsSETargetLowering:: 1677lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 1678 SDLoc DL(Op); 1679 EVT ResTy = Op->getValueType(0); 1680 SDValue Op0 = Op->getOperand(0); 1681 EVT VecTy = Op0->getValueType(0); 1682 1683 if (!VecTy.is128BitVector()) 1684 return SDValue(); 1685 1686 if (ResTy.isInteger()) { 1687 SDValue Op1 = Op->getOperand(1); 1688 EVT EltTy = VecTy.getVectorElementType(); 1689 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 1690 DAG.getValueType(EltTy)); 1691 } 1692 1693 return Op; 1694} 1695 1696static bool isConstantOrUndef(const SDValue Op) { 1697 if (Op->getOpcode() == ISD::UNDEF) 1698 return true; 1699 if (dyn_cast<ConstantSDNode>(Op)) 1700 return true; 1701 if (dyn_cast<ConstantFPSDNode>(Op)) 1702 return true; 1703 return false; 1704} 1705 1706static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 1707 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 1708 if (isConstantOrUndef(Op->getOperand(i))) 1709 return true; 1710 return false; 1711} 1712 1713// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 1714// backend. 1715// 1716// Lowers according to the following rules: 1717// - Constant splats are legal as-is as long as the SplatBitSize is a power of 1718// 2 less than or equal to 64 and the value fits into a signed 10-bit 1719// immediate 1720// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 1721// is a power of 2 less than or equal to 64 and the value does not fit into a 1722// signed 10-bit immediate 1723// - Non-constant splats are legal as-is. 1724// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 1725// - All others are illegal and must be expanded. 1726SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 1727 SelectionDAG &DAG) const { 1728 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 1729 EVT ResTy = Op->getValueType(0); 1730 SDLoc DL(Op); 1731 APInt SplatValue, SplatUndef; 1732 unsigned SplatBitSize; 1733 bool HasAnyUndefs; 1734 1735 if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) 1736 return SDValue(); 1737 1738 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 1739 HasAnyUndefs, 8, 1740 !Subtarget->isLittle()) && SplatBitSize <= 64) { 1741 // We can only cope with 8, 16, 32, or 64-bit elements 1742 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 1743 SplatBitSize != 64) 1744 return SDValue(); 1745 1746 // If the value fits into a simm10 then we can use ldi.[bhwd] 1747 if (SplatValue.isSignedIntN(10)) 1748 return Op; 1749 1750 EVT ViaVecTy; 1751 1752 switch (SplatBitSize) { 1753 default: 1754 return SDValue(); 1755 case 8: 1756 ViaVecTy = MVT::v16i8; 1757 break; 1758 case 16: 1759 ViaVecTy = MVT::v8i16; 1760 break; 1761 case 32: 1762 ViaVecTy = MVT::v4i32; 1763 break; 1764 case 64: 1765 // There's no fill.d to fall back on for 64-bit values 1766 return SDValue(); 1767 } 1768 1769 SmallVector<SDValue, 16> Ops; 1770 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32); 1771 1772 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) 1773 Ops.push_back(Constant); 1774 1775 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy, 1776 &Ops[0], Ops.size()); 1777 1778 if (ViaVecTy != ResTy) 1779 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 1780 1781 return Result; 1782 } else if (isSplatVector(Node)) 1783 return Op; 1784 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 1785 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 1786 // The resulting code is the same length as the expansion, but it doesn't 1787 // use memory operations 1788 EVT ResTy = Node->getValueType(0); 1789 1790 assert(ResTy.isVector()); 1791 1792 unsigned NumElts = ResTy.getVectorNumElements(); 1793 SDValue Vector = DAG.getUNDEF(ResTy); 1794 for (unsigned i = 0; i < NumElts; ++i) { 1795 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 1796 Node->getOperand(i), 1797 DAG.getConstant(i, MVT::i32)); 1798 } 1799 return Vector; 1800 } 1801 1802 return SDValue(); 1803} 1804 1805// Lower VECTOR_SHUFFLE into SHF (if possible). 1806// 1807// SHF splits the vector into blocks of four elements, then shuffles these 1808// elements according to a <4 x i2> constant (encoded as an integer immediate). 1809// 1810// It is therefore possible to lower into SHF when the mask takes the form: 1811// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 1812// When undef's appear they are treated as if they were whatever value is 1813// necessary in order to fit the above form. 1814// 1815// For example: 1816// %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 1817// <8 x i32> <i32 3, i32 2, i32 1, i32 0, 1818// i32 7, i32 6, i32 5, i32 4> 1819// is lowered to: 1820// (SHF_H $w0, $w1, 27) 1821// where the 27 comes from: 1822// 3 + (2 << 2) + (1 << 4) + (0 << 6) 1823static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 1824 SmallVector<int, 16> Indices, 1825 SelectionDAG &DAG) { 1826 int SHFIndices[4] = { -1, -1, -1, -1 }; 1827 1828 if (Indices.size() < 4) 1829 return SDValue(); 1830 1831 for (unsigned i = 0; i < 4; ++i) { 1832 for (unsigned j = i; j < Indices.size(); j += 4) { 1833 int Idx = Indices[j]; 1834 1835 // Convert from vector index to 4-element subvector index 1836 // If an index refers to an element outside of the subvector then give up 1837 if (Idx != -1) { 1838 Idx -= 4 * (j / 4); 1839 if (Idx < 0 || Idx >= 4) 1840 return SDValue(); 1841 } 1842 1843 // If the mask has an undef, replace it with the current index. 1844 // Note that it might still be undef if the current index is also undef 1845 if (SHFIndices[i] == -1) 1846 SHFIndices[i] = Idx; 1847 1848 // Check that non-undef values are the same as in the mask. If they 1849 // aren't then give up 1850 if (!(Idx == -1 || Idx == SHFIndices[i])) 1851 return SDValue(); 1852 } 1853 } 1854 1855 // Calculate the immediate. Replace any remaining undefs with zero 1856 APInt Imm(32, 0); 1857 for (int i = 3; i >= 0; --i) { 1858 int Idx = SHFIndices[i]; 1859 1860 if (Idx == -1) 1861 Idx = 0; 1862 1863 Imm <<= 2; 1864 Imm |= Idx & 0x3; 1865 } 1866 1867 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 1868 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 1869} 1870 1871// Lower VECTOR_SHUFFLE into ILVEV (if possible). 1872// 1873// ILVEV interleaves the even elements from each vector. 1874// 1875// It is possible to lower into ILVEV when the mask takes the form: 1876// <0, n, 2, n+2, 4, n+4, ...> 1877// where n is the number of elements in the vector. 1878// 1879// When undef's appear in the mask they are treated as if they were whatever 1880// value is necessary in order to fit the above form. 1881static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 1882 SmallVector<int, 16> Indices, 1883 SelectionDAG &DAG) { 1884 assert ((Indices.size() % 2) == 0); 1885 int WsIdx = 0; 1886 int WtIdx = ResTy.getVectorNumElements(); 1887 1888 for (unsigned i = 0; i < Indices.size(); i += 2) { 1889 if (Indices[i] != -1 && Indices[i] != WsIdx) 1890 return SDValue(); 1891 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1892 return SDValue(); 1893 WsIdx += 2; 1894 WtIdx += 2; 1895 } 1896 1897 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 1898 Op->getOperand(1)); 1899} 1900 1901// Lower VECTOR_SHUFFLE into ILVOD (if possible). 1902// 1903// ILVOD interleaves the odd elements from each vector. 1904// 1905// It is possible to lower into ILVOD when the mask takes the form: 1906// <1, n+1, 3, n+3, 5, n+5, ...> 1907// where n is the number of elements in the vector. 1908// 1909// When undef's appear in the mask they are treated as if they were whatever 1910// value is necessary in order to fit the above form. 1911static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 1912 SmallVector<int, 16> Indices, 1913 SelectionDAG &DAG) { 1914 assert ((Indices.size() % 2) == 0); 1915 int WsIdx = 1; 1916 int WtIdx = ResTy.getVectorNumElements() + 1; 1917 1918 for (unsigned i = 0; i < Indices.size(); i += 2) { 1919 if (Indices[i] != -1 && Indices[i] != WsIdx) 1920 return SDValue(); 1921 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1922 return SDValue(); 1923 WsIdx += 2; 1924 WtIdx += 2; 1925 } 1926 1927 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 1928 Op->getOperand(1)); 1929} 1930 1931// Lower VECTOR_SHUFFLE into ILVL (if possible). 1932// 1933// ILVL interleaves consecutive elements from the left half of each vector. 1934// 1935// It is possible to lower into ILVL when the mask takes the form: 1936// <0, n, 1, n+1, 2, n+2, ...> 1937// where n is the number of elements in the vector. 1938// 1939// When undef's appear in the mask they are treated as if they were whatever 1940// value is necessary in order to fit the above form. 1941static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 1942 SmallVector<int, 16> Indices, 1943 SelectionDAG &DAG) { 1944 assert ((Indices.size() % 2) == 0); 1945 int WsIdx = 0; 1946 int WtIdx = ResTy.getVectorNumElements(); 1947 1948 for (unsigned i = 0; i < Indices.size(); i += 2) { 1949 if (Indices[i] != -1 && Indices[i] != WsIdx) 1950 return SDValue(); 1951 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1952 return SDValue(); 1953 WsIdx ++; 1954 WtIdx ++; 1955 } 1956 1957 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 1958 Op->getOperand(1)); 1959} 1960 1961// Lower VECTOR_SHUFFLE into ILVR (if possible). 1962// 1963// ILVR interleaves consecutive elements from the right half of each vector. 1964// 1965// It is possible to lower into ILVR when the mask takes the form: 1966// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 1967// where n is the number of elements in the vector and x is half n. 1968// 1969// When undef's appear in the mask they are treated as if they were whatever 1970// value is necessary in order to fit the above form. 1971static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 1972 SmallVector<int, 16> Indices, 1973 SelectionDAG &DAG) { 1974 assert ((Indices.size() % 2) == 0); 1975 unsigned NumElts = ResTy.getVectorNumElements(); 1976 int WsIdx = NumElts / 2; 1977 int WtIdx = NumElts + NumElts / 2; 1978 1979 for (unsigned i = 0; i < Indices.size(); i += 2) { 1980 if (Indices[i] != -1 && Indices[i] != WsIdx) 1981 return SDValue(); 1982 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1983 return SDValue(); 1984 WsIdx ++; 1985 WtIdx ++; 1986 } 1987 1988 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 1989 Op->getOperand(1)); 1990} 1991 1992// Lower VECTOR_SHUFFLE into PCKEV (if possible). 1993// 1994// PCKEV copies the even elements of each vector into the result vector. 1995// 1996// It is possible to lower into PCKEV when the mask takes the form: 1997// <0, 2, 4, ..., n, n+2, n+4, ...> 1998// where n is the number of elements in the vector. 1999// 2000// When undef's appear in the mask they are treated as if they were whatever 2001// value is necessary in order to fit the above form. 2002static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2003 SmallVector<int, 16> Indices, 2004 SelectionDAG &DAG) { 2005 assert ((Indices.size() % 2) == 0); 2006 int Idx = 0; 2007 2008 for (unsigned i = 0; i < Indices.size(); ++i) { 2009 if (Indices[i] != -1 && Indices[i] != Idx) 2010 return SDValue(); 2011 Idx += 2; 2012 } 2013 2014 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2015 Op->getOperand(1)); 2016} 2017 2018// Lower VECTOR_SHUFFLE into PCKOD (if possible). 2019// 2020// PCKOD copies the odd elements of each vector into the result vector. 2021// 2022// It is possible to lower into PCKOD when the mask takes the form: 2023// <1, 3, 5, ..., n+1, n+3, n+5, ...> 2024// where n is the number of elements in the vector. 2025// 2026// When undef's appear in the mask they are treated as if they were whatever 2027// value is necessary in order to fit the above form. 2028static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2029 SmallVector<int, 16> Indices, 2030 SelectionDAG &DAG) { 2031 assert ((Indices.size() % 2) == 0); 2032 int Idx = 1; 2033 2034 for (unsigned i = 0; i < Indices.size(); ++i) { 2035 if (Indices[i] != -1 && Indices[i] != Idx) 2036 return SDValue(); 2037 Idx += 2; 2038 } 2039 2040 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2041 Op->getOperand(1)); 2042} 2043 2044// Lower VECTOR_SHUFFLE into VSHF. 2045// 2046// This mostly consists of converting the shuffle indices in Indices into a 2047// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2048// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2049// if the type is v8i16 and all the indices are less than 8 then the second 2050// operand is unused and can be replaced with anything. We choose to replace it 2051// with the used operand since this reduces the number of instructions overall. 2052static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2053 SmallVector<int, 16> Indices, 2054 SelectionDAG &DAG) { 2055 SmallVector<SDValue, 16> Ops; 2056 SDValue Op0; 2057 SDValue Op1; 2058 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2059 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2060 bool Using1stVec = false; 2061 bool Using2ndVec = false; 2062 SDLoc DL(Op); 2063 int ResTyNumElts = ResTy.getVectorNumElements(); 2064 2065 for (int i = 0; i < ResTyNumElts; ++i) { 2066 // Idx == -1 means UNDEF 2067 int Idx = Indices[i]; 2068 2069 if (0 <= Idx && Idx < ResTyNumElts) 2070 Using1stVec = true; 2071 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2072 Using2ndVec = true; 2073 } 2074 2075 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2076 ++I) 2077 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2078 2079 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0], 2080 Ops.size()); 2081 2082 if (Using1stVec && Using2ndVec) { 2083 Op0 = Op->getOperand(0); 2084 Op1 = Op->getOperand(1); 2085 } else if (Using1stVec) 2086 Op0 = Op1 = Op->getOperand(0); 2087 else if (Using2ndVec) 2088 Op0 = Op1 = Op->getOperand(1); 2089 else 2090 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2091 2092 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1); 2093} 2094 2095// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2096// indices in the shuffle. 2097SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2098 SelectionDAG &DAG) const { 2099 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2100 EVT ResTy = Op->getValueType(0); 2101 2102 if (!ResTy.is128BitVector()) 2103 return SDValue(); 2104 2105 int ResTyNumElts = ResTy.getVectorNumElements(); 2106 SmallVector<int, 16> Indices; 2107 2108 for (int i = 0; i < ResTyNumElts; ++i) 2109 Indices.push_back(Node->getMaskElt(i)); 2110 2111 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2112 if (Result.getNode()) 2113 return Result; 2114 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2115 if (Result.getNode()) 2116 return Result; 2117 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2118 if (Result.getNode()) 2119 return Result; 2120 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2121 if (Result.getNode()) 2122 return Result; 2123 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2124 if (Result.getNode()) 2125 return Result; 2126 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2127 if (Result.getNode()) 2128 return Result; 2129 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2130 if (Result.getNode()) 2131 return Result; 2132 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2133} 2134 2135MachineBasicBlock * MipsSETargetLowering:: 2136emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2137 // $bb: 2138 // bposge32_pseudo $vr0 2139 // => 2140 // $bb: 2141 // bposge32 $tbb 2142 // $fbb: 2143 // li $vr2, 0 2144 // b $sink 2145 // $tbb: 2146 // li $vr1, 1 2147 // $sink: 2148 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2149 2150 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2151 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2152 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2153 DebugLoc DL = MI->getDebugLoc(); 2154 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2155 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2156 MachineFunction *F = BB->getParent(); 2157 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2158 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2159 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2160 F->insert(It, FBB); 2161 F->insert(It, TBB); 2162 F->insert(It, Sink); 2163 2164 // Transfer the remainder of BB and its successor edges to Sink. 2165 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2166 BB->end()); 2167 Sink->transferSuccessorsAndUpdatePHIs(BB); 2168 2169 // Add successors. 2170 BB->addSuccessor(FBB); 2171 BB->addSuccessor(TBB); 2172 FBB->addSuccessor(Sink); 2173 TBB->addSuccessor(Sink); 2174 2175 // Insert the real bposge32 instruction to $BB. 2176 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2177 2178 // Fill $FBB. 2179 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2180 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2181 .addReg(Mips::ZERO).addImm(0); 2182 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2183 2184 // Fill $TBB. 2185 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2186 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2187 .addReg(Mips::ZERO).addImm(1); 2188 2189 // Insert phi function to $Sink. 2190 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2191 MI->getOperand(0).getReg()) 2192 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2193 2194 MI->eraseFromParent(); // The pseudo instruction is gone now. 2195 return Sink; 2196} 2197 2198MachineBasicBlock * MipsSETargetLowering:: 2199emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2200 unsigned BranchOp) const{ 2201 // $bb: 2202 // vany_nonzero $rd, $ws 2203 // => 2204 // $bb: 2205 // bnz.b $ws, $tbb 2206 // b $fbb 2207 // $fbb: 2208 // li $rd1, 0 2209 // b $sink 2210 // $tbb: 2211 // li $rd2, 1 2212 // $sink: 2213 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2214 2215 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2217 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2218 DebugLoc DL = MI->getDebugLoc(); 2219 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2220 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2221 MachineFunction *F = BB->getParent(); 2222 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2223 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2224 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2225 F->insert(It, FBB); 2226 F->insert(It, TBB); 2227 F->insert(It, Sink); 2228 2229 // Transfer the remainder of BB and its successor edges to Sink. 2230 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2231 BB->end()); 2232 Sink->transferSuccessorsAndUpdatePHIs(BB); 2233 2234 // Add successors. 2235 BB->addSuccessor(FBB); 2236 BB->addSuccessor(TBB); 2237 FBB->addSuccessor(Sink); 2238 TBB->addSuccessor(Sink); 2239 2240 // Insert the real bnz.b instruction to $BB. 2241 BuildMI(BB, DL, TII->get(BranchOp)) 2242 .addReg(MI->getOperand(1).getReg()) 2243 .addMBB(TBB); 2244 2245 // Fill $FBB. 2246 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2247 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2248 .addReg(Mips::ZERO).addImm(0); 2249 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2250 2251 // Fill $TBB. 2252 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2253 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2254 .addReg(Mips::ZERO).addImm(1); 2255 2256 // Insert phi function to $Sink. 2257 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2258 MI->getOperand(0).getReg()) 2259 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2260 2261 MI->eraseFromParent(); // The pseudo instruction is gone now. 2262 return Sink; 2263} 2264 2265// Emit the COPY_FW pseudo instruction. 2266// 2267// copy_fw_pseudo $fd, $ws, n 2268// => 2269// copy_u_w $rt, $ws, $n 2270// mtc1 $rt, $fd 2271// 2272// When n is zero, the equivalent operation can be performed with (potentially) 2273// zero instructions due to register overlaps. This optimization is never valid 2274// for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2275MachineBasicBlock * MipsSETargetLowering:: 2276emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2277 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2278 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2279 DebugLoc DL = MI->getDebugLoc(); 2280 unsigned Fd = MI->getOperand(0).getReg(); 2281 unsigned Ws = MI->getOperand(1).getReg(); 2282 unsigned Lane = MI->getOperand(2).getImm(); 2283 2284 if (Lane == 0) 2285 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2286 else { 2287 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2288 2289 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); 2290 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2291 } 2292 2293 MI->eraseFromParent(); // The pseudo instruction is gone now. 2294 return BB; 2295} 2296 2297// Emit the COPY_FD pseudo instruction. 2298// 2299// copy_fd_pseudo $fd, $ws, n 2300// => 2301// splati.d $wt, $ws, $n 2302// copy $fd, $wt:sub_64 2303// 2304// When n is zero, the equivalent operation can be performed with (potentially) 2305// zero instructions due to register overlaps. This optimization is always 2306// valid because FR=1 mode which is the only supported mode in MSA. 2307MachineBasicBlock * MipsSETargetLowering:: 2308emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2309 assert(Subtarget->isFP64bit()); 2310 2311 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2312 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2313 unsigned Fd = MI->getOperand(0).getReg(); 2314 unsigned Ws = MI->getOperand(1).getReg(); 2315 unsigned Lane = MI->getOperand(2).getImm() * 2; 2316 DebugLoc DL = MI->getDebugLoc(); 2317 2318 if (Lane == 0) 2319 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2320 else { 2321 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2322 2323 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2324 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2325 } 2326 2327 MI->eraseFromParent(); // The pseudo instruction is gone now. 2328 return BB; 2329} 2330 2331// Emit the INSERT_FW pseudo instruction. 2332// 2333// insert_fw_pseudo $wd, $wd_in, $n, $fs 2334// => 2335// subreg_to_reg $wt:sub_lo, $fs 2336// insve_w $wd[$n], $wd_in, $wt[0] 2337MachineBasicBlock * MipsSETargetLowering:: 2338emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2339 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2340 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2341 DebugLoc DL = MI->getDebugLoc(); 2342 unsigned Wd = MI->getOperand(0).getReg(); 2343 unsigned Wd_in = MI->getOperand(1).getReg(); 2344 unsigned Lane = MI->getOperand(2).getImm(); 2345 unsigned Fs = MI->getOperand(3).getReg(); 2346 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2347 2348 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2349 .addImm(0).addReg(Fs).addImm(Mips::sub_lo); 2350 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2351 .addReg(Wd_in).addImm(Lane).addReg(Wt); 2352 2353 MI->eraseFromParent(); // The pseudo instruction is gone now. 2354 return BB; 2355} 2356 2357// Emit the INSERT_FD pseudo instruction. 2358// 2359// insert_fd_pseudo $wd, $fs, n 2360// => 2361// subreg_to_reg $wt:sub_64, $fs 2362// insve_d $wd[$n], $wd_in, $wt[0] 2363MachineBasicBlock * MipsSETargetLowering:: 2364emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2365 assert(Subtarget->isFP64bit()); 2366 2367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2368 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2369 DebugLoc DL = MI->getDebugLoc(); 2370 unsigned Wd = MI->getOperand(0).getReg(); 2371 unsigned Wd_in = MI->getOperand(1).getReg(); 2372 unsigned Lane = MI->getOperand(2).getImm(); 2373 unsigned Fs = MI->getOperand(3).getReg(); 2374 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2375 2376 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2377 .addImm(0).addReg(Fs).addImm(Mips::sub_64); 2378 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2379 .addReg(Wd_in).addImm(Lane).addReg(Wt); 2380 2381 MI->eraseFromParent(); // The pseudo instruction is gone now. 2382 return BB; 2383} 2384