MipsSEISelLowering.cpp revision 52244da7f2b3def646900520668b859343b84a33
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips32/64. 11// 12//===----------------------------------------------------------------------===// 13#include "MipsSEISelLowering.h" 14#include "MipsRegisterInfo.h" 15#include "MipsTargetMachine.h" 16#include "llvm/CodeGen/MachineInstrBuilder.h" 17#include "llvm/CodeGen/MachineRegisterInfo.h" 18#include "llvm/IR/Intrinsics.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22using namespace llvm; 23 24static cl::opt<bool> 25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 26 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 27 28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 29 cl::desc("Expand double precision loads and " 30 "stores to their single precision " 31 "counterparts")); 32 33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) 34 : MipsTargetLowering(TM) { 35 // Set up the register classes 36 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 37 38 if (HasMips64) 39 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 40 41 if (Subtarget->hasDSP() || Subtarget->hasMSA()) { 42 // Expand all truncating stores and extending loads. 43 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 44 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 45 46 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { 47 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) 48 setTruncStoreAction((MVT::SimpleValueType)VT0, 49 (MVT::SimpleValueType)VT1, Expand); 50 51 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 52 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 53 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); 54 } 55 } 56 57 if (Subtarget->hasDSP()) { 58 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 59 60 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 61 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 62 63 // Expand all builtin opcodes. 64 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 65 setOperationAction(Opc, VecTys[i], Expand); 66 67 setOperationAction(ISD::ADD, VecTys[i], Legal); 68 setOperationAction(ISD::SUB, VecTys[i], Legal); 69 setOperationAction(ISD::LOAD, VecTys[i], Legal); 70 setOperationAction(ISD::STORE, VecTys[i], Legal); 71 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 72 } 73 74 setTargetDAGCombine(ISD::SHL); 75 setTargetDAGCombine(ISD::SRA); 76 setTargetDAGCombine(ISD::SRL); 77 setTargetDAGCombine(ISD::SETCC); 78 setTargetDAGCombine(ISD::VSELECT); 79 } 80 81 if (Subtarget->hasDSPR2()) 82 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 83 84 if (Subtarget->hasMSA()) { 85 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 86 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 87 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 88 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 89 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 90 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 91 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 92 93 setTargetDAGCombine(ISD::AND); 94 setTargetDAGCombine(ISD::SRA); 95 setTargetDAGCombine(ISD::VSELECT); 96 setTargetDAGCombine(ISD::XOR); 97 } 98 99 if (!Subtarget->mipsSEUsesSoftFloat()) { 100 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 101 102 // When dealing with single precision only, use libcalls 103 if (!Subtarget->isSingleFloat()) { 104 if (Subtarget->isFP64bit()) 105 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 106 else 107 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 108 } 109 } 110 111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 112 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 113 setOperationAction(ISD::MULHS, MVT::i32, Custom); 114 setOperationAction(ISD::MULHU, MVT::i32, Custom); 115 116 if (HasMips64) { 117 setOperationAction(ISD::MULHS, MVT::i64, Custom); 118 setOperationAction(ISD::MULHU, MVT::i64, Custom); 119 setOperationAction(ISD::MUL, MVT::i64, Custom); 120 } 121 122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 123 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 124 125 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 126 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 127 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 128 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 129 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 130 setOperationAction(ISD::LOAD, MVT::i32, Custom); 131 setOperationAction(ISD::STORE, MVT::i32, Custom); 132 133 setTargetDAGCombine(ISD::ADDE); 134 setTargetDAGCombine(ISD::SUBE); 135 setTargetDAGCombine(ISD::MUL); 136 137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 138 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 139 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 140 141 if (NoDPLoadStore) { 142 setOperationAction(ISD::LOAD, MVT::f64, Custom); 143 setOperationAction(ISD::STORE, MVT::f64, Custom); 144 } 145 146 computeRegisterProperties(); 147} 148 149const MipsTargetLowering * 150llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { 151 return new MipsSETargetLowering(TM); 152} 153 154// Enable MSA support for the given integer type and Register class. 155void MipsSETargetLowering:: 156addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 157 addRegisterClass(Ty, RC); 158 159 // Expand all builtin opcodes. 160 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 161 setOperationAction(Opc, Ty, Expand); 162 163 setOperationAction(ISD::BITCAST, Ty, Legal); 164 setOperationAction(ISD::LOAD, Ty, Legal); 165 setOperationAction(ISD::STORE, Ty, Legal); 166 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 167 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 168 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 169 170 setOperationAction(ISD::ADD, Ty, Legal); 171 setOperationAction(ISD::AND, Ty, Legal); 172 setOperationAction(ISD::CTLZ, Ty, Legal); 173 setOperationAction(ISD::CTPOP, Ty, Legal); 174 setOperationAction(ISD::MUL, Ty, Legal); 175 setOperationAction(ISD::OR, Ty, Legal); 176 setOperationAction(ISD::SDIV, Ty, Legal); 177 setOperationAction(ISD::SREM, Ty, Legal); 178 setOperationAction(ISD::SHL, Ty, Legal); 179 setOperationAction(ISD::SRA, Ty, Legal); 180 setOperationAction(ISD::SRL, Ty, Legal); 181 setOperationAction(ISD::SUB, Ty, Legal); 182 setOperationAction(ISD::UDIV, Ty, Legal); 183 setOperationAction(ISD::UREM, Ty, Legal); 184 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 185 setOperationAction(ISD::VSELECT, Ty, Legal); 186 setOperationAction(ISD::XOR, Ty, Legal); 187 188 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 189 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); 190 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); 191 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 192 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 193 } 194 195 setOperationAction(ISD::SETCC, Ty, Legal); 196 setCondCodeAction(ISD::SETNE, Ty, Expand); 197 setCondCodeAction(ISD::SETGE, Ty, Expand); 198 setCondCodeAction(ISD::SETGT, Ty, Expand); 199 setCondCodeAction(ISD::SETUGE, Ty, Expand); 200 setCondCodeAction(ISD::SETUGT, Ty, Expand); 201} 202 203// Enable MSA support for the given floating-point type and Register class. 204void MipsSETargetLowering:: 205addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 206 addRegisterClass(Ty, RC); 207 208 // Expand all builtin opcodes. 209 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 210 setOperationAction(Opc, Ty, Expand); 211 212 setOperationAction(ISD::LOAD, Ty, Legal); 213 setOperationAction(ISD::STORE, Ty, Legal); 214 setOperationAction(ISD::BITCAST, Ty, Legal); 215 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 216 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 217 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 218 219 if (Ty != MVT::v8f16) { 220 setOperationAction(ISD::FABS, Ty, Legal); 221 setOperationAction(ISD::FADD, Ty, Legal); 222 setOperationAction(ISD::FDIV, Ty, Legal); 223 setOperationAction(ISD::FLOG2, Ty, Legal); 224 setOperationAction(ISD::FMA, Ty, Legal); 225 setOperationAction(ISD::FMUL, Ty, Legal); 226 setOperationAction(ISD::FRINT, Ty, Legal); 227 setOperationAction(ISD::FSQRT, Ty, Legal); 228 setOperationAction(ISD::FSUB, Ty, Legal); 229 setOperationAction(ISD::VSELECT, Ty, Legal); 230 231 setOperationAction(ISD::SETCC, Ty, Legal); 232 setCondCodeAction(ISD::SETOGE, Ty, Expand); 233 setCondCodeAction(ISD::SETOGT, Ty, Expand); 234 setCondCodeAction(ISD::SETUGE, Ty, Expand); 235 setCondCodeAction(ISD::SETUGT, Ty, Expand); 236 setCondCodeAction(ISD::SETGE, Ty, Expand); 237 setCondCodeAction(ISD::SETGT, Ty, Expand); 238 } 239} 240 241bool 242MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 243 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 244 245 switch (SVT) { 246 case MVT::i64: 247 case MVT::i32: 248 if (Fast) 249 *Fast = true; 250 return true; 251 default: 252 return false; 253 } 254} 255 256SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 257 SelectionDAG &DAG) const { 258 switch(Op.getOpcode()) { 259 case ISD::LOAD: return lowerLOAD(Op, DAG); 260 case ISD::STORE: return lowerSTORE(Op, DAG); 261 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 262 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 263 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 264 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 265 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 266 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 267 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 268 DAG); 269 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 270 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 271 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 272 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 273 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 274 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 275 } 276 277 return MipsTargetLowering::LowerOperation(Op, DAG); 278} 279 280// selectMADD - 281// Transforms a subgraph in CurDAG if the following pattern is found: 282// (addc multLo, Lo0), (adde multHi, Hi0), 283// where, 284// multHi/Lo: product of multiplication 285// Lo0: initial value of Lo register 286// Hi0: initial value of Hi register 287// Return true if pattern matching was successful. 288static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 289 // ADDENode's second operand must be a flag output of an ADDC node in order 290 // for the matching to be successful. 291 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 292 293 if (ADDCNode->getOpcode() != ISD::ADDC) 294 return false; 295 296 SDValue MultHi = ADDENode->getOperand(0); 297 SDValue MultLo = ADDCNode->getOperand(0); 298 SDNode *MultNode = MultHi.getNode(); 299 unsigned MultOpc = MultHi.getOpcode(); 300 301 // MultHi and MultLo must be generated by the same node, 302 if (MultLo.getNode() != MultNode) 303 return false; 304 305 // and it must be a multiplication. 306 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 307 return false; 308 309 // MultLo amd MultHi must be the first and second output of MultNode 310 // respectively. 311 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 312 return false; 313 314 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 315 // of the values of MultNode, in which case MultNode will be removed in later 316 // phases. 317 // If there exist users other than ADDENode or ADDCNode, this function returns 318 // here, which will result in MultNode being mapped to a single MULT 319 // instruction node rather than a pair of MULT and MADD instructions being 320 // produced. 321 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 322 return false; 323 324 SDLoc DL(ADDENode); 325 326 // Initialize accumulator. 327 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 328 ADDCNode->getOperand(1), 329 ADDENode->getOperand(1)); 330 331 // create MipsMAdd(u) node 332 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 333 334 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 335 MultNode->getOperand(0),// Factor 0 336 MultNode->getOperand(1),// Factor 1 337 ACCIn); 338 339 // replace uses of adde and addc here 340 if (!SDValue(ADDCNode, 0).use_empty()) { 341 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 342 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 343 } 344 if (!SDValue(ADDENode, 0).use_empty()) { 345 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 346 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 347 } 348 349 return true; 350} 351 352// selectMSUB - 353// Transforms a subgraph in CurDAG if the following pattern is found: 354// (addc Lo0, multLo), (sube Hi0, multHi), 355// where, 356// multHi/Lo: product of multiplication 357// Lo0: initial value of Lo register 358// Hi0: initial value of Hi register 359// Return true if pattern matching was successful. 360static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 361 // SUBENode's second operand must be a flag output of an SUBC node in order 362 // for the matching to be successful. 363 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 364 365 if (SUBCNode->getOpcode() != ISD::SUBC) 366 return false; 367 368 SDValue MultHi = SUBENode->getOperand(1); 369 SDValue MultLo = SUBCNode->getOperand(1); 370 SDNode *MultNode = MultHi.getNode(); 371 unsigned MultOpc = MultHi.getOpcode(); 372 373 // MultHi and MultLo must be generated by the same node, 374 if (MultLo.getNode() != MultNode) 375 return false; 376 377 // and it must be a multiplication. 378 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 379 return false; 380 381 // MultLo amd MultHi must be the first and second output of MultNode 382 // respectively. 383 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 384 return false; 385 386 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 387 // of the values of MultNode, in which case MultNode will be removed in later 388 // phases. 389 // If there exist users other than SUBENode or SUBCNode, this function returns 390 // here, which will result in MultNode being mapped to a single MULT 391 // instruction node rather than a pair of MULT and MSUB instructions being 392 // produced. 393 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 394 return false; 395 396 SDLoc DL(SUBENode); 397 398 // Initialize accumulator. 399 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 400 SUBCNode->getOperand(0), 401 SUBENode->getOperand(0)); 402 403 // create MipsSub(u) node 404 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 405 406 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 407 MultNode->getOperand(0),// Factor 0 408 MultNode->getOperand(1),// Factor 1 409 ACCIn); 410 411 // replace uses of sube and subc here 412 if (!SDValue(SUBCNode, 0).use_empty()) { 413 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); 414 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 415 } 416 if (!SDValue(SUBENode, 0).use_empty()) { 417 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); 418 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 419 } 420 421 return true; 422} 423 424static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 425 TargetLowering::DAGCombinerInfo &DCI, 426 const MipsSubtarget *Subtarget) { 427 if (DCI.isBeforeLegalize()) 428 return SDValue(); 429 430 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 431 selectMADD(N, &DAG)) 432 return SDValue(N, 0); 433 434 return SDValue(); 435} 436 437// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 438// 439// Performs the following transformations: 440// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 441// sign/zero-extension is completely overwritten by the new one performed by 442// the ISD::AND. 443// - Removes redundant zero extensions performed by an ISD::AND. 444static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 445 TargetLowering::DAGCombinerInfo &DCI, 446 const MipsSubtarget *Subtarget) { 447 if (!Subtarget->hasMSA()) 448 return SDValue(); 449 450 SDValue Op0 = N->getOperand(0); 451 SDValue Op1 = N->getOperand(1); 452 unsigned Op0Opcode = Op0->getOpcode(); 453 454 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 455 // where $d + 1 == 2^n and n == 32 456 // or $d + 1 == 2^n and n <= 32 and ZExt 457 // -> (MipsVExtractZExt $a, $b, $c) 458 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 459 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 460 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 461 462 if (!Mask) 463 return SDValue(); 464 465 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 466 467 if (Log2IfPositive <= 0) 468 return SDValue(); // Mask+1 is not a power of 2 469 470 SDValue Op0Op2 = Op0->getOperand(2); 471 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 472 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 473 unsigned Log2 = Log2IfPositive; 474 475 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 476 Log2 == ExtendTySize) { 477 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 478 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 479 Op0->getVTList(), Ops, Op0->getNumOperands()); 480 return Op0; 481 } 482 } 483 484 return SDValue(); 485} 486 487static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 488 TargetLowering::DAGCombinerInfo &DCI, 489 const MipsSubtarget *Subtarget) { 490 if (DCI.isBeforeLegalize()) 491 return SDValue(); 492 493 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 494 selectMSUB(N, &DAG)) 495 return SDValue(N, 0); 496 497 return SDValue(); 498} 499 500static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 501 EVT ShiftTy, SelectionDAG &DAG) { 502 // Clear the upper (64 - VT.sizeInBits) bits. 503 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 504 505 // Return 0. 506 if (C == 0) 507 return DAG.getConstant(0, VT); 508 509 // Return x. 510 if (C == 1) 511 return X; 512 513 // If c is power of 2, return (shl x, log2(c)). 514 if (isPowerOf2_64(C)) 515 return DAG.getNode(ISD::SHL, DL, VT, X, 516 DAG.getConstant(Log2_64(C), ShiftTy)); 517 518 unsigned Log2Ceil = Log2_64_Ceil(C); 519 uint64_t Floor = 1LL << Log2_64(C); 520 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 521 522 // If |c - floor_c| <= |c - ceil_c|, 523 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 524 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 525 if (C - Floor <= Ceil - C) { 526 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 527 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 528 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 529 } 530 531 // If |c - floor_c| > |c - ceil_c|, 532 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 533 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 534 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 535 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 536} 537 538static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 539 const TargetLowering::DAGCombinerInfo &DCI, 540 const MipsSETargetLowering *TL) { 541 EVT VT = N->getValueType(0); 542 543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 544 if (!VT.isVector()) 545 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 546 VT, TL->getScalarShiftAmountTy(VT), DAG); 547 548 return SDValue(N, 0); 549} 550 551static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 552 SelectionDAG &DAG, 553 const MipsSubtarget *Subtarget) { 554 // See if this is a vector splat immediate node. 555 APInt SplatValue, SplatUndef; 556 unsigned SplatBitSize; 557 bool HasAnyUndefs; 558 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 559 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 560 561 if (!BV || 562 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 563 EltSize, !Subtarget->isLittle()) || 564 (SplatBitSize != EltSize) || 565 (SplatValue.getZExtValue() >= EltSize)) 566 return SDValue(); 567 568 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 569 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 570} 571 572static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 573 TargetLowering::DAGCombinerInfo &DCI, 574 const MipsSubtarget *Subtarget) { 575 EVT Ty = N->getValueType(0); 576 577 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 578 return SDValue(); 579 580 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 581} 582 583// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 584// constant splats into MipsISD::SHRA_DSP for DSPr2. 585// 586// Performs the following transformations: 587// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 588// sign/zero-extension is completely overwritten by the new one performed by 589// the ISD::SRA and ISD::SHL nodes. 590// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 591// sequence. 592// 593// See performDSPShiftCombine for more information about the transformation 594// used for DSPr2. 595static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 596 TargetLowering::DAGCombinerInfo &DCI, 597 const MipsSubtarget *Subtarget) { 598 EVT Ty = N->getValueType(0); 599 600 if (Subtarget->hasMSA()) { 601 SDValue Op0 = N->getOperand(0); 602 SDValue Op1 = N->getOperand(1); 603 604 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 605 // where $d + sizeof($c) == 32 606 // or $d + sizeof($c) <= 32 and SExt 607 // -> (MipsVExtractSExt $a, $b, $c) 608 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 609 SDValue Op0Op0 = Op0->getOperand(0); 610 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 611 612 if (!ShAmount) 613 return SDValue(); 614 615 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 616 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 617 return SDValue(); 618 619 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 620 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 621 622 if (TotalBits == 32 || 623 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 624 TotalBits <= 32)) { 625 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 626 Op0Op0->getOperand(2) }; 627 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, 628 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands()); 629 return Op0Op0; 630 } 631 } 632 } 633 634 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) 635 return SDValue(); 636 637 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 638} 639 640 641static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 642 TargetLowering::DAGCombinerInfo &DCI, 643 const MipsSubtarget *Subtarget) { 644 EVT Ty = N->getValueType(0); 645 646 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) 647 return SDValue(); 648 649 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 650} 651 652static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 653 bool IsV216 = (Ty == MVT::v2i16); 654 655 switch (CC) { 656 case ISD::SETEQ: 657 case ISD::SETNE: return true; 658 case ISD::SETLT: 659 case ISD::SETLE: 660 case ISD::SETGT: 661 case ISD::SETGE: return IsV216; 662 case ISD::SETULT: 663 case ISD::SETULE: 664 case ISD::SETUGT: 665 case ISD::SETUGE: return !IsV216; 666 default: return false; 667 } 668} 669 670static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 671 EVT Ty = N->getValueType(0); 672 673 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 674 return SDValue(); 675 676 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 677 return SDValue(); 678 679 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 680 N->getOperand(1), N->getOperand(2)); 681} 682 683static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 684 EVT Ty = N->getValueType(0); 685 686 if (Ty.is128BitVector() && Ty.isInteger()) { 687 // Try the following combines: 688 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 689 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 690 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 691 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 692 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 693 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 694 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 695 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 696 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 697 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 698 // legalizer. 699 SDValue Op0 = N->getOperand(0); 700 701 if (Op0->getOpcode() != ISD::SETCC) 702 return SDValue(); 703 704 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 705 bool Signed; 706 707 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 708 Signed = true; 709 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 710 Signed = false; 711 else 712 return SDValue(); 713 714 SDValue Op1 = N->getOperand(1); 715 SDValue Op2 = N->getOperand(2); 716 SDValue Op0Op0 = Op0->getOperand(0); 717 SDValue Op0Op1 = Op0->getOperand(1); 718 719 if (Op1 == Op0Op0 && Op2 == Op0Op1) 720 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 721 Ty, Op1, Op2); 722 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 723 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 724 Ty, Op1, Op2); 725 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 726 SDValue SetCC = N->getOperand(0); 727 728 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 729 return SDValue(); 730 731 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 732 SetCC.getOperand(0), SetCC.getOperand(1), 733 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 734 } 735 736 return SDValue(); 737} 738 739static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 740 const MipsSubtarget *Subtarget) { 741 EVT Ty = N->getValueType(0); 742 743 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 744 // Try the following combines: 745 // (xor (or $a, $b), (build_vector allones)) 746 // (xor (or $a, $b), (bitcast (build_vector allones))) 747 SDValue Op0 = N->getOperand(0); 748 SDValue Op1 = N->getOperand(1); 749 SDValue NotOp; 750 751 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 752 NotOp = Op1; 753 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 754 NotOp = Op0; 755 else 756 return SDValue(); 757 758 if (NotOp->getOpcode() == ISD::OR) 759 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 760 NotOp->getOperand(1)); 761 } 762 763 return SDValue(); 764} 765 766SDValue 767MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 768 SelectionDAG &DAG = DCI.DAG; 769 SDValue Val; 770 771 switch (N->getOpcode()) { 772 case ISD::ADDE: 773 return performADDECombine(N, DAG, DCI, Subtarget); 774 case ISD::AND: 775 Val = performANDCombine(N, DAG, DCI, Subtarget); 776 break; 777 case ISD::SUBE: 778 return performSUBECombine(N, DAG, DCI, Subtarget); 779 case ISD::MUL: 780 return performMULCombine(N, DAG, DCI, this); 781 case ISD::SHL: 782 return performSHLCombine(N, DAG, DCI, Subtarget); 783 case ISD::SRA: 784 return performSRACombine(N, DAG, DCI, Subtarget); 785 case ISD::SRL: 786 return performSRLCombine(N, DAG, DCI, Subtarget); 787 case ISD::VSELECT: 788 return performVSELECTCombine(N, DAG); 789 case ISD::XOR: 790 Val = performXORCombine(N, DAG, Subtarget); 791 break; 792 case ISD::SETCC: 793 Val = performSETCCCombine(N, DAG); 794 break; 795 } 796 797 if (Val.getNode()) 798 return Val; 799 800 return MipsTargetLowering::PerformDAGCombine(N, DCI); 801} 802 803MachineBasicBlock * 804MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 805 MachineBasicBlock *BB) const { 806 switch (MI->getOpcode()) { 807 default: 808 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 809 case Mips::BPOSGE32_PSEUDO: 810 return emitBPOSGE32(MI, BB); 811 case Mips::SNZ_B_PSEUDO: 812 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 813 case Mips::SNZ_H_PSEUDO: 814 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 815 case Mips::SNZ_W_PSEUDO: 816 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 817 case Mips::SNZ_D_PSEUDO: 818 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 819 case Mips::SNZ_V_PSEUDO: 820 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 821 case Mips::SZ_B_PSEUDO: 822 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 823 case Mips::SZ_H_PSEUDO: 824 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 825 case Mips::SZ_W_PSEUDO: 826 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 827 case Mips::SZ_D_PSEUDO: 828 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 829 case Mips::SZ_V_PSEUDO: 830 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 831 case Mips::COPY_FW_PSEUDO: 832 return emitCOPY_FW(MI, BB); 833 case Mips::COPY_FD_PSEUDO: 834 return emitCOPY_FD(MI, BB); 835 case Mips::INSERT_FW_PSEUDO: 836 return emitINSERT_FW(MI, BB); 837 case Mips::INSERT_FD_PSEUDO: 838 return emitINSERT_FD(MI, BB); 839 case Mips::FILL_FW_PSEUDO: 840 return emitFILL_FW(MI, BB); 841 case Mips::FILL_FD_PSEUDO: 842 return emitFILL_FD(MI, BB); 843 } 844} 845 846bool MipsSETargetLowering:: 847isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 848 unsigned NextStackOffset, 849 const MipsFunctionInfo& FI) const { 850 if (!EnableMipsTailCalls) 851 return false; 852 853 // Return false if either the callee or caller has a byval argument. 854 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 855 return false; 856 857 // Return true if the callee's argument area is no larger than the 858 // caller's. 859 return NextStackOffset <= FI.getIncomingArgSize(); 860} 861 862void MipsSETargetLowering:: 863getOpndList(SmallVectorImpl<SDValue> &Ops, 864 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 865 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 866 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 867 // T9 should contain the address of the callee function if 868 // -reloction-model=pic or it is an indirect call. 869 if (IsPICCall || !GlobalOrExternal) { 870 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 871 RegsToPass.push_front(std::make_pair(T9Reg, Callee)); 872 } else 873 Ops.push_back(Callee); 874 875 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 876 InternalLinkage, CLI, Callee, Chain); 877} 878 879SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 880 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 881 882 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 883 return MipsTargetLowering::lowerLOAD(Op, DAG); 884 885 // Replace a double precision load with two i32 loads and a buildpair64. 886 SDLoc DL(Op); 887 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 888 EVT PtrVT = Ptr.getValueType(); 889 890 // i32 load from lower address. 891 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 892 MachinePointerInfo(), Nd.isVolatile(), 893 Nd.isNonTemporal(), Nd.isInvariant(), 894 Nd.getAlignment()); 895 896 // i32 load from higher address. 897 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 898 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 899 MachinePointerInfo(), Nd.isVolatile(), 900 Nd.isNonTemporal(), Nd.isInvariant(), 901 std::min(Nd.getAlignment(), 4U)); 902 903 if (!Subtarget->isLittle()) 904 std::swap(Lo, Hi); 905 906 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 907 SDValue Ops[2] = {BP, Hi.getValue(1)}; 908 return DAG.getMergeValues(Ops, 2, DL); 909} 910 911SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 912 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 913 914 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 915 return MipsTargetLowering::lowerSTORE(Op, DAG); 916 917 // Replace a double precision store with two extractelement64s and i32 stores. 918 SDLoc DL(Op); 919 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 920 EVT PtrVT = Ptr.getValueType(); 921 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 922 Val, DAG.getConstant(0, MVT::i32)); 923 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 924 Val, DAG.getConstant(1, MVT::i32)); 925 926 if (!Subtarget->isLittle()) 927 std::swap(Lo, Hi); 928 929 // i32 store to lower address. 930 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 931 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 932 Nd.getTBAAInfo()); 933 934 // i32 store to higher address. 935 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 936 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 937 Nd.isVolatile(), Nd.isNonTemporal(), 938 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); 939} 940 941SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 942 bool HasLo, bool HasHi, 943 SelectionDAG &DAG) const { 944 EVT Ty = Op.getOperand(0).getValueType(); 945 SDLoc DL(Op); 946 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 947 Op.getOperand(0), Op.getOperand(1)); 948 SDValue Lo, Hi; 949 950 if (HasLo) 951 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); 952 if (HasHi) 953 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); 954 955 if (!HasLo || !HasHi) 956 return HasLo ? Lo : Hi; 957 958 SDValue Vals[] = { Lo, Hi }; 959 return DAG.getMergeValues(Vals, 2, DL); 960} 961 962 963static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 964 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 965 DAG.getConstant(0, MVT::i32)); 966 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 967 DAG.getConstant(1, MVT::i32)); 968 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); 969} 970 971static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 972 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); 973 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); 974 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 975} 976 977// This function expands mips intrinsic nodes which have 64-bit input operands 978// or output values. 979// 980// out64 = intrinsic-node in64 981// => 982// lo = copy (extract-element (in64, 0)) 983// hi = copy (extract-element (in64, 1)) 984// mips-specific-node 985// v0 = copy lo 986// v1 = copy hi 987// out64 = merge-values (v0, v1) 988// 989static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 990 SDLoc DL(Op); 991 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 992 SmallVector<SDValue, 3> Ops; 993 unsigned OpNo = 0; 994 995 // See if Op has a chain input. 996 if (HasChainIn) 997 Ops.push_back(Op->getOperand(OpNo++)); 998 999 // The next operand is the intrinsic opcode. 1000 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1001 1002 // See if the next operand has type i64. 1003 SDValue Opnd = Op->getOperand(++OpNo), In64; 1004 1005 if (Opnd.getValueType() == MVT::i64) 1006 In64 = initAccumulator(Opnd, DL, DAG); 1007 else 1008 Ops.push_back(Opnd); 1009 1010 // Push the remaining operands. 1011 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1012 Ops.push_back(Op->getOperand(OpNo)); 1013 1014 // Add In64 to the end of the list. 1015 if (In64.getNode()) 1016 Ops.push_back(In64); 1017 1018 // Scan output. 1019 SmallVector<EVT, 2> ResTys; 1020 1021 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1022 I != E; ++I) 1023 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1024 1025 // Create node. 1026 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); 1027 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1028 1029 if (!HasChainIn) 1030 return Out; 1031 1032 assert(Val->getValueType(1) == MVT::Other); 1033 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1034 return DAG.getMergeValues(Vals, 2, DL); 1035} 1036 1037// Lower an MSA copy intrinsic into the specified SelectionDAG node 1038static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1039 SDLoc DL(Op); 1040 SDValue Vec = Op->getOperand(1); 1041 SDValue Idx = Op->getOperand(2); 1042 EVT ResTy = Op->getValueType(0); 1043 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1044 1045 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1046 DAG.getValueType(EltTy)); 1047 1048 return Result; 1049} 1050 1051static SDValue 1052lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) { 1053 EVT ViaVecTy = ResTy; 1054 SmallVector<SDValue, 16> Ops; 1055 SDValue ImmHiOp; 1056 1057 if (ViaVecTy == MVT::v2i64) { 1058 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp, 1059 DAG.getConstant(31, MVT::i32)); 1060 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) { 1061 Ops.push_back(ImmHiOp); 1062 Ops.push_back(ImmOp); 1063 } 1064 ViaVecTy = MVT::v4i32; 1065 } else { 1066 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1067 Ops.push_back(ImmOp); 1068 } 1069 1070 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0], 1071 Ops.size()); 1072 1073 if (ResTy != ViaVecTy) 1074 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result); 1075 1076 return Result; 1077} 1078 1079static SDValue 1080lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1081 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0), 1082 Op->getOperand(ImmOp), DAG); 1083} 1084 1085SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1086 SelectionDAG &DAG) const { 1087 SDLoc DL(Op); 1088 1089 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1090 default: 1091 return SDValue(); 1092 case Intrinsic::mips_shilo: 1093 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1094 case Intrinsic::mips_dpau_h_qbl: 1095 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1096 case Intrinsic::mips_dpau_h_qbr: 1097 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1098 case Intrinsic::mips_dpsu_h_qbl: 1099 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1100 case Intrinsic::mips_dpsu_h_qbr: 1101 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1102 case Intrinsic::mips_dpa_w_ph: 1103 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1104 case Intrinsic::mips_dps_w_ph: 1105 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1106 case Intrinsic::mips_dpax_w_ph: 1107 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1108 case Intrinsic::mips_dpsx_w_ph: 1109 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1110 case Intrinsic::mips_mulsa_w_ph: 1111 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1112 case Intrinsic::mips_mult: 1113 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1114 case Intrinsic::mips_multu: 1115 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1116 case Intrinsic::mips_madd: 1117 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1118 case Intrinsic::mips_maddu: 1119 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1120 case Intrinsic::mips_msub: 1121 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1122 case Intrinsic::mips_msubu: 1123 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1124 case Intrinsic::mips_addv_b: 1125 case Intrinsic::mips_addv_h: 1126 case Intrinsic::mips_addv_w: 1127 case Intrinsic::mips_addv_d: 1128 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1129 Op->getOperand(2)); 1130 case Intrinsic::mips_addvi_b: 1131 case Intrinsic::mips_addvi_h: 1132 case Intrinsic::mips_addvi_w: 1133 case Intrinsic::mips_addvi_d: 1134 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1135 lowerMSASplatImm(Op, 2, DAG)); 1136 case Intrinsic::mips_and_v: 1137 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1138 Op->getOperand(2)); 1139 case Intrinsic::mips_andi_b: 1140 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1141 lowerMSASplatImm(Op, 2, DAG)); 1142 case Intrinsic::mips_bnz_b: 1143 case Intrinsic::mips_bnz_h: 1144 case Intrinsic::mips_bnz_w: 1145 case Intrinsic::mips_bnz_d: 1146 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1147 Op->getOperand(1)); 1148 case Intrinsic::mips_bnz_v: 1149 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1150 Op->getOperand(1)); 1151 case Intrinsic::mips_bsel_v: 1152 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1153 Op->getOperand(1), Op->getOperand(2), 1154 Op->getOperand(3)); 1155 case Intrinsic::mips_bseli_b: 1156 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1157 Op->getOperand(1), Op->getOperand(2), 1158 lowerMSASplatImm(Op, 3, DAG)); 1159 case Intrinsic::mips_bz_b: 1160 case Intrinsic::mips_bz_h: 1161 case Intrinsic::mips_bz_w: 1162 case Intrinsic::mips_bz_d: 1163 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1164 Op->getOperand(1)); 1165 case Intrinsic::mips_bz_v: 1166 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1167 Op->getOperand(1)); 1168 case Intrinsic::mips_ceq_b: 1169 case Intrinsic::mips_ceq_h: 1170 case Intrinsic::mips_ceq_w: 1171 case Intrinsic::mips_ceq_d: 1172 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1173 Op->getOperand(2), ISD::SETEQ); 1174 case Intrinsic::mips_ceqi_b: 1175 case Intrinsic::mips_ceqi_h: 1176 case Intrinsic::mips_ceqi_w: 1177 case Intrinsic::mips_ceqi_d: 1178 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1179 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1180 case Intrinsic::mips_cle_s_b: 1181 case Intrinsic::mips_cle_s_h: 1182 case Intrinsic::mips_cle_s_w: 1183 case Intrinsic::mips_cle_s_d: 1184 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1185 Op->getOperand(2), ISD::SETLE); 1186 case Intrinsic::mips_clei_s_b: 1187 case Intrinsic::mips_clei_s_h: 1188 case Intrinsic::mips_clei_s_w: 1189 case Intrinsic::mips_clei_s_d: 1190 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1191 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1192 case Intrinsic::mips_cle_u_b: 1193 case Intrinsic::mips_cle_u_h: 1194 case Intrinsic::mips_cle_u_w: 1195 case Intrinsic::mips_cle_u_d: 1196 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1197 Op->getOperand(2), ISD::SETULE); 1198 case Intrinsic::mips_clei_u_b: 1199 case Intrinsic::mips_clei_u_h: 1200 case Intrinsic::mips_clei_u_w: 1201 case Intrinsic::mips_clei_u_d: 1202 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1203 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1204 case Intrinsic::mips_clt_s_b: 1205 case Intrinsic::mips_clt_s_h: 1206 case Intrinsic::mips_clt_s_w: 1207 case Intrinsic::mips_clt_s_d: 1208 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1209 Op->getOperand(2), ISD::SETLT); 1210 case Intrinsic::mips_clti_s_b: 1211 case Intrinsic::mips_clti_s_h: 1212 case Intrinsic::mips_clti_s_w: 1213 case Intrinsic::mips_clti_s_d: 1214 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1215 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1216 case Intrinsic::mips_clt_u_b: 1217 case Intrinsic::mips_clt_u_h: 1218 case Intrinsic::mips_clt_u_w: 1219 case Intrinsic::mips_clt_u_d: 1220 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1221 Op->getOperand(2), ISD::SETULT); 1222 case Intrinsic::mips_clti_u_b: 1223 case Intrinsic::mips_clti_u_h: 1224 case Intrinsic::mips_clti_u_w: 1225 case Intrinsic::mips_clti_u_d: 1226 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1227 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1228 case Intrinsic::mips_copy_s_b: 1229 case Intrinsic::mips_copy_s_h: 1230 case Intrinsic::mips_copy_s_w: 1231 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1232 case Intrinsic::mips_copy_s_d: 1233 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal. 1234 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1235 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1236 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1237 Op->getOperand(1), Op->getOperand(2)); 1238 case Intrinsic::mips_copy_u_b: 1239 case Intrinsic::mips_copy_u_h: 1240 case Intrinsic::mips_copy_u_w: 1241 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1242 case Intrinsic::mips_copy_u_d: 1243 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal. 1244 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1245 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1246 // 1247 // Note: When i64 is illegal, this results in copy_s.w instructions instead 1248 // of copy_u.w instructions. This makes no difference to the behaviour 1249 // since i64 is only illegal when the register file is 32-bit. 1250 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1251 Op->getOperand(1), Op->getOperand(2)); 1252 case Intrinsic::mips_div_s_b: 1253 case Intrinsic::mips_div_s_h: 1254 case Intrinsic::mips_div_s_w: 1255 case Intrinsic::mips_div_s_d: 1256 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1257 Op->getOperand(2)); 1258 case Intrinsic::mips_div_u_b: 1259 case Intrinsic::mips_div_u_h: 1260 case Intrinsic::mips_div_u_w: 1261 case Intrinsic::mips_div_u_d: 1262 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1263 Op->getOperand(2)); 1264 case Intrinsic::mips_fadd_w: 1265 case Intrinsic::mips_fadd_d: 1266 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1267 Op->getOperand(2)); 1268 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1269 case Intrinsic::mips_fceq_w: 1270 case Intrinsic::mips_fceq_d: 1271 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1272 Op->getOperand(2), ISD::SETOEQ); 1273 case Intrinsic::mips_fcle_w: 1274 case Intrinsic::mips_fcle_d: 1275 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1276 Op->getOperand(2), ISD::SETOLE); 1277 case Intrinsic::mips_fclt_w: 1278 case Intrinsic::mips_fclt_d: 1279 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1280 Op->getOperand(2), ISD::SETOLT); 1281 case Intrinsic::mips_fcne_w: 1282 case Intrinsic::mips_fcne_d: 1283 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1284 Op->getOperand(2), ISD::SETONE); 1285 case Intrinsic::mips_fcor_w: 1286 case Intrinsic::mips_fcor_d: 1287 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1288 Op->getOperand(2), ISD::SETO); 1289 case Intrinsic::mips_fcueq_w: 1290 case Intrinsic::mips_fcueq_d: 1291 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1292 Op->getOperand(2), ISD::SETUEQ); 1293 case Intrinsic::mips_fcule_w: 1294 case Intrinsic::mips_fcule_d: 1295 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1296 Op->getOperand(2), ISD::SETULE); 1297 case Intrinsic::mips_fcult_w: 1298 case Intrinsic::mips_fcult_d: 1299 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1300 Op->getOperand(2), ISD::SETULT); 1301 case Intrinsic::mips_fcun_w: 1302 case Intrinsic::mips_fcun_d: 1303 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1304 Op->getOperand(2), ISD::SETUO); 1305 case Intrinsic::mips_fcune_w: 1306 case Intrinsic::mips_fcune_d: 1307 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1308 Op->getOperand(2), ISD::SETUNE); 1309 case Intrinsic::mips_fdiv_w: 1310 case Intrinsic::mips_fdiv_d: 1311 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1312 Op->getOperand(2)); 1313 case Intrinsic::mips_ffint_u_w: 1314 case Intrinsic::mips_ffint_u_d: 1315 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), 1316 Op->getOperand(1)); 1317 case Intrinsic::mips_ffint_s_w: 1318 case Intrinsic::mips_ffint_s_d: 1319 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), 1320 Op->getOperand(1)); 1321 case Intrinsic::mips_fill_b: 1322 case Intrinsic::mips_fill_h: 1323 case Intrinsic::mips_fill_w: 1324 case Intrinsic::mips_fill_d: { 1325 SmallVector<SDValue, 16> Ops; 1326 EVT ResTy = Op->getValueType(0); 1327 1328 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1329 Ops.push_back(Op->getOperand(1)); 1330 1331 // If ResTy is v2i64 then the type legalizer will break this node down into 1332 // an equivalent v4i32. 1333 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); 1334 } 1335 case Intrinsic::mips_flog2_w: 1336 case Intrinsic::mips_flog2_d: 1337 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1338 case Intrinsic::mips_fmadd_w: 1339 case Intrinsic::mips_fmadd_d: 1340 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), 1341 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1342 case Intrinsic::mips_fmul_w: 1343 case Intrinsic::mips_fmul_d: 1344 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1345 Op->getOperand(2)); 1346 case Intrinsic::mips_fmsub_w: 1347 case Intrinsic::mips_fmsub_d: { 1348 EVT ResTy = Op->getValueType(0); 1349 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1), 1350 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, 1351 Op->getOperand(2), Op->getOperand(3))); 1352 } 1353 case Intrinsic::mips_frint_w: 1354 case Intrinsic::mips_frint_d: 1355 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1356 case Intrinsic::mips_fsqrt_w: 1357 case Intrinsic::mips_fsqrt_d: 1358 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1359 case Intrinsic::mips_fsub_w: 1360 case Intrinsic::mips_fsub_d: 1361 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1362 Op->getOperand(2)); 1363 case Intrinsic::mips_ftrunc_u_w: 1364 case Intrinsic::mips_ftrunc_u_d: 1365 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), 1366 Op->getOperand(1)); 1367 case Intrinsic::mips_ftrunc_s_w: 1368 case Intrinsic::mips_ftrunc_s_d: 1369 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), 1370 Op->getOperand(1)); 1371 case Intrinsic::mips_ilvev_b: 1372 case Intrinsic::mips_ilvev_h: 1373 case Intrinsic::mips_ilvev_w: 1374 case Intrinsic::mips_ilvev_d: 1375 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1376 Op->getOperand(1), Op->getOperand(2)); 1377 case Intrinsic::mips_ilvl_b: 1378 case Intrinsic::mips_ilvl_h: 1379 case Intrinsic::mips_ilvl_w: 1380 case Intrinsic::mips_ilvl_d: 1381 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1382 Op->getOperand(1), Op->getOperand(2)); 1383 case Intrinsic::mips_ilvod_b: 1384 case Intrinsic::mips_ilvod_h: 1385 case Intrinsic::mips_ilvod_w: 1386 case Intrinsic::mips_ilvod_d: 1387 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1388 Op->getOperand(1), Op->getOperand(2)); 1389 case Intrinsic::mips_ilvr_b: 1390 case Intrinsic::mips_ilvr_h: 1391 case Intrinsic::mips_ilvr_w: 1392 case Intrinsic::mips_ilvr_d: 1393 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1394 Op->getOperand(1), Op->getOperand(2)); 1395 case Intrinsic::mips_insert_b: 1396 case Intrinsic::mips_insert_h: 1397 case Intrinsic::mips_insert_w: 1398 case Intrinsic::mips_insert_d: 1399 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1400 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1401 case Intrinsic::mips_ldi_b: 1402 case Intrinsic::mips_ldi_h: 1403 case Intrinsic::mips_ldi_w: 1404 case Intrinsic::mips_ldi_d: 1405 return lowerMSASplatImm(Op, 1, DAG); 1406 case Intrinsic::mips_lsa: { 1407 EVT ResTy = Op->getValueType(0); 1408 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1409 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, 1410 Op->getOperand(2), Op->getOperand(3))); 1411 } 1412 case Intrinsic::mips_maddv_b: 1413 case Intrinsic::mips_maddv_h: 1414 case Intrinsic::mips_maddv_w: 1415 case Intrinsic::mips_maddv_d: { 1416 EVT ResTy = Op->getValueType(0); 1417 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1418 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1419 Op->getOperand(2), Op->getOperand(3))); 1420 } 1421 case Intrinsic::mips_max_s_b: 1422 case Intrinsic::mips_max_s_h: 1423 case Intrinsic::mips_max_s_w: 1424 case Intrinsic::mips_max_s_d: 1425 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1426 Op->getOperand(1), Op->getOperand(2)); 1427 case Intrinsic::mips_max_u_b: 1428 case Intrinsic::mips_max_u_h: 1429 case Intrinsic::mips_max_u_w: 1430 case Intrinsic::mips_max_u_d: 1431 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1432 Op->getOperand(1), Op->getOperand(2)); 1433 case Intrinsic::mips_maxi_s_b: 1434 case Intrinsic::mips_maxi_s_h: 1435 case Intrinsic::mips_maxi_s_w: 1436 case Intrinsic::mips_maxi_s_d: 1437 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1438 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1439 case Intrinsic::mips_maxi_u_b: 1440 case Intrinsic::mips_maxi_u_h: 1441 case Intrinsic::mips_maxi_u_w: 1442 case Intrinsic::mips_maxi_u_d: 1443 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1444 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1445 case Intrinsic::mips_min_s_b: 1446 case Intrinsic::mips_min_s_h: 1447 case Intrinsic::mips_min_s_w: 1448 case Intrinsic::mips_min_s_d: 1449 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1450 Op->getOperand(1), Op->getOperand(2)); 1451 case Intrinsic::mips_min_u_b: 1452 case Intrinsic::mips_min_u_h: 1453 case Intrinsic::mips_min_u_w: 1454 case Intrinsic::mips_min_u_d: 1455 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1456 Op->getOperand(1), Op->getOperand(2)); 1457 case Intrinsic::mips_mini_s_b: 1458 case Intrinsic::mips_mini_s_h: 1459 case Intrinsic::mips_mini_s_w: 1460 case Intrinsic::mips_mini_s_d: 1461 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1462 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1463 case Intrinsic::mips_mini_u_b: 1464 case Intrinsic::mips_mini_u_h: 1465 case Intrinsic::mips_mini_u_w: 1466 case Intrinsic::mips_mini_u_d: 1467 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1468 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1469 case Intrinsic::mips_mod_s_b: 1470 case Intrinsic::mips_mod_s_h: 1471 case Intrinsic::mips_mod_s_w: 1472 case Intrinsic::mips_mod_s_d: 1473 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), 1474 Op->getOperand(2)); 1475 case Intrinsic::mips_mod_u_b: 1476 case Intrinsic::mips_mod_u_h: 1477 case Intrinsic::mips_mod_u_w: 1478 case Intrinsic::mips_mod_u_d: 1479 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), 1480 Op->getOperand(2)); 1481 case Intrinsic::mips_mulv_b: 1482 case Intrinsic::mips_mulv_h: 1483 case Intrinsic::mips_mulv_w: 1484 case Intrinsic::mips_mulv_d: 1485 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 1486 Op->getOperand(2)); 1487 case Intrinsic::mips_msubv_b: 1488 case Intrinsic::mips_msubv_h: 1489 case Intrinsic::mips_msubv_w: 1490 case Intrinsic::mips_msubv_d: { 1491 EVT ResTy = Op->getValueType(0); 1492 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), 1493 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1494 Op->getOperand(2), Op->getOperand(3))); 1495 } 1496 case Intrinsic::mips_nlzc_b: 1497 case Intrinsic::mips_nlzc_h: 1498 case Intrinsic::mips_nlzc_w: 1499 case Intrinsic::mips_nlzc_d: 1500 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 1501 case Intrinsic::mips_nor_v: { 1502 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1503 Op->getOperand(1), Op->getOperand(2)); 1504 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1505 } 1506 case Intrinsic::mips_nori_b: { 1507 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1508 Op->getOperand(1), 1509 lowerMSASplatImm(Op, 2, DAG)); 1510 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1511 } 1512 case Intrinsic::mips_or_v: 1513 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 1514 Op->getOperand(2)); 1515 case Intrinsic::mips_ori_b: 1516 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1517 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1518 case Intrinsic::mips_pckev_b: 1519 case Intrinsic::mips_pckev_h: 1520 case Intrinsic::mips_pckev_w: 1521 case Intrinsic::mips_pckev_d: 1522 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 1523 Op->getOperand(1), Op->getOperand(2)); 1524 case Intrinsic::mips_pckod_b: 1525 case Intrinsic::mips_pckod_h: 1526 case Intrinsic::mips_pckod_w: 1527 case Intrinsic::mips_pckod_d: 1528 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 1529 Op->getOperand(1), Op->getOperand(2)); 1530 case Intrinsic::mips_pcnt_b: 1531 case Intrinsic::mips_pcnt_h: 1532 case Intrinsic::mips_pcnt_w: 1533 case Intrinsic::mips_pcnt_d: 1534 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 1535 case Intrinsic::mips_shf_b: 1536 case Intrinsic::mips_shf_h: 1537 case Intrinsic::mips_shf_w: 1538 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 1539 Op->getOperand(2), Op->getOperand(1)); 1540 case Intrinsic::mips_sll_b: 1541 case Intrinsic::mips_sll_h: 1542 case Intrinsic::mips_sll_w: 1543 case Intrinsic::mips_sll_d: 1544 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 1545 Op->getOperand(2)); 1546 case Intrinsic::mips_slli_b: 1547 case Intrinsic::mips_slli_h: 1548 case Intrinsic::mips_slli_w: 1549 case Intrinsic::mips_slli_d: 1550 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 1551 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1552 case Intrinsic::mips_splati_b: 1553 case Intrinsic::mips_splati_h: 1554 case Intrinsic::mips_splati_w: 1555 case Intrinsic::mips_splati_d: 1556 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1557 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1558 Op->getOperand(1)); 1559 case Intrinsic::mips_sra_b: 1560 case Intrinsic::mips_sra_h: 1561 case Intrinsic::mips_sra_w: 1562 case Intrinsic::mips_sra_d: 1563 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 1564 Op->getOperand(2)); 1565 case Intrinsic::mips_srai_b: 1566 case Intrinsic::mips_srai_h: 1567 case Intrinsic::mips_srai_w: 1568 case Intrinsic::mips_srai_d: 1569 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 1570 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1571 case Intrinsic::mips_srl_b: 1572 case Intrinsic::mips_srl_h: 1573 case Intrinsic::mips_srl_w: 1574 case Intrinsic::mips_srl_d: 1575 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 1576 Op->getOperand(2)); 1577 case Intrinsic::mips_srli_b: 1578 case Intrinsic::mips_srli_h: 1579 case Intrinsic::mips_srli_w: 1580 case Intrinsic::mips_srli_d: 1581 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 1582 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1583 case Intrinsic::mips_subv_b: 1584 case Intrinsic::mips_subv_h: 1585 case Intrinsic::mips_subv_w: 1586 case Intrinsic::mips_subv_d: 1587 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 1588 Op->getOperand(2)); 1589 case Intrinsic::mips_subvi_b: 1590 case Intrinsic::mips_subvi_h: 1591 case Intrinsic::mips_subvi_w: 1592 case Intrinsic::mips_subvi_d: 1593 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 1594 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1595 case Intrinsic::mips_vshf_b: 1596 case Intrinsic::mips_vshf_h: 1597 case Intrinsic::mips_vshf_w: 1598 case Intrinsic::mips_vshf_d: 1599 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1600 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1601 case Intrinsic::mips_xor_v: 1602 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 1603 Op->getOperand(2)); 1604 case Intrinsic::mips_xori_b: 1605 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 1606 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1607 } 1608} 1609 1610static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1611 SDLoc DL(Op); 1612 SDValue ChainIn = Op->getOperand(0); 1613 SDValue Address = Op->getOperand(2); 1614 SDValue Offset = Op->getOperand(3); 1615 EVT ResTy = Op->getValueType(0); 1616 EVT PtrTy = Address->getValueType(0); 1617 1618 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1619 1620 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 1621 false, false, 16); 1622} 1623 1624SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 1625 SelectionDAG &DAG) const { 1626 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1627 switch (Intr) { 1628 default: 1629 return SDValue(); 1630 case Intrinsic::mips_extp: 1631 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 1632 case Intrinsic::mips_extpdp: 1633 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 1634 case Intrinsic::mips_extr_w: 1635 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 1636 case Intrinsic::mips_extr_r_w: 1637 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 1638 case Intrinsic::mips_extr_rs_w: 1639 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 1640 case Intrinsic::mips_extr_s_h: 1641 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 1642 case Intrinsic::mips_mthlip: 1643 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 1644 case Intrinsic::mips_mulsaq_s_w_ph: 1645 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 1646 case Intrinsic::mips_maq_s_w_phl: 1647 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 1648 case Intrinsic::mips_maq_s_w_phr: 1649 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 1650 case Intrinsic::mips_maq_sa_w_phl: 1651 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 1652 case Intrinsic::mips_maq_sa_w_phr: 1653 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 1654 case Intrinsic::mips_dpaq_s_w_ph: 1655 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 1656 case Intrinsic::mips_dpsq_s_w_ph: 1657 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 1658 case Intrinsic::mips_dpaq_sa_l_w: 1659 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 1660 case Intrinsic::mips_dpsq_sa_l_w: 1661 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 1662 case Intrinsic::mips_dpaqx_s_w_ph: 1663 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 1664 case Intrinsic::mips_dpaqx_sa_w_ph: 1665 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 1666 case Intrinsic::mips_dpsqx_s_w_ph: 1667 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 1668 case Intrinsic::mips_dpsqx_sa_w_ph: 1669 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 1670 case Intrinsic::mips_ld_b: 1671 case Intrinsic::mips_ld_h: 1672 case Intrinsic::mips_ld_w: 1673 case Intrinsic::mips_ld_d: 1674 return lowerMSALoadIntr(Op, DAG, Intr); 1675 } 1676} 1677 1678static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1679 SDLoc DL(Op); 1680 SDValue ChainIn = Op->getOperand(0); 1681 SDValue Value = Op->getOperand(2); 1682 SDValue Address = Op->getOperand(3); 1683 SDValue Offset = Op->getOperand(4); 1684 EVT PtrTy = Address->getValueType(0); 1685 1686 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1687 1688 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 1689 false, 16); 1690} 1691 1692SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 1693 SelectionDAG &DAG) const { 1694 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1695 switch (Intr) { 1696 default: 1697 return SDValue(); 1698 case Intrinsic::mips_st_b: 1699 case Intrinsic::mips_st_h: 1700 case Intrinsic::mips_st_w: 1701 case Intrinsic::mips_st_d: 1702 return lowerMSAStoreIntr(Op, DAG, Intr); 1703 } 1704} 1705 1706/// \brief Check if the given BuildVectorSDNode is a splat. 1707/// This method currently relies on DAG nodes being reused when equivalent, 1708/// so it's possible for this to return false even when isConstantSplat returns 1709/// true. 1710static bool isSplatVector(const BuildVectorSDNode *N) { 1711 unsigned int nOps = N->getNumOperands(); 1712 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector"); 1713 1714 SDValue Operand0 = N->getOperand(0); 1715 1716 for (unsigned int i = 1; i < nOps; ++i) { 1717 if (N->getOperand(i) != Operand0) 1718 return false; 1719 } 1720 1721 return true; 1722} 1723 1724// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 1725// 1726// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 1727// choose to sign-extend but we could have equally chosen zero-extend. The 1728// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 1729// result into this node later (possibly changing it to a zero-extend in the 1730// process). 1731SDValue MipsSETargetLowering:: 1732lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 1733 SDLoc DL(Op); 1734 EVT ResTy = Op->getValueType(0); 1735 SDValue Op0 = Op->getOperand(0); 1736 EVT VecTy = Op0->getValueType(0); 1737 1738 if (!VecTy.is128BitVector()) 1739 return SDValue(); 1740 1741 if (ResTy.isInteger()) { 1742 SDValue Op1 = Op->getOperand(1); 1743 EVT EltTy = VecTy.getVectorElementType(); 1744 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 1745 DAG.getValueType(EltTy)); 1746 } 1747 1748 return Op; 1749} 1750 1751static bool isConstantOrUndef(const SDValue Op) { 1752 if (Op->getOpcode() == ISD::UNDEF) 1753 return true; 1754 if (dyn_cast<ConstantSDNode>(Op)) 1755 return true; 1756 if (dyn_cast<ConstantFPSDNode>(Op)) 1757 return true; 1758 return false; 1759} 1760 1761static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 1762 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 1763 if (isConstantOrUndef(Op->getOperand(i))) 1764 return true; 1765 return false; 1766} 1767 1768// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 1769// backend. 1770// 1771// Lowers according to the following rules: 1772// - Constant splats are legal as-is as long as the SplatBitSize is a power of 1773// 2 less than or equal to 64 and the value fits into a signed 10-bit 1774// immediate 1775// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 1776// is a power of 2 less than or equal to 64 and the value does not fit into a 1777// signed 10-bit immediate 1778// - Non-constant splats are legal as-is. 1779// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 1780// - All others are illegal and must be expanded. 1781SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 1782 SelectionDAG &DAG) const { 1783 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 1784 EVT ResTy = Op->getValueType(0); 1785 SDLoc DL(Op); 1786 APInt SplatValue, SplatUndef; 1787 unsigned SplatBitSize; 1788 bool HasAnyUndefs; 1789 1790 if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) 1791 return SDValue(); 1792 1793 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 1794 HasAnyUndefs, 8, 1795 !Subtarget->isLittle()) && SplatBitSize <= 64) { 1796 // We can only cope with 8, 16, 32, or 64-bit elements 1797 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 1798 SplatBitSize != 64) 1799 return SDValue(); 1800 1801 // If the value fits into a simm10 then we can use ldi.[bhwd] 1802 if (SplatValue.isSignedIntN(10)) 1803 return Op; 1804 1805 EVT ViaVecTy; 1806 1807 switch (SplatBitSize) { 1808 default: 1809 return SDValue(); 1810 case 8: 1811 ViaVecTy = MVT::v16i8; 1812 break; 1813 case 16: 1814 ViaVecTy = MVT::v8i16; 1815 break; 1816 case 32: 1817 ViaVecTy = MVT::v4i32; 1818 break; 1819 case 64: 1820 // There's no fill.d to fall back on for 64-bit values 1821 return SDValue(); 1822 } 1823 1824 SmallVector<SDValue, 16> Ops; 1825 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32); 1826 1827 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) 1828 Ops.push_back(Constant); 1829 1830 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy, 1831 &Ops[0], Ops.size()); 1832 1833 if (ViaVecTy != ResTy) 1834 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 1835 1836 return Result; 1837 } else if (isSplatVector(Node)) 1838 return Op; 1839 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 1840 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 1841 // The resulting code is the same length as the expansion, but it doesn't 1842 // use memory operations 1843 EVT ResTy = Node->getValueType(0); 1844 1845 assert(ResTy.isVector()); 1846 1847 unsigned NumElts = ResTy.getVectorNumElements(); 1848 SDValue Vector = DAG.getUNDEF(ResTy); 1849 for (unsigned i = 0; i < NumElts; ++i) { 1850 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 1851 Node->getOperand(i), 1852 DAG.getConstant(i, MVT::i32)); 1853 } 1854 return Vector; 1855 } 1856 1857 return SDValue(); 1858} 1859 1860// Lower VECTOR_SHUFFLE into SHF (if possible). 1861// 1862// SHF splits the vector into blocks of four elements, then shuffles these 1863// elements according to a <4 x i2> constant (encoded as an integer immediate). 1864// 1865// It is therefore possible to lower into SHF when the mask takes the form: 1866// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 1867// When undef's appear they are treated as if they were whatever value is 1868// necessary in order to fit the above form. 1869// 1870// For example: 1871// %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 1872// <8 x i32> <i32 3, i32 2, i32 1, i32 0, 1873// i32 7, i32 6, i32 5, i32 4> 1874// is lowered to: 1875// (SHF_H $w0, $w1, 27) 1876// where the 27 comes from: 1877// 3 + (2 << 2) + (1 << 4) + (0 << 6) 1878static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 1879 SmallVector<int, 16> Indices, 1880 SelectionDAG &DAG) { 1881 int SHFIndices[4] = { -1, -1, -1, -1 }; 1882 1883 if (Indices.size() < 4) 1884 return SDValue(); 1885 1886 for (unsigned i = 0; i < 4; ++i) { 1887 for (unsigned j = i; j < Indices.size(); j += 4) { 1888 int Idx = Indices[j]; 1889 1890 // Convert from vector index to 4-element subvector index 1891 // If an index refers to an element outside of the subvector then give up 1892 if (Idx != -1) { 1893 Idx -= 4 * (j / 4); 1894 if (Idx < 0 || Idx >= 4) 1895 return SDValue(); 1896 } 1897 1898 // If the mask has an undef, replace it with the current index. 1899 // Note that it might still be undef if the current index is also undef 1900 if (SHFIndices[i] == -1) 1901 SHFIndices[i] = Idx; 1902 1903 // Check that non-undef values are the same as in the mask. If they 1904 // aren't then give up 1905 if (!(Idx == -1 || Idx == SHFIndices[i])) 1906 return SDValue(); 1907 } 1908 } 1909 1910 // Calculate the immediate. Replace any remaining undefs with zero 1911 APInt Imm(32, 0); 1912 for (int i = 3; i >= 0; --i) { 1913 int Idx = SHFIndices[i]; 1914 1915 if (Idx == -1) 1916 Idx = 0; 1917 1918 Imm <<= 2; 1919 Imm |= Idx & 0x3; 1920 } 1921 1922 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 1923 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 1924} 1925 1926// Lower VECTOR_SHUFFLE into ILVEV (if possible). 1927// 1928// ILVEV interleaves the even elements from each vector. 1929// 1930// It is possible to lower into ILVEV when the mask takes the form: 1931// <0, n, 2, n+2, 4, n+4, ...> 1932// where n is the number of elements in the vector. 1933// 1934// When undef's appear in the mask they are treated as if they were whatever 1935// value is necessary in order to fit the above form. 1936static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 1937 SmallVector<int, 16> Indices, 1938 SelectionDAG &DAG) { 1939 assert ((Indices.size() % 2) == 0); 1940 int WsIdx = 0; 1941 int WtIdx = ResTy.getVectorNumElements(); 1942 1943 for (unsigned i = 0; i < Indices.size(); i += 2) { 1944 if (Indices[i] != -1 && Indices[i] != WsIdx) 1945 return SDValue(); 1946 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1947 return SDValue(); 1948 WsIdx += 2; 1949 WtIdx += 2; 1950 } 1951 1952 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 1953 Op->getOperand(1)); 1954} 1955 1956// Lower VECTOR_SHUFFLE into ILVOD (if possible). 1957// 1958// ILVOD interleaves the odd elements from each vector. 1959// 1960// It is possible to lower into ILVOD when the mask takes the form: 1961// <1, n+1, 3, n+3, 5, n+5, ...> 1962// where n is the number of elements in the vector. 1963// 1964// When undef's appear in the mask they are treated as if they were whatever 1965// value is necessary in order to fit the above form. 1966static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 1967 SmallVector<int, 16> Indices, 1968 SelectionDAG &DAG) { 1969 assert ((Indices.size() % 2) == 0); 1970 int WsIdx = 1; 1971 int WtIdx = ResTy.getVectorNumElements() + 1; 1972 1973 for (unsigned i = 0; i < Indices.size(); i += 2) { 1974 if (Indices[i] != -1 && Indices[i] != WsIdx) 1975 return SDValue(); 1976 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1977 return SDValue(); 1978 WsIdx += 2; 1979 WtIdx += 2; 1980 } 1981 1982 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 1983 Op->getOperand(1)); 1984} 1985 1986// Lower VECTOR_SHUFFLE into ILVL (if possible). 1987// 1988// ILVL interleaves consecutive elements from the left half of each vector. 1989// 1990// It is possible to lower into ILVL when the mask takes the form: 1991// <0, n, 1, n+1, 2, n+2, ...> 1992// where n is the number of elements in the vector. 1993// 1994// When undef's appear in the mask they are treated as if they were whatever 1995// value is necessary in order to fit the above form. 1996static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 1997 SmallVector<int, 16> Indices, 1998 SelectionDAG &DAG) { 1999 assert ((Indices.size() % 2) == 0); 2000 int WsIdx = 0; 2001 int WtIdx = ResTy.getVectorNumElements(); 2002 2003 for (unsigned i = 0; i < Indices.size(); i += 2) { 2004 if (Indices[i] != -1 && Indices[i] != WsIdx) 2005 return SDValue(); 2006 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2007 return SDValue(); 2008 WsIdx ++; 2009 WtIdx ++; 2010 } 2011 2012 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 2013 Op->getOperand(1)); 2014} 2015 2016// Lower VECTOR_SHUFFLE into ILVR (if possible). 2017// 2018// ILVR interleaves consecutive elements from the right half of each vector. 2019// 2020// It is possible to lower into ILVR when the mask takes the form: 2021// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 2022// where n is the number of elements in the vector and x is half n. 2023// 2024// When undef's appear in the mask they are treated as if they were whatever 2025// value is necessary in order to fit the above form. 2026static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 2027 SmallVector<int, 16> Indices, 2028 SelectionDAG &DAG) { 2029 assert ((Indices.size() % 2) == 0); 2030 unsigned NumElts = ResTy.getVectorNumElements(); 2031 int WsIdx = NumElts / 2; 2032 int WtIdx = NumElts + NumElts / 2; 2033 2034 for (unsigned i = 0; i < Indices.size(); i += 2) { 2035 if (Indices[i] != -1 && Indices[i] != WsIdx) 2036 return SDValue(); 2037 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2038 return SDValue(); 2039 WsIdx ++; 2040 WtIdx ++; 2041 } 2042 2043 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 2044 Op->getOperand(1)); 2045} 2046 2047// Lower VECTOR_SHUFFLE into PCKEV (if possible). 2048// 2049// PCKEV copies the even elements of each vector into the result vector. 2050// 2051// It is possible to lower into PCKEV when the mask takes the form: 2052// <0, 2, 4, ..., n, n+2, n+4, ...> 2053// where n is the number of elements in the vector. 2054// 2055// When undef's appear in the mask they are treated as if they were whatever 2056// value is necessary in order to fit the above form. 2057static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2058 SmallVector<int, 16> Indices, 2059 SelectionDAG &DAG) { 2060 assert ((Indices.size() % 2) == 0); 2061 int Idx = 0; 2062 2063 for (unsigned i = 0; i < Indices.size(); ++i) { 2064 if (Indices[i] != -1 && Indices[i] != Idx) 2065 return SDValue(); 2066 Idx += 2; 2067 } 2068 2069 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2070 Op->getOperand(1)); 2071} 2072 2073// Lower VECTOR_SHUFFLE into PCKOD (if possible). 2074// 2075// PCKOD copies the odd elements of each vector into the result vector. 2076// 2077// It is possible to lower into PCKOD when the mask takes the form: 2078// <1, 3, 5, ..., n+1, n+3, n+5, ...> 2079// where n is the number of elements in the vector. 2080// 2081// When undef's appear in the mask they are treated as if they were whatever 2082// value is necessary in order to fit the above form. 2083static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2084 SmallVector<int, 16> Indices, 2085 SelectionDAG &DAG) { 2086 assert ((Indices.size() % 2) == 0); 2087 int Idx = 1; 2088 2089 for (unsigned i = 0; i < Indices.size(); ++i) { 2090 if (Indices[i] != -1 && Indices[i] != Idx) 2091 return SDValue(); 2092 Idx += 2; 2093 } 2094 2095 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2096 Op->getOperand(1)); 2097} 2098 2099// Lower VECTOR_SHUFFLE into VSHF. 2100// 2101// This mostly consists of converting the shuffle indices in Indices into a 2102// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2103// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2104// if the type is v8i16 and all the indices are less than 8 then the second 2105// operand is unused and can be replaced with anything. We choose to replace it 2106// with the used operand since this reduces the number of instructions overall. 2107static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2108 SmallVector<int, 16> Indices, 2109 SelectionDAG &DAG) { 2110 SmallVector<SDValue, 16> Ops; 2111 SDValue Op0; 2112 SDValue Op1; 2113 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2114 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2115 bool Using1stVec = false; 2116 bool Using2ndVec = false; 2117 SDLoc DL(Op); 2118 int ResTyNumElts = ResTy.getVectorNumElements(); 2119 2120 for (int i = 0; i < ResTyNumElts; ++i) { 2121 // Idx == -1 means UNDEF 2122 int Idx = Indices[i]; 2123 2124 if (0 <= Idx && Idx < ResTyNumElts) 2125 Using1stVec = true; 2126 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2127 Using2ndVec = true; 2128 } 2129 2130 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2131 ++I) 2132 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2133 2134 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0], 2135 Ops.size()); 2136 2137 if (Using1stVec && Using2ndVec) { 2138 Op0 = Op->getOperand(0); 2139 Op1 = Op->getOperand(1); 2140 } else if (Using1stVec) 2141 Op0 = Op1 = Op->getOperand(0); 2142 else if (Using2ndVec) 2143 Op0 = Op1 = Op->getOperand(1); 2144 else 2145 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2146 2147 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1); 2148} 2149 2150// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2151// indices in the shuffle. 2152SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2153 SelectionDAG &DAG) const { 2154 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2155 EVT ResTy = Op->getValueType(0); 2156 2157 if (!ResTy.is128BitVector()) 2158 return SDValue(); 2159 2160 int ResTyNumElts = ResTy.getVectorNumElements(); 2161 SmallVector<int, 16> Indices; 2162 2163 for (int i = 0; i < ResTyNumElts; ++i) 2164 Indices.push_back(Node->getMaskElt(i)); 2165 2166 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2167 if (Result.getNode()) 2168 return Result; 2169 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2170 if (Result.getNode()) 2171 return Result; 2172 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2173 if (Result.getNode()) 2174 return Result; 2175 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2176 if (Result.getNode()) 2177 return Result; 2178 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2179 if (Result.getNode()) 2180 return Result; 2181 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2182 if (Result.getNode()) 2183 return Result; 2184 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2185 if (Result.getNode()) 2186 return Result; 2187 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2188} 2189 2190MachineBasicBlock * MipsSETargetLowering:: 2191emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2192 // $bb: 2193 // bposge32_pseudo $vr0 2194 // => 2195 // $bb: 2196 // bposge32 $tbb 2197 // $fbb: 2198 // li $vr2, 0 2199 // b $sink 2200 // $tbb: 2201 // li $vr1, 1 2202 // $sink: 2203 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2204 2205 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2207 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2208 DebugLoc DL = MI->getDebugLoc(); 2209 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2210 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2211 MachineFunction *F = BB->getParent(); 2212 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2213 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2214 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2215 F->insert(It, FBB); 2216 F->insert(It, TBB); 2217 F->insert(It, Sink); 2218 2219 // Transfer the remainder of BB and its successor edges to Sink. 2220 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2221 BB->end()); 2222 Sink->transferSuccessorsAndUpdatePHIs(BB); 2223 2224 // Add successors. 2225 BB->addSuccessor(FBB); 2226 BB->addSuccessor(TBB); 2227 FBB->addSuccessor(Sink); 2228 TBB->addSuccessor(Sink); 2229 2230 // Insert the real bposge32 instruction to $BB. 2231 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2232 2233 // Fill $FBB. 2234 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2235 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2236 .addReg(Mips::ZERO).addImm(0); 2237 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2238 2239 // Fill $TBB. 2240 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2241 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2242 .addReg(Mips::ZERO).addImm(1); 2243 2244 // Insert phi function to $Sink. 2245 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2246 MI->getOperand(0).getReg()) 2247 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2248 2249 MI->eraseFromParent(); // The pseudo instruction is gone now. 2250 return Sink; 2251} 2252 2253MachineBasicBlock * MipsSETargetLowering:: 2254emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2255 unsigned BranchOp) const{ 2256 // $bb: 2257 // vany_nonzero $rd, $ws 2258 // => 2259 // $bb: 2260 // bnz.b $ws, $tbb 2261 // b $fbb 2262 // $fbb: 2263 // li $rd1, 0 2264 // b $sink 2265 // $tbb: 2266 // li $rd2, 1 2267 // $sink: 2268 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2269 2270 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2272 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2273 DebugLoc DL = MI->getDebugLoc(); 2274 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2275 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2276 MachineFunction *F = BB->getParent(); 2277 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2278 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2279 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2280 F->insert(It, FBB); 2281 F->insert(It, TBB); 2282 F->insert(It, Sink); 2283 2284 // Transfer the remainder of BB and its successor edges to Sink. 2285 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2286 BB->end()); 2287 Sink->transferSuccessorsAndUpdatePHIs(BB); 2288 2289 // Add successors. 2290 BB->addSuccessor(FBB); 2291 BB->addSuccessor(TBB); 2292 FBB->addSuccessor(Sink); 2293 TBB->addSuccessor(Sink); 2294 2295 // Insert the real bnz.b instruction to $BB. 2296 BuildMI(BB, DL, TII->get(BranchOp)) 2297 .addReg(MI->getOperand(1).getReg()) 2298 .addMBB(TBB); 2299 2300 // Fill $FBB. 2301 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2302 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2303 .addReg(Mips::ZERO).addImm(0); 2304 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2305 2306 // Fill $TBB. 2307 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2308 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2309 .addReg(Mips::ZERO).addImm(1); 2310 2311 // Insert phi function to $Sink. 2312 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2313 MI->getOperand(0).getReg()) 2314 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2315 2316 MI->eraseFromParent(); // The pseudo instruction is gone now. 2317 return Sink; 2318} 2319 2320// Emit the COPY_FW pseudo instruction. 2321// 2322// copy_fw_pseudo $fd, $ws, n 2323// => 2324// copy_u_w $rt, $ws, $n 2325// mtc1 $rt, $fd 2326// 2327// When n is zero, the equivalent operation can be performed with (potentially) 2328// zero instructions due to register overlaps. This optimization is never valid 2329// for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2330MachineBasicBlock * MipsSETargetLowering:: 2331emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2332 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2333 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2334 DebugLoc DL = MI->getDebugLoc(); 2335 unsigned Fd = MI->getOperand(0).getReg(); 2336 unsigned Ws = MI->getOperand(1).getReg(); 2337 unsigned Lane = MI->getOperand(2).getImm(); 2338 2339 if (Lane == 0) 2340 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2341 else { 2342 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2343 2344 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); 2345 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2346 } 2347 2348 MI->eraseFromParent(); // The pseudo instruction is gone now. 2349 return BB; 2350} 2351 2352// Emit the COPY_FD pseudo instruction. 2353// 2354// copy_fd_pseudo $fd, $ws, n 2355// => 2356// splati.d $wt, $ws, $n 2357// copy $fd, $wt:sub_64 2358// 2359// When n is zero, the equivalent operation can be performed with (potentially) 2360// zero instructions due to register overlaps. This optimization is always 2361// valid because FR=1 mode which is the only supported mode in MSA. 2362MachineBasicBlock * MipsSETargetLowering:: 2363emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2364 assert(Subtarget->isFP64bit()); 2365 2366 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2367 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2368 unsigned Fd = MI->getOperand(0).getReg(); 2369 unsigned Ws = MI->getOperand(1).getReg(); 2370 unsigned Lane = MI->getOperand(2).getImm() * 2; 2371 DebugLoc DL = MI->getDebugLoc(); 2372 2373 if (Lane == 0) 2374 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2375 else { 2376 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2377 2378 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2379 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2380 } 2381 2382 MI->eraseFromParent(); // The pseudo instruction is gone now. 2383 return BB; 2384} 2385 2386// Emit the INSERT_FW pseudo instruction. 2387// 2388// insert_fw_pseudo $wd, $wd_in, $n, $fs 2389// => 2390// subreg_to_reg $wt:sub_lo, $fs 2391// insve_w $wd[$n], $wd_in, $wt[0] 2392MachineBasicBlock * 2393MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, 2394 MachineBasicBlock *BB) const { 2395 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2396 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2397 DebugLoc DL = MI->getDebugLoc(); 2398 unsigned Wd = MI->getOperand(0).getReg(); 2399 unsigned Wd_in = MI->getOperand(1).getReg(); 2400 unsigned Lane = MI->getOperand(2).getImm(); 2401 unsigned Fs = MI->getOperand(3).getReg(); 2402 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2403 2404 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2405 .addImm(0) 2406 .addReg(Fs) 2407 .addImm(Mips::sub_lo); 2408 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2409 .addReg(Wd_in) 2410 .addImm(Lane) 2411 .addReg(Wt); 2412 2413 MI->eraseFromParent(); // The pseudo instruction is gone now. 2414 return BB; 2415} 2416 2417// Emit the INSERT_FD pseudo instruction. 2418// 2419// insert_fd_pseudo $wd, $fs, n 2420// => 2421// subreg_to_reg $wt:sub_64, $fs 2422// insve_d $wd[$n], $wd_in, $wt[0] 2423MachineBasicBlock * 2424MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, 2425 MachineBasicBlock *BB) const { 2426 assert(Subtarget->isFP64bit()); 2427 2428 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2429 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2430 DebugLoc DL = MI->getDebugLoc(); 2431 unsigned Wd = MI->getOperand(0).getReg(); 2432 unsigned Wd_in = MI->getOperand(1).getReg(); 2433 unsigned Lane = MI->getOperand(2).getImm(); 2434 unsigned Fs = MI->getOperand(3).getReg(); 2435 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2436 2437 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2438 .addImm(0) 2439 .addReg(Fs) 2440 .addImm(Mips::sub_64); 2441 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2442 .addReg(Wd_in) 2443 .addImm(Lane) 2444 .addReg(Wt); 2445 2446 MI->eraseFromParent(); // The pseudo instruction is gone now. 2447 return BB; 2448} 2449 2450// Emit the FILL_FW pseudo instruction. 2451// 2452// fill_fw_pseudo $wd, $fs 2453// => 2454// implicit_def $wt1 2455// insert_subreg $wt2:subreg_lo, $wt1, $fs 2456// splati.w $wd, $wt2[0] 2457MachineBasicBlock * 2458MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, 2459 MachineBasicBlock *BB) const { 2460 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2461 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2462 DebugLoc DL = MI->getDebugLoc(); 2463 unsigned Wd = MI->getOperand(0).getReg(); 2464 unsigned Fs = MI->getOperand(1).getReg(); 2465 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2466 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2467 2468 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2469 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2470 .addReg(Wt1) 2471 .addReg(Fs) 2472 .addImm(Mips::sub_lo); 2473 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); 2474 2475 MI->eraseFromParent(); // The pseudo instruction is gone now. 2476 return BB; 2477} 2478 2479// Emit the FILL_FD pseudo instruction. 2480// 2481// fill_fd_pseudo $wd, $fs 2482// => 2483// implicit_def $wt1 2484// insert_subreg $wt2:subreg_64, $wt1, $fs 2485// splati.d $wd, $wt2[0] 2486MachineBasicBlock * 2487MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, 2488 MachineBasicBlock *BB) const { 2489 assert(Subtarget->isFP64bit()); 2490 2491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2492 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2493 DebugLoc DL = MI->getDebugLoc(); 2494 unsigned Wd = MI->getOperand(0).getReg(); 2495 unsigned Fs = MI->getOperand(1).getReg(); 2496 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2497 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2498 2499 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2500 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2501 .addReg(Wt1) 2502 .addReg(Fs) 2503 .addImm(Mips::sub_64); 2504 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); 2505 2506 MI->eraseFromParent(); // The pseudo instruction is gone now. 2507 return BB; 2508} 2509