MipsSEISelLowering.cpp revision 7e287bfb58e63c4e1068e49e8e1b714f3b9703bc 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Support/CommandLine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21using namespace llvm;
22
23static cl::opt<bool>
24EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
25                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
26
27MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
28  : MipsTargetLowering(TM) {
29  // Set up the register classes
30  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
31
32  if (HasMips64)
33    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
34
35  if (Subtarget->hasDSP()) {
36    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
37
38    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
39      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
40
41      // Expand all builtin opcodes.
42      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
43        setOperationAction(Opc, VecTys[i], Expand);
44
45      setOperationAction(ISD::LOAD, VecTys[i], Legal);
46      setOperationAction(ISD::STORE, VecTys[i], Legal);
47      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
48    }
49  }
50
51  if (!TM.Options.UseSoftFloat) {
52    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
53
54    // When dealing with single precision only, use libcalls
55    if (!Subtarget->isSingleFloat()) {
56      if (HasMips64)
57        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
58      else
59        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
60    }
61  }
62
63  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
64  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
65  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
66  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
67
68  if (HasMips64)
69    setOperationAction(ISD::MUL,              MVT::i64, Custom);
70
71  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
72  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
73  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
74  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
75  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
76  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
77  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
78  setOperationAction(ISD::STORE,              MVT::i32, Custom);
79
80  setTargetDAGCombine(ISD::ADDE);
81  setTargetDAGCombine(ISD::SUBE);
82
83  computeRegisterProperties();
84}
85
86const MipsTargetLowering *
87llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
88  return new MipsSETargetLowering(TM);
89}
90
91
92bool
93MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
94  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
95
96  switch (SVT) {
97  case MVT::i64:
98  case MVT::i32:
99    if (Fast)
100      *Fast = true;
101    return true;
102  default:
103    return false;
104  }
105}
106
107SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
108                                             SelectionDAG &DAG) const {
109  switch(Op.getOpcode()) {
110  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
111  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
112  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
113  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
114  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
115  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
116  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
117  }
118
119  return MipsTargetLowering::LowerOperation(Op, DAG);
120}
121
122// selectMADD -
123// Transforms a subgraph in CurDAG if the following pattern is found:
124//  (addc multLo, Lo0), (adde multHi, Hi0),
125// where,
126//  multHi/Lo: product of multiplication
127//  Lo0: initial value of Lo register
128//  Hi0: initial value of Hi register
129// Return true if pattern matching was successful.
130static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
131  // ADDENode's second operand must be a flag output of an ADDC node in order
132  // for the matching to be successful.
133  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
134
135  if (ADDCNode->getOpcode() != ISD::ADDC)
136    return false;
137
138  SDValue MultHi = ADDENode->getOperand(0);
139  SDValue MultLo = ADDCNode->getOperand(0);
140  SDNode *MultNode = MultHi.getNode();
141  unsigned MultOpc = MultHi.getOpcode();
142
143  // MultHi and MultLo must be generated by the same node,
144  if (MultLo.getNode() != MultNode)
145    return false;
146
147  // and it must be a multiplication.
148  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
149    return false;
150
151  // MultLo amd MultHi must be the first and second output of MultNode
152  // respectively.
153  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
154    return false;
155
156  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
157  // of the values of MultNode, in which case MultNode will be removed in later
158  // phases.
159  // If there exist users other than ADDENode or ADDCNode, this function returns
160  // here, which will result in MultNode being mapped to a single MULT
161  // instruction node rather than a pair of MULT and MADD instructions being
162  // produced.
163  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
164    return false;
165
166  DebugLoc DL = ADDENode->getDebugLoc();
167
168  // Initialize accumulator.
169  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
170                                  ADDCNode->getOperand(1),
171                                  ADDENode->getOperand(1));
172
173  // create MipsMAdd(u) node
174  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
175
176  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
177                                 MultNode->getOperand(0),// Factor 0
178                                 MultNode->getOperand(1),// Factor 1
179                                 ACCIn);
180
181  // replace uses of adde and addc here
182  if (!SDValue(ADDCNode, 0).use_empty()) {
183    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
184    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
185                                    LoIdx);
186    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
187  }
188  if (!SDValue(ADDENode, 0).use_empty()) {
189    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
190    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
191                                    HiIdx);
192    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
193  }
194
195  return true;
196}
197
198// selectMSUB -
199// Transforms a subgraph in CurDAG if the following pattern is found:
200//  (addc Lo0, multLo), (sube Hi0, multHi),
201// where,
202//  multHi/Lo: product of multiplication
203//  Lo0: initial value of Lo register
204//  Hi0: initial value of Hi register
205// Return true if pattern matching was successful.
206static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
207  // SUBENode's second operand must be a flag output of an SUBC node in order
208  // for the matching to be successful.
209  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
210
211  if (SUBCNode->getOpcode() != ISD::SUBC)
212    return false;
213
214  SDValue MultHi = SUBENode->getOperand(1);
215  SDValue MultLo = SUBCNode->getOperand(1);
216  SDNode *MultNode = MultHi.getNode();
217  unsigned MultOpc = MultHi.getOpcode();
218
219  // MultHi and MultLo must be generated by the same node,
220  if (MultLo.getNode() != MultNode)
221    return false;
222
223  // and it must be a multiplication.
224  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
225    return false;
226
227  // MultLo amd MultHi must be the first and second output of MultNode
228  // respectively.
229  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
230    return false;
231
232  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
233  // of the values of MultNode, in which case MultNode will be removed in later
234  // phases.
235  // If there exist users other than SUBENode or SUBCNode, this function returns
236  // here, which will result in MultNode being mapped to a single MULT
237  // instruction node rather than a pair of MULT and MSUB instructions being
238  // produced.
239  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
240    return false;
241
242  DebugLoc DL = SUBENode->getDebugLoc();
243
244  // Initialize accumulator.
245  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
246                                  SUBCNode->getOperand(0),
247                                  SUBENode->getOperand(0));
248
249  // create MipsSub(u) node
250  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
251
252  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
253                                 MultNode->getOperand(0),// Factor 0
254                                 MultNode->getOperand(1),// Factor 1
255                                 ACCIn);
256
257  // replace uses of sube and subc here
258  if (!SDValue(SUBCNode, 0).use_empty()) {
259    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
260    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
261                                    LoIdx);
262    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
263  }
264  if (!SDValue(SUBENode, 0).use_empty()) {
265    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
266    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
267                                    HiIdx);
268    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
269  }
270
271  return true;
272}
273
274static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
275                                  TargetLowering::DAGCombinerInfo &DCI,
276                                  const MipsSubtarget *Subtarget) {
277  if (DCI.isBeforeLegalize())
278    return SDValue();
279
280  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
281      selectMADD(N, &DAG))
282    return SDValue(N, 0);
283
284  return SDValue();
285}
286
287static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
288                                  TargetLowering::DAGCombinerInfo &DCI,
289                                  const MipsSubtarget *Subtarget) {
290  if (DCI.isBeforeLegalize())
291    return SDValue();
292
293  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
294      selectMSUB(N, &DAG))
295    return SDValue(N, 0);
296
297  return SDValue();
298}
299
300SDValue
301MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
302  SelectionDAG &DAG = DCI.DAG;
303
304  switch (N->getOpcode()) {
305  case ISD::ADDE:
306    return performADDECombine(N, DAG, DCI, Subtarget);
307  case ISD::SUBE:
308    return performSUBECombine(N, DAG, DCI, Subtarget);
309  default:
310    return MipsTargetLowering::PerformDAGCombine(N, DCI);
311  }
312}
313
314MachineBasicBlock *
315MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
316                                                  MachineBasicBlock *BB) const {
317  switch (MI->getOpcode()) {
318  default:
319    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
320  case Mips::BPOSGE32_PSEUDO:
321    return emitBPOSGE32(MI, BB);
322  }
323}
324
325bool MipsSETargetLowering::
326isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
327                                  unsigned NextStackOffset,
328                                  const MipsFunctionInfo& FI) const {
329  if (!EnableMipsTailCalls)
330    return false;
331
332  // Return false if either the callee or caller has a byval argument.
333  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
334    return false;
335
336  // Return true if the callee's argument area is no larger than the
337  // caller's.
338  return NextStackOffset <= FI.getIncomingArgSize();
339}
340
341void MipsSETargetLowering::
342getOpndList(SmallVectorImpl<SDValue> &Ops,
343            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
344            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
345            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
346  // T9 should contain the address of the callee function if
347  // -reloction-model=pic or it is an indirect call.
348  if (IsPICCall || !GlobalOrExternal) {
349    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
350    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
351  } else
352    Ops.push_back(Callee);
353
354  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
355                                  InternalLinkage, CLI, Callee, Chain);
356}
357
358SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
359                                          bool HasLo, bool HasHi,
360                                          SelectionDAG &DAG) const {
361  EVT Ty = Op.getOperand(0).getValueType();
362  DebugLoc DL = Op.getDebugLoc();
363  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
364                             Op.getOperand(0), Op.getOperand(1));
365  SDValue Lo, Hi;
366
367  if (HasLo)
368    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
369                     DAG.getConstant(Mips::sub_lo, MVT::i32));
370  if (HasHi)
371    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
372                     DAG.getConstant(Mips::sub_hi, MVT::i32));
373
374  if (!HasLo || !HasHi)
375    return HasLo ? Lo : Hi;
376
377  SDValue Vals[] = { Lo, Hi };
378  return DAG.getMergeValues(Vals, 2, DL);
379}
380
381MachineBasicBlock * MipsSETargetLowering::
382emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
383  // $bb:
384  //  bposge32_pseudo $vr0
385  //  =>
386  // $bb:
387  //  bposge32 $tbb
388  // $fbb:
389  //  li $vr2, 0
390  //  b $sink
391  // $tbb:
392  //  li $vr1, 1
393  // $sink:
394  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
395
396  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
397  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
398  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
399  DebugLoc DL = MI->getDebugLoc();
400  const BasicBlock *LLVM_BB = BB->getBasicBlock();
401  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
402  MachineFunction *F = BB->getParent();
403  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
404  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
405  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
406  F->insert(It, FBB);
407  F->insert(It, TBB);
408  F->insert(It, Sink);
409
410  // Transfer the remainder of BB and its successor edges to Sink.
411  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
412               BB->end());
413  Sink->transferSuccessorsAndUpdatePHIs(BB);
414
415  // Add successors.
416  BB->addSuccessor(FBB);
417  BB->addSuccessor(TBB);
418  FBB->addSuccessor(Sink);
419  TBB->addSuccessor(Sink);
420
421  // Insert the real bposge32 instruction to $BB.
422  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
423
424  // Fill $FBB.
425  unsigned VR2 = RegInfo.createVirtualRegister(RC);
426  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
427    .addReg(Mips::ZERO).addImm(0);
428  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
429
430  // Fill $TBB.
431  unsigned VR1 = RegInfo.createVirtualRegister(RC);
432  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
433    .addReg(Mips::ZERO).addImm(1);
434
435  // Insert phi function to $Sink.
436  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
437          MI->getOperand(0).getReg())
438    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
439
440  MI->eraseFromParent();   // The pseudo instruction is gone now.
441  return Sink;
442}
443