MipsSEISelLowering.cpp revision 9148c5d5495a25e8479f6a58e57f7058da1b4871 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#define DEBUG_TYPE "mips-isel"
14#include "MipsSEISelLowering.h"
15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/IR/Intrinsics.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
27static cl::opt<bool>
28EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
29                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
30
31static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
32                                   cl::desc("Expand double precision loads and "
33                                            "stores to their single precision "
34                                            "counterparts"));
35
36MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
37  : MipsTargetLowering(TM) {
38  // Set up the register classes
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45    // Expand all truncating stores and extending loads.
46    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
48
49    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51        setTruncStoreAction((MVT::SimpleValueType)VT0,
52                            (MVT::SimpleValueType)VT1, Expand);
53
54      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57    }
58  }
59
60  if (Subtarget->hasDSP()) {
61    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
62
63    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
65
66      // Expand all builtin opcodes.
67      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68        setOperationAction(Opc, VecTys[i], Expand);
69
70      setOperationAction(ISD::ADD, VecTys[i], Legal);
71      setOperationAction(ISD::SUB, VecTys[i], Legal);
72      setOperationAction(ISD::LOAD, VecTys[i], Legal);
73      setOperationAction(ISD::STORE, VecTys[i], Legal);
74      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
75    }
76
77    setTargetDAGCombine(ISD::SHL);
78    setTargetDAGCombine(ISD::SRA);
79    setTargetDAGCombine(ISD::SRL);
80    setTargetDAGCombine(ISD::SETCC);
81    setTargetDAGCombine(ISD::VSELECT);
82  }
83
84  if (Subtarget->hasDSPR2())
85    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
86
87  if (Subtarget->hasMSA()) {
88    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
95
96    setTargetDAGCombine(ISD::AND);
97    setTargetDAGCombine(ISD::OR);
98    setTargetDAGCombine(ISD::SRA);
99    setTargetDAGCombine(ISD::VSELECT);
100    setTargetDAGCombine(ISD::XOR);
101  }
102
103  if (!Subtarget->mipsSEUsesSoftFloat()) {
104    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105
106    // When dealing with single precision only, use libcalls
107    if (!Subtarget->isSingleFloat()) {
108      if (Subtarget->isFP64bit())
109        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110      else
111        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
112    }
113  }
114
115  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
116  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
117  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
118  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
119
120  if (HasMips64) {
121    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
122    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
123    setOperationAction(ISD::MUL,              MVT::i64, Custom);
124  }
125
126  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
127  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
128
129  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
130  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
131  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
132  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
133  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
134  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
135  setOperationAction(ISD::STORE,              MVT::i32, Custom);
136
137  setTargetDAGCombine(ISD::ADDE);
138  setTargetDAGCombine(ISD::SUBE);
139  setTargetDAGCombine(ISD::MUL);
140
141  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
142  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
143  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
144
145  if (NoDPLoadStore) {
146    setOperationAction(ISD::LOAD, MVT::f64, Custom);
147    setOperationAction(ISD::STORE, MVT::f64, Custom);
148  }
149
150  computeRegisterProperties();
151}
152
153const MipsTargetLowering *
154llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
155  return new MipsSETargetLowering(TM);
156}
157
158// Enable MSA support for the given integer type and Register class.
159void MipsSETargetLowering::
160addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
161  addRegisterClass(Ty, RC);
162
163  // Expand all builtin opcodes.
164  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
165    setOperationAction(Opc, Ty, Expand);
166
167  setOperationAction(ISD::BITCAST, Ty, Legal);
168  setOperationAction(ISD::LOAD, Ty, Legal);
169  setOperationAction(ISD::STORE, Ty, Legal);
170  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
171  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
172  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
173
174  setOperationAction(ISD::ADD, Ty, Legal);
175  setOperationAction(ISD::AND, Ty, Legal);
176  setOperationAction(ISD::CTLZ, Ty, Legal);
177  setOperationAction(ISD::CTPOP, Ty, Legal);
178  setOperationAction(ISD::MUL, Ty, Legal);
179  setOperationAction(ISD::OR, Ty, Legal);
180  setOperationAction(ISD::SDIV, Ty, Legal);
181  setOperationAction(ISD::SREM, Ty, Legal);
182  setOperationAction(ISD::SHL, Ty, Legal);
183  setOperationAction(ISD::SRA, Ty, Legal);
184  setOperationAction(ISD::SRL, Ty, Legal);
185  setOperationAction(ISD::SUB, Ty, Legal);
186  setOperationAction(ISD::UDIV, Ty, Legal);
187  setOperationAction(ISD::UREM, Ty, Legal);
188  setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
189  setOperationAction(ISD::VSELECT, Ty, Legal);
190  setOperationAction(ISD::XOR, Ty, Legal);
191
192  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
193    setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
194    setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
195    setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
196    setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
197  }
198
199  setOperationAction(ISD::SETCC, Ty, Legal);
200  setCondCodeAction(ISD::SETNE, Ty, Expand);
201  setCondCodeAction(ISD::SETGE, Ty, Expand);
202  setCondCodeAction(ISD::SETGT, Ty, Expand);
203  setCondCodeAction(ISD::SETUGE, Ty, Expand);
204  setCondCodeAction(ISD::SETUGT, Ty, Expand);
205}
206
207// Enable MSA support for the given floating-point type and Register class.
208void MipsSETargetLowering::
209addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
210  addRegisterClass(Ty, RC);
211
212  // Expand all builtin opcodes.
213  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
214    setOperationAction(Opc, Ty, Expand);
215
216  setOperationAction(ISD::LOAD, Ty, Legal);
217  setOperationAction(ISD::STORE, Ty, Legal);
218  setOperationAction(ISD::BITCAST, Ty, Legal);
219  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
220  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
222
223  if (Ty != MVT::v8f16) {
224    setOperationAction(ISD::FABS,  Ty, Legal);
225    setOperationAction(ISD::FADD,  Ty, Legal);
226    setOperationAction(ISD::FDIV,  Ty, Legal);
227    setOperationAction(ISD::FEXP2, Ty, Legal);
228    setOperationAction(ISD::FLOG2, Ty, Legal);
229    setOperationAction(ISD::FMA,   Ty, Legal);
230    setOperationAction(ISD::FMUL,  Ty, Legal);
231    setOperationAction(ISD::FRINT, Ty, Legal);
232    setOperationAction(ISD::FSQRT, Ty, Legal);
233    setOperationAction(ISD::FSUB,  Ty, Legal);
234    setOperationAction(ISD::VSELECT, Ty, Legal);
235
236    setOperationAction(ISD::SETCC, Ty, Legal);
237    setCondCodeAction(ISD::SETOGE, Ty, Expand);
238    setCondCodeAction(ISD::SETOGT, Ty, Expand);
239    setCondCodeAction(ISD::SETUGE, Ty, Expand);
240    setCondCodeAction(ISD::SETUGT, Ty, Expand);
241    setCondCodeAction(ISD::SETGE,  Ty, Expand);
242    setCondCodeAction(ISD::SETGT,  Ty, Expand);
243  }
244}
245
246bool
247MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
248  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
249
250  switch (SVT) {
251  case MVT::i64:
252  case MVT::i32:
253    if (Fast)
254      *Fast = true;
255    return true;
256  default:
257    return false;
258  }
259}
260
261SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
262                                             SelectionDAG &DAG) const {
263  switch(Op.getOpcode()) {
264  case ISD::LOAD:  return lowerLOAD(Op, DAG);
265  case ISD::STORE: return lowerSTORE(Op, DAG);
266  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
267  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
268  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
269  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
270  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
271  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
272  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
273                                          DAG);
274  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
275  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
276  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
277  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
278  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
279  case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);
280  }
281
282  return MipsTargetLowering::LowerOperation(Op, DAG);
283}
284
285// selectMADD -
286// Transforms a subgraph in CurDAG if the following pattern is found:
287//  (addc multLo, Lo0), (adde multHi, Hi0),
288// where,
289//  multHi/Lo: product of multiplication
290//  Lo0: initial value of Lo register
291//  Hi0: initial value of Hi register
292// Return true if pattern matching was successful.
293static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
294  // ADDENode's second operand must be a flag output of an ADDC node in order
295  // for the matching to be successful.
296  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
297
298  if (ADDCNode->getOpcode() != ISD::ADDC)
299    return false;
300
301  SDValue MultHi = ADDENode->getOperand(0);
302  SDValue MultLo = ADDCNode->getOperand(0);
303  SDNode *MultNode = MultHi.getNode();
304  unsigned MultOpc = MultHi.getOpcode();
305
306  // MultHi and MultLo must be generated by the same node,
307  if (MultLo.getNode() != MultNode)
308    return false;
309
310  // and it must be a multiplication.
311  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
312    return false;
313
314  // MultLo amd MultHi must be the first and second output of MultNode
315  // respectively.
316  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
317    return false;
318
319  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
320  // of the values of MultNode, in which case MultNode will be removed in later
321  // phases.
322  // If there exist users other than ADDENode or ADDCNode, this function returns
323  // here, which will result in MultNode being mapped to a single MULT
324  // instruction node rather than a pair of MULT and MADD instructions being
325  // produced.
326  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
327    return false;
328
329  SDLoc DL(ADDENode);
330
331  // Initialize accumulator.
332  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
333                                  ADDCNode->getOperand(1),
334                                  ADDENode->getOperand(1));
335
336  // create MipsMAdd(u) node
337  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
338
339  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
340                                 MultNode->getOperand(0),// Factor 0
341                                 MultNode->getOperand(1),// Factor 1
342                                 ACCIn);
343
344  // replace uses of adde and addc here
345  if (!SDValue(ADDCNode, 0).use_empty()) {
346    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
347    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
348  }
349  if (!SDValue(ADDENode, 0).use_empty()) {
350    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
351    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
352  }
353
354  return true;
355}
356
357// selectMSUB -
358// Transforms a subgraph in CurDAG if the following pattern is found:
359//  (addc Lo0, multLo), (sube Hi0, multHi),
360// where,
361//  multHi/Lo: product of multiplication
362//  Lo0: initial value of Lo register
363//  Hi0: initial value of Hi register
364// Return true if pattern matching was successful.
365static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
366  // SUBENode's second operand must be a flag output of an SUBC node in order
367  // for the matching to be successful.
368  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
369
370  if (SUBCNode->getOpcode() != ISD::SUBC)
371    return false;
372
373  SDValue MultHi = SUBENode->getOperand(1);
374  SDValue MultLo = SUBCNode->getOperand(1);
375  SDNode *MultNode = MultHi.getNode();
376  unsigned MultOpc = MultHi.getOpcode();
377
378  // MultHi and MultLo must be generated by the same node,
379  if (MultLo.getNode() != MultNode)
380    return false;
381
382  // and it must be a multiplication.
383  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
384    return false;
385
386  // MultLo amd MultHi must be the first and second output of MultNode
387  // respectively.
388  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
389    return false;
390
391  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
392  // of the values of MultNode, in which case MultNode will be removed in later
393  // phases.
394  // If there exist users other than SUBENode or SUBCNode, this function returns
395  // here, which will result in MultNode being mapped to a single MULT
396  // instruction node rather than a pair of MULT and MSUB instructions being
397  // produced.
398  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
399    return false;
400
401  SDLoc DL(SUBENode);
402
403  // Initialize accumulator.
404  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
405                                  SUBCNode->getOperand(0),
406                                  SUBENode->getOperand(0));
407
408  // create MipsSub(u) node
409  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
410
411  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
412                                 MultNode->getOperand(0),// Factor 0
413                                 MultNode->getOperand(1),// Factor 1
414                                 ACCIn);
415
416  // replace uses of sube and subc here
417  if (!SDValue(SUBCNode, 0).use_empty()) {
418    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
419    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
420  }
421  if (!SDValue(SUBENode, 0).use_empty()) {
422    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
423    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
424  }
425
426  return true;
427}
428
429static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
430                                  TargetLowering::DAGCombinerInfo &DCI,
431                                  const MipsSubtarget *Subtarget) {
432  if (DCI.isBeforeLegalize())
433    return SDValue();
434
435  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
436      selectMADD(N, &DAG))
437    return SDValue(N, 0);
438
439  return SDValue();
440}
441
442// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
443//
444// Performs the following transformations:
445// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
446//   sign/zero-extension is completely overwritten by the new one performed by
447//   the ISD::AND.
448// - Removes redundant zero extensions performed by an ISD::AND.
449static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
450                                 TargetLowering::DAGCombinerInfo &DCI,
451                                 const MipsSubtarget *Subtarget) {
452  if (!Subtarget->hasMSA())
453    return SDValue();
454
455  SDValue Op0 = N->getOperand(0);
456  SDValue Op1 = N->getOperand(1);
457  unsigned Op0Opcode = Op0->getOpcode();
458
459  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
460  // where $d + 1 == 2^n and n == 32
461  // or    $d + 1 == 2^n and n <= 32 and ZExt
462  // -> (MipsVExtractZExt $a, $b, $c)
463  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
464      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
465    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
466
467    if (!Mask)
468      return SDValue();
469
470    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
471
472    if (Log2IfPositive <= 0)
473      return SDValue(); // Mask+1 is not a power of 2
474
475    SDValue Op0Op2 = Op0->getOperand(2);
476    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
477    unsigned ExtendTySize = ExtendTy.getSizeInBits();
478    unsigned Log2 = Log2IfPositive;
479
480    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
481        Log2 == ExtendTySize) {
482      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
483      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
484                      Op0->getVTList(), Ops, Op0->getNumOperands());
485      return Op0;
486    }
487  }
488
489  return SDValue();
490}
491
492// Determine if the specified node is a constant vector splat.
493//
494// Returns true and sets Imm if:
495// * N is a ISD::BUILD_VECTOR representing a constant splat
496//
497// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
498// differences are that it assumes the MSA has already been checked and the
499// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
500// must not be in order for binsri.d to be selectable).
501static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
502  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
503
504  if (Node == NULL)
505    return false;
506
507  APInt SplatValue, SplatUndef;
508  unsigned SplatBitSize;
509  bool HasAnyUndefs;
510
511  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
512                             8, !IsLittleEndian))
513    return false;
514
515  Imm = SplatValue;
516
517  return true;
518}
519
520// Test whether the given node is an all-ones build_vector.
521static bool isVectorAllOnes(SDValue N) {
522  // Look through bitcasts. Endianness doesn't matter because we are looking
523  // for an all-ones value.
524  if (N->getOpcode() == ISD::BITCAST)
525    N = N->getOperand(0);
526
527  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
528
529  if (!BVN)
530    return false;
531
532  APInt SplatValue, SplatUndef;
533  unsigned SplatBitSize;
534  bool HasAnyUndefs;
535
536  // Endianness doesn't matter in this context because we are looking for
537  // an all-ones value.
538  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
539    return SplatValue.isAllOnesValue();
540
541  return false;
542}
543
544// Test whether N is the bitwise inverse of OfNode.
545static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
546  if (N->getOpcode() != ISD::XOR)
547    return false;
548
549  if (isVectorAllOnes(N->getOperand(0)))
550    return N->getOperand(1) == OfNode;
551
552  if (isVectorAllOnes(N->getOperand(1)))
553    return N->getOperand(0) == OfNode;
554
555  return false;
556}
557
558// Perform combines where ISD::OR is the root node.
559//
560// Performs the following transformations:
561// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
562//   where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
563//   vector type.
564static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
565                                TargetLowering::DAGCombinerInfo &DCI,
566                                const MipsSubtarget *Subtarget) {
567  if (!Subtarget->hasMSA())
568    return SDValue();
569
570  EVT Ty = N->getValueType(0);
571
572  if (!Ty.is128BitVector())
573    return SDValue();
574
575  SDValue Op0 = N->getOperand(0);
576  SDValue Op1 = N->getOperand(1);
577
578  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
579    SDValue Op0Op0 = Op0->getOperand(0);
580    SDValue Op0Op1 = Op0->getOperand(1);
581    SDValue Op1Op0 = Op1->getOperand(0);
582    SDValue Op1Op1 = Op1->getOperand(1);
583    bool IsLittleEndian = !Subtarget->isLittle();
584
585    SDValue IfSet, IfClr, Cond;
586    bool IsConstantMask = false;
587    APInt Mask, InvMask;
588
589    // If Op0Op0 is an appropriate mask, try to find it's inverse in either
590    // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
591    // looking.
592    // IfClr will be set if we find a valid match.
593    if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
594      Cond = Op0Op0;
595      IfSet = Op0Op1;
596
597      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
598        IfClr = Op1Op1;
599      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
600        IfClr = Op1Op0;
601
602      IsConstantMask = true;
603    }
604
605    // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
606    // thing again using this mask.
607    // IfClr will be set if we find a valid match.
608    if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
609      Cond = Op0Op1;
610      IfSet = Op0Op0;
611
612      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
613        IfClr = Op1Op1;
614      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
615        IfClr = Op1Op0;
616
617      IsConstantMask = true;
618    }
619
620    // If IfClr is not yet set, try looking for a non-constant match.
621    // IfClr will be set if we find a valid match amongst the eight
622    // possibilities.
623    if (!IfClr.getNode()) {
624      if (isBitwiseInverse(Op0Op0, Op1Op0)) {
625        Cond = Op1Op0;
626        IfSet = Op1Op1;
627        IfClr = Op0Op1;
628      } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
629        Cond = Op1Op0;
630        IfSet = Op1Op1;
631        IfClr = Op0Op0;
632      } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
633        Cond = Op1Op1;
634        IfSet = Op1Op0;
635        IfClr = Op0Op1;
636      } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
637        Cond = Op1Op1;
638        IfSet = Op1Op0;
639        IfClr = Op0Op0;
640      } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
641        Cond = Op0Op0;
642        IfSet = Op0Op1;
643        IfClr = Op1Op1;
644      } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
645        Cond = Op0Op0;
646        IfSet = Op0Op1;
647        IfClr = Op1Op0;
648      } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
649        Cond = Op0Op1;
650        IfSet = Op0Op0;
651        IfClr = Op1Op1;
652      } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
653        Cond = Op0Op1;
654        IfSet = Op0Op0;
655        IfClr = Op1Op0;
656      }
657    }
658
659    // At this point, IfClr will be set if we have a valid match.
660    if (!IfClr.getNode())
661      return SDValue();
662
663    assert(Cond.getNode() && IfSet.getNode());
664
665    // Fold degenerate cases.
666    if (IsConstantMask) {
667      if (Mask.isAllOnesValue())
668        return IfSet;
669      else if (Mask == 0)
670        return IfClr;
671    }
672
673    // Transform the DAG into an equivalent VSELECT.
674    return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
675  }
676
677  return SDValue();
678}
679
680static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
681                                  TargetLowering::DAGCombinerInfo &DCI,
682                                  const MipsSubtarget *Subtarget) {
683  if (DCI.isBeforeLegalize())
684    return SDValue();
685
686  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
687      selectMSUB(N, &DAG))
688    return SDValue(N, 0);
689
690  return SDValue();
691}
692
693static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
694                            EVT ShiftTy, SelectionDAG &DAG) {
695  // Clear the upper (64 - VT.sizeInBits) bits.
696  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
697
698  // Return 0.
699  if (C == 0)
700    return DAG.getConstant(0, VT);
701
702  // Return x.
703  if (C == 1)
704    return X;
705
706  // If c is power of 2, return (shl x, log2(c)).
707  if (isPowerOf2_64(C))
708    return DAG.getNode(ISD::SHL, DL, VT, X,
709                       DAG.getConstant(Log2_64(C), ShiftTy));
710
711  unsigned Log2Ceil = Log2_64_Ceil(C);
712  uint64_t Floor = 1LL << Log2_64(C);
713  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
714
715  // If |c - floor_c| <= |c - ceil_c|,
716  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
717  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
718  if (C - Floor <= Ceil - C) {
719    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
720    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
721    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
722  }
723
724  // If |c - floor_c| > |c - ceil_c|,
725  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
726  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
727  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
728  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
729}
730
731static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
732                                 const TargetLowering::DAGCombinerInfo &DCI,
733                                 const MipsSETargetLowering *TL) {
734  EVT VT = N->getValueType(0);
735
736  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
737    if (!VT.isVector())
738      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
739                          VT, TL->getScalarShiftAmountTy(VT), DAG);
740
741  return SDValue(N, 0);
742}
743
744static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
745                                      SelectionDAG &DAG,
746                                      const MipsSubtarget *Subtarget) {
747  // See if this is a vector splat immediate node.
748  APInt SplatValue, SplatUndef;
749  unsigned SplatBitSize;
750  bool HasAnyUndefs;
751  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
752  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
753
754  if (!Subtarget->hasDSP())
755    return SDValue();
756
757  if (!BV ||
758      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
759                           EltSize, !Subtarget->isLittle()) ||
760      (SplatBitSize != EltSize) ||
761      (SplatValue.getZExtValue() >= EltSize))
762    return SDValue();
763
764  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
765                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
766}
767
768static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
769                                 TargetLowering::DAGCombinerInfo &DCI,
770                                 const MipsSubtarget *Subtarget) {
771  EVT Ty = N->getValueType(0);
772
773  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
774    return SDValue();
775
776  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
777}
778
779// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
780// constant splats into MipsISD::SHRA_DSP for DSPr2.
781//
782// Performs the following transformations:
783// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
784//   sign/zero-extension is completely overwritten by the new one performed by
785//   the ISD::SRA and ISD::SHL nodes.
786// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
787//   sequence.
788//
789// See performDSPShiftCombine for more information about the transformation
790// used for DSPr2.
791static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
792                                 TargetLowering::DAGCombinerInfo &DCI,
793                                 const MipsSubtarget *Subtarget) {
794  EVT Ty = N->getValueType(0);
795
796  if (Subtarget->hasMSA()) {
797    SDValue Op0 = N->getOperand(0);
798    SDValue Op1 = N->getOperand(1);
799
800    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
801    // where $d + sizeof($c) == 32
802    // or    $d + sizeof($c) <= 32 and SExt
803    // -> (MipsVExtractSExt $a, $b, $c)
804    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
805      SDValue Op0Op0 = Op0->getOperand(0);
806      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
807
808      if (!ShAmount)
809        return SDValue();
810
811      if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
812          Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
813        return SDValue();
814
815      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
816      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
817
818      if (TotalBits == 32 ||
819          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
820           TotalBits <= 32)) {
821        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
822                          Op0Op0->getOperand(2) };
823        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
824                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
825        return Op0Op0;
826      }
827    }
828  }
829
830  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
831    return SDValue();
832
833  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
834}
835
836
837static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
838                                 TargetLowering::DAGCombinerInfo &DCI,
839                                 const MipsSubtarget *Subtarget) {
840  EVT Ty = N->getValueType(0);
841
842  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
843    return SDValue();
844
845  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
846}
847
848static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
849  bool IsV216 = (Ty == MVT::v2i16);
850
851  switch (CC) {
852  case ISD::SETEQ:
853  case ISD::SETNE:  return true;
854  case ISD::SETLT:
855  case ISD::SETLE:
856  case ISD::SETGT:
857  case ISD::SETGE:  return IsV216;
858  case ISD::SETULT:
859  case ISD::SETULE:
860  case ISD::SETUGT:
861  case ISD::SETUGE: return !IsV216;
862  default:          return false;
863  }
864}
865
866static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
867  EVT Ty = N->getValueType(0);
868
869  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
870    return SDValue();
871
872  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
873    return SDValue();
874
875  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
876                     N->getOperand(1), N->getOperand(2));
877}
878
879static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
880  EVT Ty = N->getValueType(0);
881
882  if (Ty.is128BitVector() && Ty.isInteger()) {
883    // Try the following combines:
884    //   (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
885    //   (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
886    //   (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
887    //   (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
888    //   (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
889    //   (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
890    //   (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
891    //   (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
892    // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
893    // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
894    // legalizer.
895    SDValue Op0 = N->getOperand(0);
896
897    if (Op0->getOpcode() != ISD::SETCC)
898      return SDValue();
899
900    ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
901    bool Signed;
902
903    if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)
904      Signed = true;
905    else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
906      Signed = false;
907    else
908      return SDValue();
909
910    SDValue Op1 = N->getOperand(1);
911    SDValue Op2 = N->getOperand(2);
912    SDValue Op0Op0 = Op0->getOperand(0);
913    SDValue Op0Op1 = Op0->getOperand(1);
914
915    if (Op1 == Op0Op0 && Op2 == Op0Op1)
916      return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
917                         Ty, Op1, Op2);
918    else if (Op1 == Op0Op1 && Op2 == Op0Op0)
919      return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
920                         Ty, Op1, Op2);
921  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
922    SDValue SetCC = N->getOperand(0);
923
924    if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
925      return SDValue();
926
927    return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
928                       SetCC.getOperand(0), SetCC.getOperand(1),
929                       N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
930  }
931
932  return SDValue();
933}
934
935static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
936                                 const MipsSubtarget *Subtarget) {
937  EVT Ty = N->getValueType(0);
938
939  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
940    // Try the following combines:
941    //   (xor (or $a, $b), (build_vector allones))
942    //   (xor (or $a, $b), (bitcast (build_vector allones)))
943    SDValue Op0 = N->getOperand(0);
944    SDValue Op1 = N->getOperand(1);
945    SDValue NotOp;
946
947    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
948      NotOp = Op1;
949    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
950      NotOp = Op0;
951    else
952      return SDValue();
953
954    if (NotOp->getOpcode() == ISD::OR)
955      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
956                         NotOp->getOperand(1));
957  }
958
959  return SDValue();
960}
961
962SDValue
963MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
964  SelectionDAG &DAG = DCI.DAG;
965  SDValue Val;
966
967  switch (N->getOpcode()) {
968  case ISD::ADDE:
969    return performADDECombine(N, DAG, DCI, Subtarget);
970  case ISD::AND:
971    Val = performANDCombine(N, DAG, DCI, Subtarget);
972    break;
973  case ISD::OR:
974    Val = performORCombine(N, DAG, DCI, Subtarget);
975    break;
976  case ISD::SUBE:
977    return performSUBECombine(N, DAG, DCI, Subtarget);
978  case ISD::MUL:
979    return performMULCombine(N, DAG, DCI, this);
980  case ISD::SHL:
981    return performSHLCombine(N, DAG, DCI, Subtarget);
982  case ISD::SRA:
983    return performSRACombine(N, DAG, DCI, Subtarget);
984  case ISD::SRL:
985    return performSRLCombine(N, DAG, DCI, Subtarget);
986  case ISD::VSELECT:
987    return performVSELECTCombine(N, DAG);
988  case ISD::XOR:
989    Val = performXORCombine(N, DAG, Subtarget);
990    break;
991  case ISD::SETCC:
992    Val = performSETCCCombine(N, DAG);
993    break;
994  }
995
996  if (Val.getNode()) {
997    DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
998          N->printrWithDepth(dbgs(), &DAG);
999          dbgs() << "\n=> \n";
1000          Val.getNode()->printrWithDepth(dbgs(), &DAG);
1001          dbgs() << "\n");
1002    return Val;
1003  }
1004
1005  return MipsTargetLowering::PerformDAGCombine(N, DCI);
1006}
1007
1008MachineBasicBlock *
1009MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1010                                                  MachineBasicBlock *BB) const {
1011  switch (MI->getOpcode()) {
1012  default:
1013    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1014  case Mips::BPOSGE32_PSEUDO:
1015    return emitBPOSGE32(MI, BB);
1016  case Mips::SNZ_B_PSEUDO:
1017    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1018  case Mips::SNZ_H_PSEUDO:
1019    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1020  case Mips::SNZ_W_PSEUDO:
1021    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1022  case Mips::SNZ_D_PSEUDO:
1023    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1024  case Mips::SNZ_V_PSEUDO:
1025    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1026  case Mips::SZ_B_PSEUDO:
1027    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1028  case Mips::SZ_H_PSEUDO:
1029    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1030  case Mips::SZ_W_PSEUDO:
1031    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1032  case Mips::SZ_D_PSEUDO:
1033    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1034  case Mips::SZ_V_PSEUDO:
1035    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1036  case Mips::COPY_FW_PSEUDO:
1037    return emitCOPY_FW(MI, BB);
1038  case Mips::COPY_FD_PSEUDO:
1039    return emitCOPY_FD(MI, BB);
1040  case Mips::INSERT_FW_PSEUDO:
1041    return emitINSERT_FW(MI, BB);
1042  case Mips::INSERT_FD_PSEUDO:
1043    return emitINSERT_FD(MI, BB);
1044  case Mips::FILL_FW_PSEUDO:
1045    return emitFILL_FW(MI, BB);
1046  case Mips::FILL_FD_PSEUDO:
1047    return emitFILL_FD(MI, BB);
1048  case Mips::FEXP2_W_1_PSEUDO:
1049    return emitFEXP2_W_1(MI, BB);
1050  case Mips::FEXP2_D_1_PSEUDO:
1051    return emitFEXP2_D_1(MI, BB);
1052  }
1053}
1054
1055bool MipsSETargetLowering::
1056isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1057                                  unsigned NextStackOffset,
1058                                  const MipsFunctionInfo& FI) const {
1059  if (!EnableMipsTailCalls)
1060    return false;
1061
1062  // Return false if either the callee or caller has a byval argument.
1063  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1064    return false;
1065
1066  // Return true if the callee's argument area is no larger than the
1067  // caller's.
1068  return NextStackOffset <= FI.getIncomingArgSize();
1069}
1070
1071void MipsSETargetLowering::
1072getOpndList(SmallVectorImpl<SDValue> &Ops,
1073            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1074            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1075            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1076  // T9 should contain the address of the callee function if
1077  // -reloction-model=pic or it is an indirect call.
1078  if (IsPICCall || !GlobalOrExternal) {
1079    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
1080    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
1081  } else
1082    Ops.push_back(Callee);
1083
1084  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1085                                  InternalLinkage, CLI, Callee, Chain);
1086}
1087
1088SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1089  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1090
1091  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1092    return MipsTargetLowering::lowerLOAD(Op, DAG);
1093
1094  // Replace a double precision load with two i32 loads and a buildpair64.
1095  SDLoc DL(Op);
1096  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1097  EVT PtrVT = Ptr.getValueType();
1098
1099  // i32 load from lower address.
1100  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1101                           MachinePointerInfo(), Nd.isVolatile(),
1102                           Nd.isNonTemporal(), Nd.isInvariant(),
1103                           Nd.getAlignment());
1104
1105  // i32 load from higher address.
1106  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1107  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1108                           MachinePointerInfo(), Nd.isVolatile(),
1109                           Nd.isNonTemporal(), Nd.isInvariant(),
1110                           std::min(Nd.getAlignment(), 4U));
1111
1112  if (!Subtarget->isLittle())
1113    std::swap(Lo, Hi);
1114
1115  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1116  SDValue Ops[2] = {BP, Hi.getValue(1)};
1117  return DAG.getMergeValues(Ops, 2, DL);
1118}
1119
1120SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1121  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1122
1123  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1124    return MipsTargetLowering::lowerSTORE(Op, DAG);
1125
1126  // Replace a double precision store with two extractelement64s and i32 stores.
1127  SDLoc DL(Op);
1128  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1129  EVT PtrVT = Ptr.getValueType();
1130  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1131                           Val, DAG.getConstant(0, MVT::i32));
1132  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1133                           Val, DAG.getConstant(1, MVT::i32));
1134
1135  if (!Subtarget->isLittle())
1136    std::swap(Lo, Hi);
1137
1138  // i32 store to lower address.
1139  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1140                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1141                       Nd.getTBAAInfo());
1142
1143  // i32 store to higher address.
1144  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1145  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1146                      Nd.isVolatile(), Nd.isNonTemporal(),
1147                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1148}
1149
1150SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1151                                          bool HasLo, bool HasHi,
1152                                          SelectionDAG &DAG) const {
1153  EVT Ty = Op.getOperand(0).getValueType();
1154  SDLoc DL(Op);
1155  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1156                             Op.getOperand(0), Op.getOperand(1));
1157  SDValue Lo, Hi;
1158
1159  if (HasLo)
1160    Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1161  if (HasHi)
1162    Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1163
1164  if (!HasLo || !HasHi)
1165    return HasLo ? Lo : Hi;
1166
1167  SDValue Vals[] = { Lo, Hi };
1168  return DAG.getMergeValues(Vals, 2, DL);
1169}
1170
1171
1172static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1173  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1174                             DAG.getConstant(0, MVT::i32));
1175  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1176                             DAG.getConstant(1, MVT::i32));
1177  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1178}
1179
1180static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1181  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1182  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1183  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1184}
1185
1186// This function expands mips intrinsic nodes which have 64-bit input operands
1187// or output values.
1188//
1189// out64 = intrinsic-node in64
1190// =>
1191// lo = copy (extract-element (in64, 0))
1192// hi = copy (extract-element (in64, 1))
1193// mips-specific-node
1194// v0 = copy lo
1195// v1 = copy hi
1196// out64 = merge-values (v0, v1)
1197//
1198static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1199  SDLoc DL(Op);
1200  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1201  SmallVector<SDValue, 3> Ops;
1202  unsigned OpNo = 0;
1203
1204  // See if Op has a chain input.
1205  if (HasChainIn)
1206    Ops.push_back(Op->getOperand(OpNo++));
1207
1208  // The next operand is the intrinsic opcode.
1209  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1210
1211  // See if the next operand has type i64.
1212  SDValue Opnd = Op->getOperand(++OpNo), In64;
1213
1214  if (Opnd.getValueType() == MVT::i64)
1215    In64 = initAccumulator(Opnd, DL, DAG);
1216  else
1217    Ops.push_back(Opnd);
1218
1219  // Push the remaining operands.
1220  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1221    Ops.push_back(Op->getOperand(OpNo));
1222
1223  // Add In64 to the end of the list.
1224  if (In64.getNode())
1225    Ops.push_back(In64);
1226
1227  // Scan output.
1228  SmallVector<EVT, 2> ResTys;
1229
1230  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1231       I != E; ++I)
1232    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1233
1234  // Create node.
1235  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1236  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1237
1238  if (!HasChainIn)
1239    return Out;
1240
1241  assert(Val->getValueType(1) == MVT::Other);
1242  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1243  return DAG.getMergeValues(Vals, 2, DL);
1244}
1245
1246// Lower an MSA copy intrinsic into the specified SelectionDAG node
1247static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1248  SDLoc DL(Op);
1249  SDValue Vec = Op->getOperand(1);
1250  SDValue Idx = Op->getOperand(2);
1251  EVT ResTy = Op->getValueType(0);
1252  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1253
1254  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1255                               DAG.getValueType(EltTy));
1256
1257  return Result;
1258}
1259
1260static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1261  EVT ResVecTy = Op->getValueType(0);
1262  EVT ViaVecTy = ResVecTy;
1263  SDLoc DL(Op);
1264
1265  // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1266  // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1267  // lanes.
1268  SDValue LaneA;
1269  SDValue LaneB = Op->getOperand(2);
1270
1271  if (ResVecTy == MVT::v2i64) {
1272    LaneA = DAG.getConstant(0, MVT::i32);
1273    ViaVecTy = MVT::v4i32;
1274  } else
1275    LaneA = LaneB;
1276
1277  SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1278                      LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1279
1280  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1281                               ViaVecTy.getVectorNumElements());
1282
1283  if (ViaVecTy != ResVecTy)
1284    Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
1285
1286  return Result;
1287}
1288
1289static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1290  return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0));
1291}
1292
1293static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1294                                   bool BigEndian, SelectionDAG &DAG) {
1295  EVT ViaVecTy = VecTy;
1296  SDValue SplatValueA = SplatValue;
1297  SDValue SplatValueB = SplatValue;
1298  SDLoc DL(SplatValue);
1299
1300  if (VecTy == MVT::v2i64) {
1301    // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1302    ViaVecTy = MVT::v4i32;
1303
1304    SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1305    SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
1306                              DAG.getConstant(32, MVT::i32));
1307    SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1308  }
1309
1310  // We currently hold the parts in little endian order. Swap them if
1311  // necessary.
1312  if (BigEndian)
1313    std::swap(SplatValueA, SplatValueB);
1314
1315  SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1316                      SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1317                      SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1318                      SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1319
1320  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops,
1321                               ViaVecTy.getVectorNumElements());
1322
1323  if (VecTy != ViaVecTy)
1324    Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1325
1326  return Result;
1327}
1328
1329static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1330                                        unsigned Opc, SDValue Imm,
1331                                        bool BigEndian) {
1332  EVT VecTy = Op->getValueType(0);
1333  SDValue Exp2Imm;
1334  SDLoc DL(Op);
1335
1336  // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1337  // here for now.
1338  if (VecTy == MVT::v2i64) {
1339    if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1340      APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1341
1342      SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1343      SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1344
1345      if (BigEndian)
1346        std::swap(BitImmLoOp, BitImmHiOp);
1347
1348      Exp2Imm =
1349          DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1350                      DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp,
1351                                  BitImmHiOp, BitImmLoOp, BitImmHiOp));
1352    }
1353  }
1354
1355  if (Exp2Imm.getNode() == NULL) {
1356    // We couldnt constant fold, do a vector shift instead
1357
1358    // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1359    // only values 0-63 are valid.
1360    if (VecTy == MVT::v2i64)
1361      Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1362
1363    Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1364
1365    Exp2Imm =
1366        DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm);
1367  }
1368
1369  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1370}
1371
1372static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1373  EVT ResTy = Op->getValueType(0);
1374  SDLoc DL(Op);
1375  SDValue One = DAG.getConstant(1, ResTy);
1376  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1377
1378  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1379                     DAG.getNOT(DL, Bit, ResTy));
1380}
1381
1382static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1383  SDLoc DL(Op);
1384  EVT ResTy = Op->getValueType(0);
1385  APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1386                 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
1387  SDValue BitMask = DAG.getConstant(~BitImm, ResTy);
1388
1389  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1390}
1391
1392SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1393                                                      SelectionDAG &DAG) const {
1394  SDLoc DL(Op);
1395
1396  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1397  default:
1398    return SDValue();
1399  case Intrinsic::mips_shilo:
1400    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1401  case Intrinsic::mips_dpau_h_qbl:
1402    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1403  case Intrinsic::mips_dpau_h_qbr:
1404    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1405  case Intrinsic::mips_dpsu_h_qbl:
1406    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1407  case Intrinsic::mips_dpsu_h_qbr:
1408    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1409  case Intrinsic::mips_dpa_w_ph:
1410    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1411  case Intrinsic::mips_dps_w_ph:
1412    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1413  case Intrinsic::mips_dpax_w_ph:
1414    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1415  case Intrinsic::mips_dpsx_w_ph:
1416    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1417  case Intrinsic::mips_mulsa_w_ph:
1418    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1419  case Intrinsic::mips_mult:
1420    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1421  case Intrinsic::mips_multu:
1422    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1423  case Intrinsic::mips_madd:
1424    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1425  case Intrinsic::mips_maddu:
1426    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1427  case Intrinsic::mips_msub:
1428    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1429  case Intrinsic::mips_msubu:
1430    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1431  case Intrinsic::mips_addv_b:
1432  case Intrinsic::mips_addv_h:
1433  case Intrinsic::mips_addv_w:
1434  case Intrinsic::mips_addv_d:
1435    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1436                       Op->getOperand(2));
1437  case Intrinsic::mips_addvi_b:
1438  case Intrinsic::mips_addvi_h:
1439  case Intrinsic::mips_addvi_w:
1440  case Intrinsic::mips_addvi_d:
1441    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1442                       lowerMSASplatImm(Op, 2, DAG));
1443  case Intrinsic::mips_and_v:
1444    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1445                       Op->getOperand(2));
1446  case Intrinsic::mips_andi_b:
1447    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1448                       lowerMSASplatImm(Op, 2, DAG));
1449  case Intrinsic::mips_bclr_b:
1450  case Intrinsic::mips_bclr_h:
1451  case Intrinsic::mips_bclr_w:
1452  case Intrinsic::mips_bclr_d:
1453    return lowerMSABitClear(Op, DAG);
1454  case Intrinsic::mips_bclri_b:
1455  case Intrinsic::mips_bclri_h:
1456  case Intrinsic::mips_bclri_w:
1457  case Intrinsic::mips_bclri_d:
1458    return lowerMSABitClearImm(Op, DAG);
1459  case Intrinsic::mips_binsli_b:
1460  case Intrinsic::mips_binsli_h:
1461  case Intrinsic::mips_binsli_w:
1462  case Intrinsic::mips_binsli_d: {
1463    EVT VecTy = Op->getValueType(0);
1464    EVT EltTy = VecTy.getVectorElementType();
1465    APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1466                                       Op->getConstantOperandVal(3));
1467    return DAG.getNode(ISD::VSELECT, DL, VecTy,
1468                       DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1469                       Op->getOperand(2));
1470  }
1471  case Intrinsic::mips_binsri_b:
1472  case Intrinsic::mips_binsri_h:
1473  case Intrinsic::mips_binsri_w:
1474  case Intrinsic::mips_binsri_d: {
1475    EVT VecTy = Op->getValueType(0);
1476    EVT EltTy = VecTy.getVectorElementType();
1477    APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1478                                      Op->getConstantOperandVal(3));
1479    return DAG.getNode(ISD::VSELECT, DL, VecTy,
1480                       DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1481                       Op->getOperand(2));
1482  }
1483  case Intrinsic::mips_bmnz_v:
1484    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1485                       Op->getOperand(2), Op->getOperand(1));
1486  case Intrinsic::mips_bmnzi_b:
1487    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1488                       lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1489                       Op->getOperand(1));
1490  case Intrinsic::mips_bmz_v:
1491    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1492                       Op->getOperand(1), Op->getOperand(2));
1493  case Intrinsic::mips_bmzi_b:
1494    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1495                       lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1496                       Op->getOperand(2));
1497  case Intrinsic::mips_bneg_b:
1498  case Intrinsic::mips_bneg_h:
1499  case Intrinsic::mips_bneg_w:
1500  case Intrinsic::mips_bneg_d: {
1501    EVT VecTy = Op->getValueType(0);
1502    SDValue One = DAG.getConstant(1, VecTy);
1503
1504    return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1505                       DAG.getNode(ISD::SHL, DL, VecTy, One,
1506                                   Op->getOperand(2)));
1507  }
1508  case Intrinsic::mips_bnegi_b:
1509  case Intrinsic::mips_bnegi_h:
1510  case Intrinsic::mips_bnegi_w:
1511  case Intrinsic::mips_bnegi_d:
1512    return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1513                                    !Subtarget->isLittle());
1514  case Intrinsic::mips_bnz_b:
1515  case Intrinsic::mips_bnz_h:
1516  case Intrinsic::mips_bnz_w:
1517  case Intrinsic::mips_bnz_d:
1518    return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1519                       Op->getOperand(1));
1520  case Intrinsic::mips_bnz_v:
1521    return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1522                       Op->getOperand(1));
1523  case Intrinsic::mips_bsel_v:
1524    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1525                       Op->getOperand(1), Op->getOperand(2),
1526                       Op->getOperand(3));
1527  case Intrinsic::mips_bseli_b:
1528    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1529                       Op->getOperand(1), Op->getOperand(2),
1530                       lowerMSASplatImm(Op, 3, DAG));
1531  case Intrinsic::mips_bset_b:
1532  case Intrinsic::mips_bset_h:
1533  case Intrinsic::mips_bset_w:
1534  case Intrinsic::mips_bset_d: {
1535    EVT VecTy = Op->getValueType(0);
1536    SDValue One = DAG.getConstant(1, VecTy);
1537
1538    return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1539                       DAG.getNode(ISD::SHL, DL, VecTy, One,
1540                                   Op->getOperand(2)));
1541  }
1542  case Intrinsic::mips_bseti_b:
1543  case Intrinsic::mips_bseti_h:
1544  case Intrinsic::mips_bseti_w:
1545  case Intrinsic::mips_bseti_d:
1546    return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1547                                    !Subtarget->isLittle());
1548  case Intrinsic::mips_bz_b:
1549  case Intrinsic::mips_bz_h:
1550  case Intrinsic::mips_bz_w:
1551  case Intrinsic::mips_bz_d:
1552    return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1553                       Op->getOperand(1));
1554  case Intrinsic::mips_bz_v:
1555    return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1556                       Op->getOperand(1));
1557  case Intrinsic::mips_ceq_b:
1558  case Intrinsic::mips_ceq_h:
1559  case Intrinsic::mips_ceq_w:
1560  case Intrinsic::mips_ceq_d:
1561    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1562                        Op->getOperand(2), ISD::SETEQ);
1563  case Intrinsic::mips_ceqi_b:
1564  case Intrinsic::mips_ceqi_h:
1565  case Intrinsic::mips_ceqi_w:
1566  case Intrinsic::mips_ceqi_d:
1567    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1568                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1569  case Intrinsic::mips_cle_s_b:
1570  case Intrinsic::mips_cle_s_h:
1571  case Intrinsic::mips_cle_s_w:
1572  case Intrinsic::mips_cle_s_d:
1573    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1574                        Op->getOperand(2), ISD::SETLE);
1575  case Intrinsic::mips_clei_s_b:
1576  case Intrinsic::mips_clei_s_h:
1577  case Intrinsic::mips_clei_s_w:
1578  case Intrinsic::mips_clei_s_d:
1579    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1580                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1581  case Intrinsic::mips_cle_u_b:
1582  case Intrinsic::mips_cle_u_h:
1583  case Intrinsic::mips_cle_u_w:
1584  case Intrinsic::mips_cle_u_d:
1585    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1586                        Op->getOperand(2), ISD::SETULE);
1587  case Intrinsic::mips_clei_u_b:
1588  case Intrinsic::mips_clei_u_h:
1589  case Intrinsic::mips_clei_u_w:
1590  case Intrinsic::mips_clei_u_d:
1591    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1592                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1593  case Intrinsic::mips_clt_s_b:
1594  case Intrinsic::mips_clt_s_h:
1595  case Intrinsic::mips_clt_s_w:
1596  case Intrinsic::mips_clt_s_d:
1597    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1598                        Op->getOperand(2), ISD::SETLT);
1599  case Intrinsic::mips_clti_s_b:
1600  case Intrinsic::mips_clti_s_h:
1601  case Intrinsic::mips_clti_s_w:
1602  case Intrinsic::mips_clti_s_d:
1603    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1604                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1605  case Intrinsic::mips_clt_u_b:
1606  case Intrinsic::mips_clt_u_h:
1607  case Intrinsic::mips_clt_u_w:
1608  case Intrinsic::mips_clt_u_d:
1609    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1610                        Op->getOperand(2), ISD::SETULT);
1611  case Intrinsic::mips_clti_u_b:
1612  case Intrinsic::mips_clti_u_h:
1613  case Intrinsic::mips_clti_u_w:
1614  case Intrinsic::mips_clti_u_d:
1615    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1616                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1617  case Intrinsic::mips_copy_s_b:
1618  case Intrinsic::mips_copy_s_h:
1619  case Intrinsic::mips_copy_s_w:
1620    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1621  case Intrinsic::mips_copy_s_d:
1622    // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1623    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1624    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1625    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1626                       Op->getOperand(1), Op->getOperand(2));
1627  case Intrinsic::mips_copy_u_b:
1628  case Intrinsic::mips_copy_u_h:
1629  case Intrinsic::mips_copy_u_w:
1630    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1631  case Intrinsic::mips_copy_u_d:
1632    // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1633    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1634    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1635    //
1636    // Note: When i64 is illegal, this results in copy_s.w instructions instead
1637    // of copy_u.w instructions. This makes no difference to the behaviour
1638    // since i64 is only illegal when the register file is 32-bit.
1639    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1640                       Op->getOperand(1), Op->getOperand(2));
1641  case Intrinsic::mips_div_s_b:
1642  case Intrinsic::mips_div_s_h:
1643  case Intrinsic::mips_div_s_w:
1644  case Intrinsic::mips_div_s_d:
1645    return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1646                       Op->getOperand(2));
1647  case Intrinsic::mips_div_u_b:
1648  case Intrinsic::mips_div_u_h:
1649  case Intrinsic::mips_div_u_w:
1650  case Intrinsic::mips_div_u_d:
1651    return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1652                       Op->getOperand(2));
1653  case Intrinsic::mips_fadd_w:
1654  case Intrinsic::mips_fadd_d:
1655    return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1656                       Op->getOperand(2));
1657  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1658  case Intrinsic::mips_fceq_w:
1659  case Intrinsic::mips_fceq_d:
1660    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1661                        Op->getOperand(2), ISD::SETOEQ);
1662  case Intrinsic::mips_fcle_w:
1663  case Intrinsic::mips_fcle_d:
1664    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1665                        Op->getOperand(2), ISD::SETOLE);
1666  case Intrinsic::mips_fclt_w:
1667  case Intrinsic::mips_fclt_d:
1668    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1669                        Op->getOperand(2), ISD::SETOLT);
1670  case Intrinsic::mips_fcne_w:
1671  case Intrinsic::mips_fcne_d:
1672    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1673                        Op->getOperand(2), ISD::SETONE);
1674  case Intrinsic::mips_fcor_w:
1675  case Intrinsic::mips_fcor_d:
1676    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1677                        Op->getOperand(2), ISD::SETO);
1678  case Intrinsic::mips_fcueq_w:
1679  case Intrinsic::mips_fcueq_d:
1680    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1681                        Op->getOperand(2), ISD::SETUEQ);
1682  case Intrinsic::mips_fcule_w:
1683  case Intrinsic::mips_fcule_d:
1684    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1685                        Op->getOperand(2), ISD::SETULE);
1686  case Intrinsic::mips_fcult_w:
1687  case Intrinsic::mips_fcult_d:
1688    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1689                        Op->getOperand(2), ISD::SETULT);
1690  case Intrinsic::mips_fcun_w:
1691  case Intrinsic::mips_fcun_d:
1692    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1693                        Op->getOperand(2), ISD::SETUO);
1694  case Intrinsic::mips_fcune_w:
1695  case Intrinsic::mips_fcune_d:
1696    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1697                        Op->getOperand(2), ISD::SETUNE);
1698  case Intrinsic::mips_fdiv_w:
1699  case Intrinsic::mips_fdiv_d:
1700    return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1701                       Op->getOperand(2));
1702  case Intrinsic::mips_ffint_u_w:
1703  case Intrinsic::mips_ffint_u_d:
1704    return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1705                       Op->getOperand(1));
1706  case Intrinsic::mips_ffint_s_w:
1707  case Intrinsic::mips_ffint_s_d:
1708    return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1709                       Op->getOperand(1));
1710  case Intrinsic::mips_fill_b:
1711  case Intrinsic::mips_fill_h:
1712  case Intrinsic::mips_fill_w:
1713  case Intrinsic::mips_fill_d: {
1714    SmallVector<SDValue, 16> Ops;
1715    EVT ResTy = Op->getValueType(0);
1716
1717    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1718      Ops.push_back(Op->getOperand(1));
1719
1720    // If ResTy is v2i64 then the type legalizer will break this node down into
1721    // an equivalent v4i32.
1722    return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1723  }
1724  case Intrinsic::mips_fexp2_w:
1725  case Intrinsic::mips_fexp2_d: {
1726    EVT ResTy = Op->getValueType(0);
1727    return DAG.getNode(
1728        ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1729        DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1730  }
1731  case Intrinsic::mips_flog2_w:
1732  case Intrinsic::mips_flog2_d:
1733    return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1734  case Intrinsic::mips_fmadd_w:
1735  case Intrinsic::mips_fmadd_d:
1736    return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1737                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1738  case Intrinsic::mips_fmul_w:
1739  case Intrinsic::mips_fmul_d:
1740    return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1741                       Op->getOperand(2));
1742  case Intrinsic::mips_fmsub_w:
1743  case Intrinsic::mips_fmsub_d: {
1744    EVT ResTy = Op->getValueType(0);
1745    return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1746                       DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1747                                   Op->getOperand(2), Op->getOperand(3)));
1748  }
1749  case Intrinsic::mips_frint_w:
1750  case Intrinsic::mips_frint_d:
1751    return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1752  case Intrinsic::mips_fsqrt_w:
1753  case Intrinsic::mips_fsqrt_d:
1754    return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1755  case Intrinsic::mips_fsub_w:
1756  case Intrinsic::mips_fsub_d:
1757    return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1758                       Op->getOperand(2));
1759  case Intrinsic::mips_ftrunc_u_w:
1760  case Intrinsic::mips_ftrunc_u_d:
1761    return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1762                       Op->getOperand(1));
1763  case Intrinsic::mips_ftrunc_s_w:
1764  case Intrinsic::mips_ftrunc_s_d:
1765    return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1766                       Op->getOperand(1));
1767  case Intrinsic::mips_ilvev_b:
1768  case Intrinsic::mips_ilvev_h:
1769  case Intrinsic::mips_ilvev_w:
1770  case Intrinsic::mips_ilvev_d:
1771    return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1772                       Op->getOperand(1), Op->getOperand(2));
1773  case Intrinsic::mips_ilvl_b:
1774  case Intrinsic::mips_ilvl_h:
1775  case Intrinsic::mips_ilvl_w:
1776  case Intrinsic::mips_ilvl_d:
1777    return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1778                       Op->getOperand(1), Op->getOperand(2));
1779  case Intrinsic::mips_ilvod_b:
1780  case Intrinsic::mips_ilvod_h:
1781  case Intrinsic::mips_ilvod_w:
1782  case Intrinsic::mips_ilvod_d:
1783    return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1784                       Op->getOperand(1), Op->getOperand(2));
1785  case Intrinsic::mips_ilvr_b:
1786  case Intrinsic::mips_ilvr_h:
1787  case Intrinsic::mips_ilvr_w:
1788  case Intrinsic::mips_ilvr_d:
1789    return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1790                       Op->getOperand(1), Op->getOperand(2));
1791  case Intrinsic::mips_insert_b:
1792  case Intrinsic::mips_insert_h:
1793  case Intrinsic::mips_insert_w:
1794  case Intrinsic::mips_insert_d:
1795    return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1796                       Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1797  case Intrinsic::mips_ldi_b:
1798  case Intrinsic::mips_ldi_h:
1799  case Intrinsic::mips_ldi_w:
1800  case Intrinsic::mips_ldi_d:
1801    return lowerMSASplatImm(Op, 1, DAG);
1802  case Intrinsic::mips_lsa: {
1803    EVT ResTy = Op->getValueType(0);
1804    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1805                       DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1806                                   Op->getOperand(2), Op->getOperand(3)));
1807  }
1808  case Intrinsic::mips_maddv_b:
1809  case Intrinsic::mips_maddv_h:
1810  case Intrinsic::mips_maddv_w:
1811  case Intrinsic::mips_maddv_d: {
1812    EVT ResTy = Op->getValueType(0);
1813    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1814                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1815                                   Op->getOperand(2), Op->getOperand(3)));
1816  }
1817  case Intrinsic::mips_max_s_b:
1818  case Intrinsic::mips_max_s_h:
1819  case Intrinsic::mips_max_s_w:
1820  case Intrinsic::mips_max_s_d:
1821    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1822                       Op->getOperand(1), Op->getOperand(2));
1823  case Intrinsic::mips_max_u_b:
1824  case Intrinsic::mips_max_u_h:
1825  case Intrinsic::mips_max_u_w:
1826  case Intrinsic::mips_max_u_d:
1827    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1828                       Op->getOperand(1), Op->getOperand(2));
1829  case Intrinsic::mips_maxi_s_b:
1830  case Intrinsic::mips_maxi_s_h:
1831  case Intrinsic::mips_maxi_s_w:
1832  case Intrinsic::mips_maxi_s_d:
1833    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1834                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1835  case Intrinsic::mips_maxi_u_b:
1836  case Intrinsic::mips_maxi_u_h:
1837  case Intrinsic::mips_maxi_u_w:
1838  case Intrinsic::mips_maxi_u_d:
1839    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1840                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1841  case Intrinsic::mips_min_s_b:
1842  case Intrinsic::mips_min_s_h:
1843  case Intrinsic::mips_min_s_w:
1844  case Intrinsic::mips_min_s_d:
1845    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1846                       Op->getOperand(1), Op->getOperand(2));
1847  case Intrinsic::mips_min_u_b:
1848  case Intrinsic::mips_min_u_h:
1849  case Intrinsic::mips_min_u_w:
1850  case Intrinsic::mips_min_u_d:
1851    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1852                       Op->getOperand(1), Op->getOperand(2));
1853  case Intrinsic::mips_mini_s_b:
1854  case Intrinsic::mips_mini_s_h:
1855  case Intrinsic::mips_mini_s_w:
1856  case Intrinsic::mips_mini_s_d:
1857    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1858                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1859  case Intrinsic::mips_mini_u_b:
1860  case Intrinsic::mips_mini_u_h:
1861  case Intrinsic::mips_mini_u_w:
1862  case Intrinsic::mips_mini_u_d:
1863    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1864                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1865  case Intrinsic::mips_mod_s_b:
1866  case Intrinsic::mips_mod_s_h:
1867  case Intrinsic::mips_mod_s_w:
1868  case Intrinsic::mips_mod_s_d:
1869    return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1870                       Op->getOperand(2));
1871  case Intrinsic::mips_mod_u_b:
1872  case Intrinsic::mips_mod_u_h:
1873  case Intrinsic::mips_mod_u_w:
1874  case Intrinsic::mips_mod_u_d:
1875    return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1876                       Op->getOperand(2));
1877  case Intrinsic::mips_mulv_b:
1878  case Intrinsic::mips_mulv_h:
1879  case Intrinsic::mips_mulv_w:
1880  case Intrinsic::mips_mulv_d:
1881    return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1882                       Op->getOperand(2));
1883  case Intrinsic::mips_msubv_b:
1884  case Intrinsic::mips_msubv_h:
1885  case Intrinsic::mips_msubv_w:
1886  case Intrinsic::mips_msubv_d: {
1887    EVT ResTy = Op->getValueType(0);
1888    return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1889                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1890                                   Op->getOperand(2), Op->getOperand(3)));
1891  }
1892  case Intrinsic::mips_nlzc_b:
1893  case Intrinsic::mips_nlzc_h:
1894  case Intrinsic::mips_nlzc_w:
1895  case Intrinsic::mips_nlzc_d:
1896    return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1897  case Intrinsic::mips_nor_v: {
1898    SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1899                              Op->getOperand(1), Op->getOperand(2));
1900    return DAG.getNOT(DL, Res, Res->getValueType(0));
1901  }
1902  case Intrinsic::mips_nori_b: {
1903    SDValue Res =  DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1904                               Op->getOperand(1),
1905                               lowerMSASplatImm(Op, 2, DAG));
1906    return DAG.getNOT(DL, Res, Res->getValueType(0));
1907  }
1908  case Intrinsic::mips_or_v:
1909    return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1910                       Op->getOperand(2));
1911  case Intrinsic::mips_ori_b:
1912    return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1913                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1914  case Intrinsic::mips_pckev_b:
1915  case Intrinsic::mips_pckev_h:
1916  case Intrinsic::mips_pckev_w:
1917  case Intrinsic::mips_pckev_d:
1918    return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1919                       Op->getOperand(1), Op->getOperand(2));
1920  case Intrinsic::mips_pckod_b:
1921  case Intrinsic::mips_pckod_h:
1922  case Intrinsic::mips_pckod_w:
1923  case Intrinsic::mips_pckod_d:
1924    return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1925                       Op->getOperand(1), Op->getOperand(2));
1926  case Intrinsic::mips_pcnt_b:
1927  case Intrinsic::mips_pcnt_h:
1928  case Intrinsic::mips_pcnt_w:
1929  case Intrinsic::mips_pcnt_d:
1930    return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1931  case Intrinsic::mips_shf_b:
1932  case Intrinsic::mips_shf_h:
1933  case Intrinsic::mips_shf_w:
1934    return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1935                       Op->getOperand(2), Op->getOperand(1));
1936  case Intrinsic::mips_sll_b:
1937  case Intrinsic::mips_sll_h:
1938  case Intrinsic::mips_sll_w:
1939  case Intrinsic::mips_sll_d:
1940    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1941                       Op->getOperand(2));
1942  case Intrinsic::mips_slli_b:
1943  case Intrinsic::mips_slli_h:
1944  case Intrinsic::mips_slli_w:
1945  case Intrinsic::mips_slli_d:
1946    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1947                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1948  case Intrinsic::mips_splat_b:
1949  case Intrinsic::mips_splat_h:
1950  case Intrinsic::mips_splat_w:
1951  case Intrinsic::mips_splat_d:
1952    // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1953    // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1954    // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1955    // Instead we lower to MipsISD::VSHF and match from there.
1956    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1957                       lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
1958                       Op->getOperand(1));
1959  case Intrinsic::mips_splati_b:
1960  case Intrinsic::mips_splati_h:
1961  case Intrinsic::mips_splati_w:
1962  case Intrinsic::mips_splati_d:
1963    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1964                       lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1965                       Op->getOperand(1));
1966  case Intrinsic::mips_sra_b:
1967  case Intrinsic::mips_sra_h:
1968  case Intrinsic::mips_sra_w:
1969  case Intrinsic::mips_sra_d:
1970    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1971                       Op->getOperand(2));
1972  case Intrinsic::mips_srai_b:
1973  case Intrinsic::mips_srai_h:
1974  case Intrinsic::mips_srai_w:
1975  case Intrinsic::mips_srai_d:
1976    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1977                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1978  case Intrinsic::mips_srl_b:
1979  case Intrinsic::mips_srl_h:
1980  case Intrinsic::mips_srl_w:
1981  case Intrinsic::mips_srl_d:
1982    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1983                       Op->getOperand(2));
1984  case Intrinsic::mips_srli_b:
1985  case Intrinsic::mips_srli_h:
1986  case Intrinsic::mips_srli_w:
1987  case Intrinsic::mips_srli_d:
1988    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1989                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1990  case Intrinsic::mips_subv_b:
1991  case Intrinsic::mips_subv_h:
1992  case Intrinsic::mips_subv_w:
1993  case Intrinsic::mips_subv_d:
1994    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1995                       Op->getOperand(2));
1996  case Intrinsic::mips_subvi_b:
1997  case Intrinsic::mips_subvi_h:
1998  case Intrinsic::mips_subvi_w:
1999  case Intrinsic::mips_subvi_d:
2000    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2001                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2002  case Intrinsic::mips_vshf_b:
2003  case Intrinsic::mips_vshf_h:
2004  case Intrinsic::mips_vshf_w:
2005  case Intrinsic::mips_vshf_d:
2006    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2007                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
2008  case Intrinsic::mips_xor_v:
2009    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2010                       Op->getOperand(2));
2011  case Intrinsic::mips_xori_b:
2012    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2013                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
2014  }
2015}
2016
2017static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2018  SDLoc DL(Op);
2019  SDValue ChainIn = Op->getOperand(0);
2020  SDValue Address = Op->getOperand(2);
2021  SDValue Offset  = Op->getOperand(3);
2022  EVT ResTy = Op->getValueType(0);
2023  EVT PtrTy = Address->getValueType(0);
2024
2025  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2026
2027  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2028                     false, false, 16);
2029}
2030
2031SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2032                                                     SelectionDAG &DAG) const {
2033  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2034  switch (Intr) {
2035  default:
2036    return SDValue();
2037  case Intrinsic::mips_extp:
2038    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2039  case Intrinsic::mips_extpdp:
2040    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2041  case Intrinsic::mips_extr_w:
2042    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2043  case Intrinsic::mips_extr_r_w:
2044    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2045  case Intrinsic::mips_extr_rs_w:
2046    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2047  case Intrinsic::mips_extr_s_h:
2048    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2049  case Intrinsic::mips_mthlip:
2050    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2051  case Intrinsic::mips_mulsaq_s_w_ph:
2052    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2053  case Intrinsic::mips_maq_s_w_phl:
2054    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2055  case Intrinsic::mips_maq_s_w_phr:
2056    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2057  case Intrinsic::mips_maq_sa_w_phl:
2058    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2059  case Intrinsic::mips_maq_sa_w_phr:
2060    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2061  case Intrinsic::mips_dpaq_s_w_ph:
2062    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2063  case Intrinsic::mips_dpsq_s_w_ph:
2064    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2065  case Intrinsic::mips_dpaq_sa_l_w:
2066    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2067  case Intrinsic::mips_dpsq_sa_l_w:
2068    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2069  case Intrinsic::mips_dpaqx_s_w_ph:
2070    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2071  case Intrinsic::mips_dpaqx_sa_w_ph:
2072    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2073  case Intrinsic::mips_dpsqx_s_w_ph:
2074    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2075  case Intrinsic::mips_dpsqx_sa_w_ph:
2076    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2077  case Intrinsic::mips_ld_b:
2078  case Intrinsic::mips_ld_h:
2079  case Intrinsic::mips_ld_w:
2080  case Intrinsic::mips_ld_d:
2081   return lowerMSALoadIntr(Op, DAG, Intr);
2082  }
2083}
2084
2085static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2086  SDLoc DL(Op);
2087  SDValue ChainIn = Op->getOperand(0);
2088  SDValue Value   = Op->getOperand(2);
2089  SDValue Address = Op->getOperand(3);
2090  SDValue Offset  = Op->getOperand(4);
2091  EVT PtrTy = Address->getValueType(0);
2092
2093  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2094
2095  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2096                      false, 16);
2097}
2098
2099SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2100                                                  SelectionDAG &DAG) const {
2101  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2102  switch (Intr) {
2103  default:
2104    return SDValue();
2105  case Intrinsic::mips_st_b:
2106  case Intrinsic::mips_st_h:
2107  case Intrinsic::mips_st_w:
2108  case Intrinsic::mips_st_d:
2109    return lowerMSAStoreIntr(Op, DAG, Intr);
2110  }
2111}
2112
2113/// \brief Check if the given BuildVectorSDNode is a splat.
2114/// This method currently relies on DAG nodes being reused when equivalent,
2115/// so it's possible for this to return false even when isConstantSplat returns
2116/// true.
2117static bool isSplatVector(const BuildVectorSDNode *N) {
2118  unsigned int nOps = N->getNumOperands();
2119  assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2120
2121  SDValue Operand0 = N->getOperand(0);
2122
2123  for (unsigned int i = 1; i < nOps; ++i) {
2124    if (N->getOperand(i) != Operand0)
2125      return false;
2126  }
2127
2128  return true;
2129}
2130
2131// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2132//
2133// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2134// choose to sign-extend but we could have equally chosen zero-extend. The
2135// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2136// result into this node later (possibly changing it to a zero-extend in the
2137// process).
2138SDValue MipsSETargetLowering::
2139lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2140  SDLoc DL(Op);
2141  EVT ResTy = Op->getValueType(0);
2142  SDValue Op0 = Op->getOperand(0);
2143  EVT VecTy = Op0->getValueType(0);
2144
2145  if (!VecTy.is128BitVector())
2146    return SDValue();
2147
2148  if (ResTy.isInteger()) {
2149    SDValue Op1 = Op->getOperand(1);
2150    EVT EltTy = VecTy.getVectorElementType();
2151    return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2152                       DAG.getValueType(EltTy));
2153  }
2154
2155  return Op;
2156}
2157
2158static bool isConstantOrUndef(const SDValue Op) {
2159  if (Op->getOpcode() == ISD::UNDEF)
2160    return true;
2161  if (dyn_cast<ConstantSDNode>(Op))
2162    return true;
2163  if (dyn_cast<ConstantFPSDNode>(Op))
2164    return true;
2165  return false;
2166}
2167
2168static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2169  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2170    if (isConstantOrUndef(Op->getOperand(i)))
2171      return true;
2172  return false;
2173}
2174
2175// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2176// backend.
2177//
2178// Lowers according to the following rules:
2179// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2180//   2 less than or equal to 64 and the value fits into a signed 10-bit
2181//   immediate
2182// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2183//   is a power of 2 less than or equal to 64 and the value does not fit into a
2184//   signed 10-bit immediate
2185// - Non-constant splats are legal as-is.
2186// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2187// - All others are illegal and must be expanded.
2188SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2189                                                SelectionDAG &DAG) const {
2190  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2191  EVT ResTy = Op->getValueType(0);
2192  SDLoc DL(Op);
2193  APInt SplatValue, SplatUndef;
2194  unsigned SplatBitSize;
2195  bool HasAnyUndefs;
2196
2197  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2198    return SDValue();
2199
2200  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2201                            HasAnyUndefs, 8,
2202                            !Subtarget->isLittle()) && SplatBitSize <= 64) {
2203    // We can only cope with 8, 16, 32, or 64-bit elements
2204    if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2205        SplatBitSize != 64)
2206      return SDValue();
2207
2208    // If the value fits into a simm10 then we can use ldi.[bhwd]
2209    if (SplatValue.isSignedIntN(10))
2210      return Op;
2211
2212    EVT ViaVecTy;
2213
2214    switch (SplatBitSize) {
2215    default:
2216      return SDValue();
2217    case 8:
2218      ViaVecTy = MVT::v16i8;
2219      break;
2220    case 16:
2221      ViaVecTy = MVT::v8i16;
2222      break;
2223    case 32:
2224      ViaVecTy = MVT::v4i32;
2225      break;
2226    case 64:
2227      // There's no fill.d to fall back on for 64-bit values
2228      return SDValue();
2229    }
2230
2231    // SelectionDAG::getConstant will promote SplatValue appropriately.
2232    SDValue Result = DAG.getConstant(SplatValue, ViaVecTy);
2233
2234    // Bitcast to the type we originally wanted
2235    if (ViaVecTy != ResTy)
2236      Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2237
2238    return Result;
2239  } else if (isSplatVector(Node))
2240    return Op;
2241  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2242    // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2243    // The resulting code is the same length as the expansion, but it doesn't
2244    // use memory operations
2245    EVT ResTy = Node->getValueType(0);
2246
2247    assert(ResTy.isVector());
2248
2249    unsigned NumElts = ResTy.getVectorNumElements();
2250    SDValue Vector = DAG.getUNDEF(ResTy);
2251    for (unsigned i = 0; i < NumElts; ++i) {
2252      Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2253                           Node->getOperand(i),
2254                           DAG.getConstant(i, MVT::i32));
2255    }
2256    return Vector;
2257  }
2258
2259  return SDValue();
2260}
2261
2262// Lower VECTOR_SHUFFLE into SHF (if possible).
2263//
2264// SHF splits the vector into blocks of four elements, then shuffles these
2265// elements according to a <4 x i2> constant (encoded as an integer immediate).
2266//
2267// It is therefore possible to lower into SHF when the mask takes the form:
2268//   <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2269// When undef's appear they are treated as if they were whatever value is
2270// necessary in order to fit the above form.
2271//
2272// For example:
2273//   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2274//                      <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2275//                                 i32 7, i32 6, i32 5, i32 4>
2276// is lowered to:
2277//   (SHF_H $w0, $w1, 27)
2278// where the 27 comes from:
2279//   3 + (2 << 2) + (1 << 4) + (0 << 6)
2280static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2281                                       SmallVector<int, 16> Indices,
2282                                       SelectionDAG &DAG) {
2283  int SHFIndices[4] = { -1, -1, -1, -1 };
2284
2285  if (Indices.size() < 4)
2286    return SDValue();
2287
2288  for (unsigned i = 0; i < 4; ++i) {
2289    for (unsigned j = i; j < Indices.size(); j += 4) {
2290      int Idx = Indices[j];
2291
2292      // Convert from vector index to 4-element subvector index
2293      // If an index refers to an element outside of the subvector then give up
2294      if (Idx != -1) {
2295        Idx -= 4 * (j / 4);
2296        if (Idx < 0 || Idx >= 4)
2297          return SDValue();
2298      }
2299
2300      // If the mask has an undef, replace it with the current index.
2301      // Note that it might still be undef if the current index is also undef
2302      if (SHFIndices[i] == -1)
2303        SHFIndices[i] = Idx;
2304
2305      // Check that non-undef values are the same as in the mask. If they
2306      // aren't then give up
2307      if (!(Idx == -1 || Idx == SHFIndices[i]))
2308        return SDValue();
2309    }
2310  }
2311
2312  // Calculate the immediate. Replace any remaining undefs with zero
2313  APInt Imm(32, 0);
2314  for (int i = 3; i >= 0; --i) {
2315    int Idx = SHFIndices[i];
2316
2317    if (Idx == -1)
2318      Idx = 0;
2319
2320    Imm <<= 2;
2321    Imm |= Idx & 0x3;
2322  }
2323
2324  return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2325                     DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2326}
2327
2328// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2329//
2330// ILVEV interleaves the even elements from each vector.
2331//
2332// It is possible to lower into ILVEV when the mask takes the form:
2333//   <0, n, 2, n+2, 4, n+4, ...>
2334// where n is the number of elements in the vector.
2335//
2336// When undef's appear in the mask they are treated as if they were whatever
2337// value is necessary in order to fit the above form.
2338static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2339                                         SmallVector<int, 16> Indices,
2340                                         SelectionDAG &DAG) {
2341  assert ((Indices.size() % 2) == 0);
2342  int WsIdx = 0;
2343  int WtIdx = ResTy.getVectorNumElements();
2344
2345  for (unsigned i = 0; i < Indices.size(); i += 2) {
2346    if (Indices[i] != -1 && Indices[i] != WsIdx)
2347      return SDValue();
2348    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2349      return SDValue();
2350    WsIdx += 2;
2351    WtIdx += 2;
2352  }
2353
2354  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2355                     Op->getOperand(1));
2356}
2357
2358// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2359//
2360// ILVOD interleaves the odd elements from each vector.
2361//
2362// It is possible to lower into ILVOD when the mask takes the form:
2363//   <1, n+1, 3, n+3, 5, n+5, ...>
2364// where n is the number of elements in the vector.
2365//
2366// When undef's appear in the mask they are treated as if they were whatever
2367// value is necessary in order to fit the above form.
2368static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2369                                         SmallVector<int, 16> Indices,
2370                                         SelectionDAG &DAG) {
2371  assert ((Indices.size() % 2) == 0);
2372  int WsIdx = 1;
2373  int WtIdx = ResTy.getVectorNumElements() + 1;
2374
2375  for (unsigned i = 0; i < Indices.size(); i += 2) {
2376    if (Indices[i] != -1 && Indices[i] != WsIdx)
2377      return SDValue();
2378    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2379      return SDValue();
2380    WsIdx += 2;
2381    WtIdx += 2;
2382  }
2383
2384  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2385                     Op->getOperand(1));
2386}
2387
2388// Lower VECTOR_SHUFFLE into ILVL (if possible).
2389//
2390// ILVL interleaves consecutive elements from the left half of each vector.
2391//
2392// It is possible to lower into ILVL when the mask takes the form:
2393//   <0, n, 1, n+1, 2, n+2, ...>
2394// where n is the number of elements in the vector.
2395//
2396// When undef's appear in the mask they are treated as if they were whatever
2397// value is necessary in order to fit the above form.
2398static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2399                                        SmallVector<int, 16> Indices,
2400                                        SelectionDAG &DAG) {
2401  assert ((Indices.size() % 2) == 0);
2402  int WsIdx = 0;
2403  int WtIdx = ResTy.getVectorNumElements();
2404
2405  for (unsigned i = 0; i < Indices.size(); i += 2) {
2406    if (Indices[i] != -1 && Indices[i] != WsIdx)
2407      return SDValue();
2408    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2409      return SDValue();
2410    WsIdx ++;
2411    WtIdx ++;
2412  }
2413
2414  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2415                     Op->getOperand(1));
2416}
2417
2418// Lower VECTOR_SHUFFLE into ILVR (if possible).
2419//
2420// ILVR interleaves consecutive elements from the right half of each vector.
2421//
2422// It is possible to lower into ILVR when the mask takes the form:
2423//   <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2424// where n is the number of elements in the vector and x is half n.
2425//
2426// When undef's appear in the mask they are treated as if they were whatever
2427// value is necessary in order to fit the above form.
2428static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2429                                        SmallVector<int, 16> Indices,
2430                                        SelectionDAG &DAG) {
2431  assert ((Indices.size() % 2) == 0);
2432  unsigned NumElts = ResTy.getVectorNumElements();
2433  int WsIdx = NumElts / 2;
2434  int WtIdx = NumElts + NumElts / 2;
2435
2436  for (unsigned i = 0; i < Indices.size(); i += 2) {
2437    if (Indices[i] != -1 && Indices[i] != WsIdx)
2438      return SDValue();
2439    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2440      return SDValue();
2441    WsIdx ++;
2442    WtIdx ++;
2443  }
2444
2445  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2446                     Op->getOperand(1));
2447}
2448
2449// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2450//
2451// PCKEV copies the even elements of each vector into the result vector.
2452//
2453// It is possible to lower into PCKEV when the mask takes the form:
2454//   <0, 2, 4, ..., n, n+2, n+4, ...>
2455// where n is the number of elements in the vector.
2456//
2457// When undef's appear in the mask they are treated as if they were whatever
2458// value is necessary in order to fit the above form.
2459static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2460                                         SmallVector<int, 16> Indices,
2461                                         SelectionDAG &DAG) {
2462  assert ((Indices.size() % 2) == 0);
2463  int Idx = 0;
2464
2465  for (unsigned i = 0; i < Indices.size(); ++i) {
2466    if (Indices[i] != -1 && Indices[i] != Idx)
2467      return SDValue();
2468    Idx += 2;
2469  }
2470
2471  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2472                     Op->getOperand(1));
2473}
2474
2475// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2476//
2477// PCKOD copies the odd elements of each vector into the result vector.
2478//
2479// It is possible to lower into PCKOD when the mask takes the form:
2480//   <1, 3, 5, ..., n+1, n+3, n+5, ...>
2481// where n is the number of elements in the vector.
2482//
2483// When undef's appear in the mask they are treated as if they were whatever
2484// value is necessary in order to fit the above form.
2485static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2486                                         SmallVector<int, 16> Indices,
2487                                         SelectionDAG &DAG) {
2488  assert ((Indices.size() % 2) == 0);
2489  int Idx = 1;
2490
2491  for (unsigned i = 0; i < Indices.size(); ++i) {
2492    if (Indices[i] != -1 && Indices[i] != Idx)
2493      return SDValue();
2494    Idx += 2;
2495  }
2496
2497  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2498                     Op->getOperand(1));
2499}
2500
2501// Lower VECTOR_SHUFFLE into VSHF.
2502//
2503// This mostly consists of converting the shuffle indices in Indices into a
2504// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2505// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2506// if the type is v8i16 and all the indices are less than 8 then the second
2507// operand is unused and can be replaced with anything. We choose to replace it
2508// with the used operand since this reduces the number of instructions overall.
2509static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2510                                        SmallVector<int, 16> Indices,
2511                                        SelectionDAG &DAG) {
2512  SmallVector<SDValue, 16> Ops;
2513  SDValue Op0;
2514  SDValue Op1;
2515  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2516  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2517  bool Using1stVec = false;
2518  bool Using2ndVec = false;
2519  SDLoc DL(Op);
2520  int ResTyNumElts = ResTy.getVectorNumElements();
2521
2522  for (int i = 0; i < ResTyNumElts; ++i) {
2523    // Idx == -1 means UNDEF
2524    int Idx = Indices[i];
2525
2526    if (0 <= Idx && Idx < ResTyNumElts)
2527      Using1stVec = true;
2528    if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2529      Using2ndVec = true;
2530  }
2531
2532  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2533       ++I)
2534    Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2535
2536  SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2537                                Ops.size());
2538
2539  if (Using1stVec && Using2ndVec) {
2540    Op0 = Op->getOperand(0);
2541    Op1 = Op->getOperand(1);
2542  } else if (Using1stVec)
2543    Op0 = Op1 = Op->getOperand(0);
2544  else if (Using2ndVec)
2545    Op0 = Op1 = Op->getOperand(1);
2546  else
2547    llvm_unreachable("shuffle vector mask references neither vector operand?");
2548
2549  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2550}
2551
2552// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2553// indices in the shuffle.
2554SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2555                                                  SelectionDAG &DAG) const {
2556  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2557  EVT ResTy = Op->getValueType(0);
2558
2559  if (!ResTy.is128BitVector())
2560    return SDValue();
2561
2562  int ResTyNumElts = ResTy.getVectorNumElements();
2563  SmallVector<int, 16> Indices;
2564
2565  for (int i = 0; i < ResTyNumElts; ++i)
2566    Indices.push_back(Node->getMaskElt(i));
2567
2568  SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2569  if (Result.getNode())
2570    return Result;
2571  Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2572  if (Result.getNode())
2573    return Result;
2574  Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2575  if (Result.getNode())
2576    return Result;
2577  Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2578  if (Result.getNode())
2579    return Result;
2580  Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2581  if (Result.getNode())
2582    return Result;
2583  Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2584  if (Result.getNode())
2585    return Result;
2586  Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2587  if (Result.getNode())
2588    return Result;
2589  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2590}
2591
2592MachineBasicBlock * MipsSETargetLowering::
2593emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2594  // $bb:
2595  //  bposge32_pseudo $vr0
2596  //  =>
2597  // $bb:
2598  //  bposge32 $tbb
2599  // $fbb:
2600  //  li $vr2, 0
2601  //  b $sink
2602  // $tbb:
2603  //  li $vr1, 1
2604  // $sink:
2605  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2606
2607  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2608  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2609  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2610  DebugLoc DL = MI->getDebugLoc();
2611  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2612  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2613  MachineFunction *F = BB->getParent();
2614  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2615  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2616  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2617  F->insert(It, FBB);
2618  F->insert(It, TBB);
2619  F->insert(It, Sink);
2620
2621  // Transfer the remainder of BB and its successor edges to Sink.
2622  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2623               BB->end());
2624  Sink->transferSuccessorsAndUpdatePHIs(BB);
2625
2626  // Add successors.
2627  BB->addSuccessor(FBB);
2628  BB->addSuccessor(TBB);
2629  FBB->addSuccessor(Sink);
2630  TBB->addSuccessor(Sink);
2631
2632  // Insert the real bposge32 instruction to $BB.
2633  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2634
2635  // Fill $FBB.
2636  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2637  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2638    .addReg(Mips::ZERO).addImm(0);
2639  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2640
2641  // Fill $TBB.
2642  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2643  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2644    .addReg(Mips::ZERO).addImm(1);
2645
2646  // Insert phi function to $Sink.
2647  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2648          MI->getOperand(0).getReg())
2649    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2650
2651  MI->eraseFromParent();   // The pseudo instruction is gone now.
2652  return Sink;
2653}
2654
2655MachineBasicBlock * MipsSETargetLowering::
2656emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2657                     unsigned BranchOp) const{
2658  // $bb:
2659  //  vany_nonzero $rd, $ws
2660  //  =>
2661  // $bb:
2662  //  bnz.b $ws, $tbb
2663  //  b $fbb
2664  // $fbb:
2665  //  li $rd1, 0
2666  //  b $sink
2667  // $tbb:
2668  //  li $rd2, 1
2669  // $sink:
2670  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
2671
2672  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2673  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2674  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2675  DebugLoc DL = MI->getDebugLoc();
2676  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2677  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2678  MachineFunction *F = BB->getParent();
2679  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2680  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2681  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2682  F->insert(It, FBB);
2683  F->insert(It, TBB);
2684  F->insert(It, Sink);
2685
2686  // Transfer the remainder of BB and its successor edges to Sink.
2687  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2688               BB->end());
2689  Sink->transferSuccessorsAndUpdatePHIs(BB);
2690
2691  // Add successors.
2692  BB->addSuccessor(FBB);
2693  BB->addSuccessor(TBB);
2694  FBB->addSuccessor(Sink);
2695  TBB->addSuccessor(Sink);
2696
2697  // Insert the real bnz.b instruction to $BB.
2698  BuildMI(BB, DL, TII->get(BranchOp))
2699    .addReg(MI->getOperand(1).getReg())
2700    .addMBB(TBB);
2701
2702  // Fill $FBB.
2703  unsigned RD1 = RegInfo.createVirtualRegister(RC);
2704  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2705    .addReg(Mips::ZERO).addImm(0);
2706  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2707
2708  // Fill $TBB.
2709  unsigned RD2 = RegInfo.createVirtualRegister(RC);
2710  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2711    .addReg(Mips::ZERO).addImm(1);
2712
2713  // Insert phi function to $Sink.
2714  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2715          MI->getOperand(0).getReg())
2716    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2717
2718  MI->eraseFromParent();   // The pseudo instruction is gone now.
2719  return Sink;
2720}
2721
2722// Emit the COPY_FW pseudo instruction.
2723//
2724// copy_fw_pseudo $fd, $ws, n
2725// =>
2726// copy_u_w $rt, $ws, $n
2727// mtc1     $rt, $fd
2728//
2729// When n is zero, the equivalent operation can be performed with (potentially)
2730// zero instructions due to register overlaps. This optimization is never valid
2731// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2732MachineBasicBlock * MipsSETargetLowering::
2733emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2734  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2735  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2736  DebugLoc DL = MI->getDebugLoc();
2737  unsigned Fd = MI->getOperand(0).getReg();
2738  unsigned Ws = MI->getOperand(1).getReg();
2739  unsigned Lane = MI->getOperand(2).getImm();
2740
2741  if (Lane == 0)
2742    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2743  else {
2744    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2745
2746    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2747    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2748  }
2749
2750  MI->eraseFromParent();   // The pseudo instruction is gone now.
2751  return BB;
2752}
2753
2754// Emit the COPY_FD pseudo instruction.
2755//
2756// copy_fd_pseudo $fd, $ws, n
2757// =>
2758// splati.d $wt, $ws, $n
2759// copy $fd, $wt:sub_64
2760//
2761// When n is zero, the equivalent operation can be performed with (potentially)
2762// zero instructions due to register overlaps. This optimization is always
2763// valid because FR=1 mode which is the only supported mode in MSA.
2764MachineBasicBlock * MipsSETargetLowering::
2765emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2766  assert(Subtarget->isFP64bit());
2767
2768  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2769  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2770  unsigned Fd  = MI->getOperand(0).getReg();
2771  unsigned Ws  = MI->getOperand(1).getReg();
2772  unsigned Lane = MI->getOperand(2).getImm() * 2;
2773  DebugLoc DL = MI->getDebugLoc();
2774
2775  if (Lane == 0)
2776    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2777  else {
2778    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2779
2780    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2781    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2782  }
2783
2784  MI->eraseFromParent();   // The pseudo instruction is gone now.
2785  return BB;
2786}
2787
2788// Emit the INSERT_FW pseudo instruction.
2789//
2790// insert_fw_pseudo $wd, $wd_in, $n, $fs
2791// =>
2792// subreg_to_reg $wt:sub_lo, $fs
2793// insve_w $wd[$n], $wd_in, $wt[0]
2794MachineBasicBlock *
2795MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2796                                    MachineBasicBlock *BB) const {
2797  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2798  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2799  DebugLoc DL = MI->getDebugLoc();
2800  unsigned Wd = MI->getOperand(0).getReg();
2801  unsigned Wd_in = MI->getOperand(1).getReg();
2802  unsigned Lane = MI->getOperand(2).getImm();
2803  unsigned Fs = MI->getOperand(3).getReg();
2804  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2805
2806  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2807      .addImm(0)
2808      .addReg(Fs)
2809      .addImm(Mips::sub_lo);
2810  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2811      .addReg(Wd_in)
2812      .addImm(Lane)
2813      .addReg(Wt);
2814
2815  MI->eraseFromParent(); // The pseudo instruction is gone now.
2816  return BB;
2817}
2818
2819// Emit the INSERT_FD pseudo instruction.
2820//
2821// insert_fd_pseudo $wd, $fs, n
2822// =>
2823// subreg_to_reg $wt:sub_64, $fs
2824// insve_d $wd[$n], $wd_in, $wt[0]
2825MachineBasicBlock *
2826MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2827                                    MachineBasicBlock *BB) const {
2828  assert(Subtarget->isFP64bit());
2829
2830  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2831  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2832  DebugLoc DL = MI->getDebugLoc();
2833  unsigned Wd = MI->getOperand(0).getReg();
2834  unsigned Wd_in = MI->getOperand(1).getReg();
2835  unsigned Lane = MI->getOperand(2).getImm();
2836  unsigned Fs = MI->getOperand(3).getReg();
2837  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2838
2839  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2840      .addImm(0)
2841      .addReg(Fs)
2842      .addImm(Mips::sub_64);
2843  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2844      .addReg(Wd_in)
2845      .addImm(Lane)
2846      .addReg(Wt);
2847
2848  MI->eraseFromParent(); // The pseudo instruction is gone now.
2849  return BB;
2850}
2851
2852// Emit the FILL_FW pseudo instruction.
2853//
2854// fill_fw_pseudo $wd, $fs
2855// =>
2856// implicit_def $wt1
2857// insert_subreg $wt2:subreg_lo, $wt1, $fs
2858// splati.w $wd, $wt2[0]
2859MachineBasicBlock *
2860MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2861                                  MachineBasicBlock *BB) const {
2862  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2863  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2864  DebugLoc DL = MI->getDebugLoc();
2865  unsigned Wd = MI->getOperand(0).getReg();
2866  unsigned Fs = MI->getOperand(1).getReg();
2867  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2868  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2869
2870  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2871  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2872      .addReg(Wt1)
2873      .addReg(Fs)
2874      .addImm(Mips::sub_lo);
2875  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2876
2877  MI->eraseFromParent(); // The pseudo instruction is gone now.
2878  return BB;
2879}
2880
2881// Emit the FILL_FD pseudo instruction.
2882//
2883// fill_fd_pseudo $wd, $fs
2884// =>
2885// implicit_def $wt1
2886// insert_subreg $wt2:subreg_64, $wt1, $fs
2887// splati.d $wd, $wt2[0]
2888MachineBasicBlock *
2889MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2890                                  MachineBasicBlock *BB) const {
2891  assert(Subtarget->isFP64bit());
2892
2893  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2894  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2895  DebugLoc DL = MI->getDebugLoc();
2896  unsigned Wd = MI->getOperand(0).getReg();
2897  unsigned Fs = MI->getOperand(1).getReg();
2898  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2899  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2900
2901  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2902  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2903      .addReg(Wt1)
2904      .addReg(Fs)
2905      .addImm(Mips::sub_64);
2906  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2907
2908  MI->eraseFromParent();   // The pseudo instruction is gone now.
2909  return BB;
2910}
2911
2912// Emit the FEXP2_W_1 pseudo instructions.
2913//
2914// fexp2_w_1_pseudo $wd, $wt
2915// =>
2916// ldi.w $ws, 1
2917// fexp2.w $wd, $ws, $wt
2918MachineBasicBlock *
2919MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2920                                    MachineBasicBlock *BB) const {
2921  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2922  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2923  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2924  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2925  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2926  DebugLoc DL = MI->getDebugLoc();
2927
2928  // Splat 1.0 into a vector
2929  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2930  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2931
2932  // Emit 1.0 * fexp2(Wt)
2933  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2934      .addReg(Ws2)
2935      .addReg(MI->getOperand(1).getReg());
2936
2937  MI->eraseFromParent(); // The pseudo instruction is gone now.
2938  return BB;
2939}
2940
2941// Emit the FEXP2_D_1 pseudo instructions.
2942//
2943// fexp2_d_1_pseudo $wd, $wt
2944// =>
2945// ldi.d $ws, 1
2946// fexp2.d $wd, $ws, $wt
2947MachineBasicBlock *
2948MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2949                                    MachineBasicBlock *BB) const {
2950  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2951  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2952  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2953  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2954  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2955  DebugLoc DL = MI->getDebugLoc();
2956
2957  // Splat 1.0 into a vector
2958  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2959  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2960
2961  // Emit 1.0 * fexp2(Wt)
2962  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2963      .addReg(Ws2)
2964      .addReg(MI->getOperand(1).getReg());
2965
2966  MI->eraseFromParent(); // The pseudo instruction is gone now.
2967  return BB;
2968}
2969