MipsSEISelLowering.cpp revision 92e94a2ee44aefda151125fdb62bf9d5b54edfb2 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#define DEBUG_TYPE "mips-isel"
14#include "MipsSEISelLowering.h"
15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/IR/Intrinsics.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
27static cl::opt<bool>
28EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
29                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
30
31static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
32                                   cl::desc("Expand double precision loads and "
33                                            "stores to their single precision "
34                                            "counterparts"));
35
36MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
37  : MipsTargetLowering(TM) {
38  // Set up the register classes
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
45    // Expand all truncating stores and extending loads.
46    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
47    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
48
49    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
50      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
51        setTruncStoreAction((MVT::SimpleValueType)VT0,
52                            (MVT::SimpleValueType)VT1, Expand);
53
54      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
55      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
56      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
57    }
58  }
59
60  if (Subtarget->hasDSP()) {
61    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
62
63    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
64      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
65
66      // Expand all builtin opcodes.
67      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
68        setOperationAction(Opc, VecTys[i], Expand);
69
70      setOperationAction(ISD::ADD, VecTys[i], Legal);
71      setOperationAction(ISD::SUB, VecTys[i], Legal);
72      setOperationAction(ISD::LOAD, VecTys[i], Legal);
73      setOperationAction(ISD::STORE, VecTys[i], Legal);
74      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
75    }
76
77    setTargetDAGCombine(ISD::SHL);
78    setTargetDAGCombine(ISD::SRA);
79    setTargetDAGCombine(ISD::SRL);
80    setTargetDAGCombine(ISD::SETCC);
81    setTargetDAGCombine(ISD::VSELECT);
82  }
83
84  if (Subtarget->hasDSPR2())
85    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
86
87  if (Subtarget->hasMSA()) {
88    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
89    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
90    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
91    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
92    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
93    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
94    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
95
96    setTargetDAGCombine(ISD::AND);
97    setTargetDAGCombine(ISD::OR);
98    setTargetDAGCombine(ISD::SRA);
99    setTargetDAGCombine(ISD::VSELECT);
100    setTargetDAGCombine(ISD::XOR);
101  }
102
103  if (!Subtarget->mipsSEUsesSoftFloat()) {
104    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
105
106    // When dealing with single precision only, use libcalls
107    if (!Subtarget->isSingleFloat()) {
108      if (Subtarget->isFP64bit())
109        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110      else
111        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
112    }
113  }
114
115  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
116  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
117  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
118  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
119
120  if (HasMips64) {
121    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
122    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
123    setOperationAction(ISD::MUL,              MVT::i64, Custom);
124  }
125
126  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
127  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
128
129  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
130  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
131  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
132  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
133  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
134  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
135  setOperationAction(ISD::STORE,              MVT::i32, Custom);
136
137  setTargetDAGCombine(ISD::ADDE);
138  setTargetDAGCombine(ISD::SUBE);
139  setTargetDAGCombine(ISD::MUL);
140
141  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
142  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
143  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
144
145  if (NoDPLoadStore) {
146    setOperationAction(ISD::LOAD, MVT::f64, Custom);
147    setOperationAction(ISD::STORE, MVT::f64, Custom);
148  }
149
150  computeRegisterProperties();
151}
152
153const MipsTargetLowering *
154llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
155  return new MipsSETargetLowering(TM);
156}
157
158// Enable MSA support for the given integer type and Register class.
159void MipsSETargetLowering::
160addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
161  addRegisterClass(Ty, RC);
162
163  // Expand all builtin opcodes.
164  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
165    setOperationAction(Opc, Ty, Expand);
166
167  setOperationAction(ISD::BITCAST, Ty, Legal);
168  setOperationAction(ISD::LOAD, Ty, Legal);
169  setOperationAction(ISD::STORE, Ty, Legal);
170  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
171  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
172  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
173
174  setOperationAction(ISD::ADD, Ty, Legal);
175  setOperationAction(ISD::AND, Ty, Legal);
176  setOperationAction(ISD::CTLZ, Ty, Legal);
177  setOperationAction(ISD::CTPOP, Ty, Legal);
178  setOperationAction(ISD::MUL, Ty, Legal);
179  setOperationAction(ISD::OR, Ty, Legal);
180  setOperationAction(ISD::SDIV, Ty, Legal);
181  setOperationAction(ISD::SREM, Ty, Legal);
182  setOperationAction(ISD::SHL, Ty, Legal);
183  setOperationAction(ISD::SRA, Ty, Legal);
184  setOperationAction(ISD::SRL, Ty, Legal);
185  setOperationAction(ISD::SUB, Ty, Legal);
186  setOperationAction(ISD::UDIV, Ty, Legal);
187  setOperationAction(ISD::UREM, Ty, Legal);
188  setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
189  setOperationAction(ISD::VSELECT, Ty, Legal);
190  setOperationAction(ISD::XOR, Ty, Legal);
191
192  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
193    setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
194    setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
195    setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
196    setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
197  }
198
199  setOperationAction(ISD::SETCC, Ty, Legal);
200  setCondCodeAction(ISD::SETNE, Ty, Expand);
201  setCondCodeAction(ISD::SETGE, Ty, Expand);
202  setCondCodeAction(ISD::SETGT, Ty, Expand);
203  setCondCodeAction(ISD::SETUGE, Ty, Expand);
204  setCondCodeAction(ISD::SETUGT, Ty, Expand);
205}
206
207// Enable MSA support for the given floating-point type and Register class.
208void MipsSETargetLowering::
209addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
210  addRegisterClass(Ty, RC);
211
212  // Expand all builtin opcodes.
213  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
214    setOperationAction(Opc, Ty, Expand);
215
216  setOperationAction(ISD::LOAD, Ty, Legal);
217  setOperationAction(ISD::STORE, Ty, Legal);
218  setOperationAction(ISD::BITCAST, Ty, Legal);
219  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
220  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
221  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
222
223  if (Ty != MVT::v8f16) {
224    setOperationAction(ISD::FABS,  Ty, Legal);
225    setOperationAction(ISD::FADD,  Ty, Legal);
226    setOperationAction(ISD::FDIV,  Ty, Legal);
227    setOperationAction(ISD::FEXP2, Ty, Legal);
228    setOperationAction(ISD::FLOG2, Ty, Legal);
229    setOperationAction(ISD::FMA,   Ty, Legal);
230    setOperationAction(ISD::FMUL,  Ty, Legal);
231    setOperationAction(ISD::FRINT, Ty, Legal);
232    setOperationAction(ISD::FSQRT, Ty, Legal);
233    setOperationAction(ISD::FSUB,  Ty, Legal);
234    setOperationAction(ISD::VSELECT, Ty, Legal);
235
236    setOperationAction(ISD::SETCC, Ty, Legal);
237    setCondCodeAction(ISD::SETOGE, Ty, Expand);
238    setCondCodeAction(ISD::SETOGT, Ty, Expand);
239    setCondCodeAction(ISD::SETUGE, Ty, Expand);
240    setCondCodeAction(ISD::SETUGT, Ty, Expand);
241    setCondCodeAction(ISD::SETGE,  Ty, Expand);
242    setCondCodeAction(ISD::SETGT,  Ty, Expand);
243  }
244}
245
246bool
247MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
248  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
249
250  switch (SVT) {
251  case MVT::i64:
252  case MVT::i32:
253    if (Fast)
254      *Fast = true;
255    return true;
256  default:
257    return false;
258  }
259}
260
261SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
262                                             SelectionDAG &DAG) const {
263  switch(Op.getOpcode()) {
264  case ISD::LOAD:  return lowerLOAD(Op, DAG);
265  case ISD::STORE: return lowerSTORE(Op, DAG);
266  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
267  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
268  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
269  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
270  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
271  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
272  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
273                                          DAG);
274  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
275  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
276  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
277  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
278  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
279  case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);
280  }
281
282  return MipsTargetLowering::LowerOperation(Op, DAG);
283}
284
285// selectMADD -
286// Transforms a subgraph in CurDAG if the following pattern is found:
287//  (addc multLo, Lo0), (adde multHi, Hi0),
288// where,
289//  multHi/Lo: product of multiplication
290//  Lo0: initial value of Lo register
291//  Hi0: initial value of Hi register
292// Return true if pattern matching was successful.
293static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
294  // ADDENode's second operand must be a flag output of an ADDC node in order
295  // for the matching to be successful.
296  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
297
298  if (ADDCNode->getOpcode() != ISD::ADDC)
299    return false;
300
301  SDValue MultHi = ADDENode->getOperand(0);
302  SDValue MultLo = ADDCNode->getOperand(0);
303  SDNode *MultNode = MultHi.getNode();
304  unsigned MultOpc = MultHi.getOpcode();
305
306  // MultHi and MultLo must be generated by the same node,
307  if (MultLo.getNode() != MultNode)
308    return false;
309
310  // and it must be a multiplication.
311  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
312    return false;
313
314  // MultLo amd MultHi must be the first and second output of MultNode
315  // respectively.
316  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
317    return false;
318
319  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
320  // of the values of MultNode, in which case MultNode will be removed in later
321  // phases.
322  // If there exist users other than ADDENode or ADDCNode, this function returns
323  // here, which will result in MultNode being mapped to a single MULT
324  // instruction node rather than a pair of MULT and MADD instructions being
325  // produced.
326  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
327    return false;
328
329  SDLoc DL(ADDENode);
330
331  // Initialize accumulator.
332  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
333                                  ADDCNode->getOperand(1),
334                                  ADDENode->getOperand(1));
335
336  // create MipsMAdd(u) node
337  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
338
339  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
340                                 MultNode->getOperand(0),// Factor 0
341                                 MultNode->getOperand(1),// Factor 1
342                                 ACCIn);
343
344  // replace uses of adde and addc here
345  if (!SDValue(ADDCNode, 0).use_empty()) {
346    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
347    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
348  }
349  if (!SDValue(ADDENode, 0).use_empty()) {
350    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
351    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
352  }
353
354  return true;
355}
356
357// selectMSUB -
358// Transforms a subgraph in CurDAG if the following pattern is found:
359//  (addc Lo0, multLo), (sube Hi0, multHi),
360// where,
361//  multHi/Lo: product of multiplication
362//  Lo0: initial value of Lo register
363//  Hi0: initial value of Hi register
364// Return true if pattern matching was successful.
365static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
366  // SUBENode's second operand must be a flag output of an SUBC node in order
367  // for the matching to be successful.
368  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
369
370  if (SUBCNode->getOpcode() != ISD::SUBC)
371    return false;
372
373  SDValue MultHi = SUBENode->getOperand(1);
374  SDValue MultLo = SUBCNode->getOperand(1);
375  SDNode *MultNode = MultHi.getNode();
376  unsigned MultOpc = MultHi.getOpcode();
377
378  // MultHi and MultLo must be generated by the same node,
379  if (MultLo.getNode() != MultNode)
380    return false;
381
382  // and it must be a multiplication.
383  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
384    return false;
385
386  // MultLo amd MultHi must be the first and second output of MultNode
387  // respectively.
388  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
389    return false;
390
391  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
392  // of the values of MultNode, in which case MultNode will be removed in later
393  // phases.
394  // If there exist users other than SUBENode or SUBCNode, this function returns
395  // here, which will result in MultNode being mapped to a single MULT
396  // instruction node rather than a pair of MULT and MSUB instructions being
397  // produced.
398  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
399    return false;
400
401  SDLoc DL(SUBENode);
402
403  // Initialize accumulator.
404  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
405                                  SUBCNode->getOperand(0),
406                                  SUBENode->getOperand(0));
407
408  // create MipsSub(u) node
409  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
410
411  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
412                                 MultNode->getOperand(0),// Factor 0
413                                 MultNode->getOperand(1),// Factor 1
414                                 ACCIn);
415
416  // replace uses of sube and subc here
417  if (!SDValue(SUBCNode, 0).use_empty()) {
418    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
419    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
420  }
421  if (!SDValue(SUBENode, 0).use_empty()) {
422    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
423    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
424  }
425
426  return true;
427}
428
429static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
430                                  TargetLowering::DAGCombinerInfo &DCI,
431                                  const MipsSubtarget *Subtarget) {
432  if (DCI.isBeforeLegalize())
433    return SDValue();
434
435  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
436      selectMADD(N, &DAG))
437    return SDValue(N, 0);
438
439  return SDValue();
440}
441
442// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
443//
444// Performs the following transformations:
445// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
446//   sign/zero-extension is completely overwritten by the new one performed by
447//   the ISD::AND.
448// - Removes redundant zero extensions performed by an ISD::AND.
449static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
450                                 TargetLowering::DAGCombinerInfo &DCI,
451                                 const MipsSubtarget *Subtarget) {
452  if (!Subtarget->hasMSA())
453    return SDValue();
454
455  SDValue Op0 = N->getOperand(0);
456  SDValue Op1 = N->getOperand(1);
457  unsigned Op0Opcode = Op0->getOpcode();
458
459  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
460  // where $d + 1 == 2^n and n == 32
461  // or    $d + 1 == 2^n and n <= 32 and ZExt
462  // -> (MipsVExtractZExt $a, $b, $c)
463  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
464      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
465    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
466
467    if (!Mask)
468      return SDValue();
469
470    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
471
472    if (Log2IfPositive <= 0)
473      return SDValue(); // Mask+1 is not a power of 2
474
475    SDValue Op0Op2 = Op0->getOperand(2);
476    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
477    unsigned ExtendTySize = ExtendTy.getSizeInBits();
478    unsigned Log2 = Log2IfPositive;
479
480    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
481        Log2 == ExtendTySize) {
482      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
483      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
484                      Op0->getVTList(), Ops, Op0->getNumOperands());
485      return Op0;
486    }
487  }
488
489  return SDValue();
490}
491
492// Determine if the specified node is a constant vector splat.
493//
494// Returns true and sets Imm if:
495// * N is a ISD::BUILD_VECTOR representing a constant splat
496//
497// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
498// differences are that it assumes the MSA has already been checked and the
499// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
500// must not be in order for binsri.d to be selectable).
501static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
502  BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
503
504  if (Node == NULL)
505    return false;
506
507  APInt SplatValue, SplatUndef;
508  unsigned SplatBitSize;
509  bool HasAnyUndefs;
510
511  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
512                             8, !IsLittleEndian))
513    return false;
514
515  Imm = SplatValue;
516
517  return true;
518}
519
520// Test whether the given node is an all-ones build_vector.
521static bool isVectorAllOnes(SDValue N) {
522  // Look through bitcasts. Endianness doesn't matter because we are looking
523  // for an all-ones value.
524  if (N->getOpcode() == ISD::BITCAST)
525    N = N->getOperand(0);
526
527  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
528
529  if (!BVN)
530    return false;
531
532  APInt SplatValue, SplatUndef;
533  unsigned SplatBitSize;
534  bool HasAnyUndefs;
535
536  // Endianness doesn't matter in this context because we are looking for
537  // an all-ones value.
538  if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
539    return SplatValue.isAllOnesValue();
540
541  return false;
542}
543
544// Test whether N is the bitwise inverse of OfNode.
545static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
546  if (N->getOpcode() != ISD::XOR)
547    return false;
548
549  if (isVectorAllOnes(N->getOperand(0)))
550    return N->getOperand(1) == OfNode;
551
552  if (isVectorAllOnes(N->getOperand(1)))
553    return N->getOperand(0) == OfNode;
554
555  return false;
556}
557
558// Perform combines where ISD::OR is the root node.
559//
560// Performs the following transformations:
561// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
562//   where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
563//   vector type.
564static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
565                                TargetLowering::DAGCombinerInfo &DCI,
566                                const MipsSubtarget *Subtarget) {
567  if (!Subtarget->hasMSA())
568    return SDValue();
569
570  EVT Ty = N->getValueType(0);
571
572  if (!Ty.is128BitVector())
573    return SDValue();
574
575  SDValue Op0 = N->getOperand(0);
576  SDValue Op1 = N->getOperand(1);
577
578  if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
579    SDValue Op0Op0 = Op0->getOperand(0);
580    SDValue Op0Op1 = Op0->getOperand(1);
581    SDValue Op1Op0 = Op1->getOperand(0);
582    SDValue Op1Op1 = Op1->getOperand(1);
583    bool IsLittleEndian = !Subtarget->isLittle();
584
585    SDValue IfSet, IfClr, Cond;
586    bool IsConstantMask = false;
587    APInt Mask, InvMask;
588
589    // If Op0Op0 is an appropriate mask, try to find it's inverse in either
590    // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
591    // looking.
592    // IfClr will be set if we find a valid match.
593    if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
594      Cond = Op0Op0;
595      IfSet = Op0Op1;
596
597      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
598        IfClr = Op1Op1;
599      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
600        IfClr = Op1Op0;
601
602      IsConstantMask = true;
603    }
604
605    // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
606    // thing again using this mask.
607    // IfClr will be set if we find a valid match.
608    if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
609      Cond = Op0Op1;
610      IfSet = Op0Op0;
611
612      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
613        IfClr = Op1Op1;
614      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
615        IfClr = Op1Op0;
616
617      IsConstantMask = true;
618    }
619
620    // If IfClr is not yet set, try looking for a non-constant match.
621    // IfClr will be set if we find a valid match amongst the eight
622    // possibilities.
623    if (!IfClr.getNode()) {
624      if (isBitwiseInverse(Op0Op0, Op1Op0)) {
625        Cond = Op1Op0;
626        IfSet = Op1Op1;
627        IfClr = Op0Op1;
628      } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
629        Cond = Op1Op0;
630        IfSet = Op1Op1;
631        IfClr = Op0Op0;
632      } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
633        Cond = Op1Op1;
634        IfSet = Op1Op0;
635        IfClr = Op0Op1;
636      } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
637        Cond = Op1Op1;
638        IfSet = Op1Op0;
639        IfClr = Op0Op0;
640      } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
641        Cond = Op0Op0;
642        IfSet = Op0Op1;
643        IfClr = Op1Op1;
644      } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
645        Cond = Op0Op0;
646        IfSet = Op0Op1;
647        IfClr = Op1Op0;
648      } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
649        Cond = Op0Op1;
650        IfSet = Op0Op0;
651        IfClr = Op1Op1;
652      } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
653        Cond = Op0Op1;
654        IfSet = Op0Op0;
655        IfClr = Op1Op0;
656      }
657    }
658
659    // At this point, IfClr will be set if we have a valid match.
660    if (!IfClr.getNode())
661      return SDValue();
662
663    assert(Cond.getNode() && IfSet.getNode());
664
665    // Fold degenerate cases.
666    if (IsConstantMask) {
667      if (Mask.isAllOnesValue())
668        return IfSet;
669      else if (Mask == 0)
670        return IfClr;
671    }
672
673    // Transform the DAG into an equivalent VSELECT.
674    return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet);
675  }
676
677  return SDValue();
678}
679
680static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
681                                  TargetLowering::DAGCombinerInfo &DCI,
682                                  const MipsSubtarget *Subtarget) {
683  if (DCI.isBeforeLegalize())
684    return SDValue();
685
686  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
687      selectMSUB(N, &DAG))
688    return SDValue(N, 0);
689
690  return SDValue();
691}
692
693static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
694                            EVT ShiftTy, SelectionDAG &DAG) {
695  // Clear the upper (64 - VT.sizeInBits) bits.
696  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
697
698  // Return 0.
699  if (C == 0)
700    return DAG.getConstant(0, VT);
701
702  // Return x.
703  if (C == 1)
704    return X;
705
706  // If c is power of 2, return (shl x, log2(c)).
707  if (isPowerOf2_64(C))
708    return DAG.getNode(ISD::SHL, DL, VT, X,
709                       DAG.getConstant(Log2_64(C), ShiftTy));
710
711  unsigned Log2Ceil = Log2_64_Ceil(C);
712  uint64_t Floor = 1LL << Log2_64(C);
713  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
714
715  // If |c - floor_c| <= |c - ceil_c|,
716  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
717  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
718  if (C - Floor <= Ceil - C) {
719    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
720    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
721    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
722  }
723
724  // If |c - floor_c| > |c - ceil_c|,
725  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
726  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
727  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
728  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
729}
730
731static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
732                                 const TargetLowering::DAGCombinerInfo &DCI,
733                                 const MipsSETargetLowering *TL) {
734  EVT VT = N->getValueType(0);
735
736  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
737    if (!VT.isVector())
738      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
739                          VT, TL->getScalarShiftAmountTy(VT), DAG);
740
741  return SDValue(N, 0);
742}
743
744static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
745                                      SelectionDAG &DAG,
746                                      const MipsSubtarget *Subtarget) {
747  // See if this is a vector splat immediate node.
748  APInt SplatValue, SplatUndef;
749  unsigned SplatBitSize;
750  bool HasAnyUndefs;
751  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
752  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
753
754  if (!BV ||
755      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
756                           EltSize, !Subtarget->isLittle()) ||
757      (SplatBitSize != EltSize) ||
758      (SplatValue.getZExtValue() >= EltSize))
759    return SDValue();
760
761  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
762                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
763}
764
765static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
766                                 TargetLowering::DAGCombinerInfo &DCI,
767                                 const MipsSubtarget *Subtarget) {
768  EVT Ty = N->getValueType(0);
769
770  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
771    return SDValue();
772
773  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
774}
775
776// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
777// constant splats into MipsISD::SHRA_DSP for DSPr2.
778//
779// Performs the following transformations:
780// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
781//   sign/zero-extension is completely overwritten by the new one performed by
782//   the ISD::SRA and ISD::SHL nodes.
783// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
784//   sequence.
785//
786// See performDSPShiftCombine for more information about the transformation
787// used for DSPr2.
788static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
789                                 TargetLowering::DAGCombinerInfo &DCI,
790                                 const MipsSubtarget *Subtarget) {
791  EVT Ty = N->getValueType(0);
792
793  if (Subtarget->hasMSA()) {
794    SDValue Op0 = N->getOperand(0);
795    SDValue Op1 = N->getOperand(1);
796
797    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
798    // where $d + sizeof($c) == 32
799    // or    $d + sizeof($c) <= 32 and SExt
800    // -> (MipsVExtractSExt $a, $b, $c)
801    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
802      SDValue Op0Op0 = Op0->getOperand(0);
803      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
804
805      if (!ShAmount)
806        return SDValue();
807
808      if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
809          Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
810        return SDValue();
811
812      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
813      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
814
815      if (TotalBits == 32 ||
816          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
817           TotalBits <= 32)) {
818        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
819                          Op0Op0->getOperand(2) };
820        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
821                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
822        return Op0Op0;
823      }
824    }
825  }
826
827  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
828    return SDValue();
829
830  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
831}
832
833
834static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
835                                 TargetLowering::DAGCombinerInfo &DCI,
836                                 const MipsSubtarget *Subtarget) {
837  EVT Ty = N->getValueType(0);
838
839  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
840    return SDValue();
841
842  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
843}
844
845static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
846  bool IsV216 = (Ty == MVT::v2i16);
847
848  switch (CC) {
849  case ISD::SETEQ:
850  case ISD::SETNE:  return true;
851  case ISD::SETLT:
852  case ISD::SETLE:
853  case ISD::SETGT:
854  case ISD::SETGE:  return IsV216;
855  case ISD::SETULT:
856  case ISD::SETULE:
857  case ISD::SETUGT:
858  case ISD::SETUGE: return !IsV216;
859  default:          return false;
860  }
861}
862
863static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
864  EVT Ty = N->getValueType(0);
865
866  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
867    return SDValue();
868
869  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
870    return SDValue();
871
872  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
873                     N->getOperand(1), N->getOperand(2));
874}
875
876static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
877  EVT Ty = N->getValueType(0);
878
879  if (Ty.is128BitVector() && Ty.isInteger()) {
880    // Try the following combines:
881    //   (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
882    //   (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
883    //   (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
884    //   (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
885    //   (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
886    //   (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
887    //   (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
888    //   (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
889    // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
890    // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
891    // legalizer.
892    SDValue Op0 = N->getOperand(0);
893
894    if (Op0->getOpcode() != ISD::SETCC)
895      return SDValue();
896
897    ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
898    bool Signed;
899
900    if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)
901      Signed = true;
902    else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
903      Signed = false;
904    else
905      return SDValue();
906
907    SDValue Op1 = N->getOperand(1);
908    SDValue Op2 = N->getOperand(2);
909    SDValue Op0Op0 = Op0->getOperand(0);
910    SDValue Op0Op1 = Op0->getOperand(1);
911
912    if (Op1 == Op0Op0 && Op2 == Op0Op1)
913      return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
914                         Ty, Op1, Op2);
915    else if (Op1 == Op0Op1 && Op2 == Op0Op0)
916      return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
917                         Ty, Op1, Op2);
918  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
919    SDValue SetCC = N->getOperand(0);
920
921    if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
922      return SDValue();
923
924    return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
925                       SetCC.getOperand(0), SetCC.getOperand(1),
926                       N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
927  }
928
929  return SDValue();
930}
931
932static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
933                                 const MipsSubtarget *Subtarget) {
934  EVT Ty = N->getValueType(0);
935
936  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
937    // Try the following combines:
938    //   (xor (or $a, $b), (build_vector allones))
939    //   (xor (or $a, $b), (bitcast (build_vector allones)))
940    SDValue Op0 = N->getOperand(0);
941    SDValue Op1 = N->getOperand(1);
942    SDValue NotOp;
943
944    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
945      NotOp = Op1;
946    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
947      NotOp = Op0;
948    else
949      return SDValue();
950
951    if (NotOp->getOpcode() == ISD::OR)
952      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
953                         NotOp->getOperand(1));
954  }
955
956  return SDValue();
957}
958
959SDValue
960MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
961  SelectionDAG &DAG = DCI.DAG;
962  SDValue Val;
963
964  switch (N->getOpcode()) {
965  case ISD::ADDE:
966    return performADDECombine(N, DAG, DCI, Subtarget);
967  case ISD::AND:
968    Val = performANDCombine(N, DAG, DCI, Subtarget);
969    break;
970  case ISD::OR:
971    Val = performORCombine(N, DAG, DCI, Subtarget);
972    break;
973  case ISD::SUBE:
974    return performSUBECombine(N, DAG, DCI, Subtarget);
975  case ISD::MUL:
976    return performMULCombine(N, DAG, DCI, this);
977  case ISD::SHL:
978    return performSHLCombine(N, DAG, DCI, Subtarget);
979  case ISD::SRA:
980    return performSRACombine(N, DAG, DCI, Subtarget);
981  case ISD::SRL:
982    return performSRLCombine(N, DAG, DCI, Subtarget);
983  case ISD::VSELECT:
984    return performVSELECTCombine(N, DAG);
985  case ISD::XOR:
986    Val = performXORCombine(N, DAG, Subtarget);
987    break;
988  case ISD::SETCC:
989    Val = performSETCCCombine(N, DAG);
990    break;
991  }
992
993  if (Val.getNode()) {
994    DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
995          N->printrWithDepth(dbgs(), &DAG);
996          dbgs() << "\n=> \n";
997          Val.getNode()->printrWithDepth(dbgs(), &DAG);
998          dbgs() << "\n");
999    return Val;
1000  }
1001
1002  return MipsTargetLowering::PerformDAGCombine(N, DCI);
1003}
1004
1005MachineBasicBlock *
1006MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1007                                                  MachineBasicBlock *BB) const {
1008  switch (MI->getOpcode()) {
1009  default:
1010    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1011  case Mips::BPOSGE32_PSEUDO:
1012    return emitBPOSGE32(MI, BB);
1013  case Mips::SNZ_B_PSEUDO:
1014    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1015  case Mips::SNZ_H_PSEUDO:
1016    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1017  case Mips::SNZ_W_PSEUDO:
1018    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1019  case Mips::SNZ_D_PSEUDO:
1020    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1021  case Mips::SNZ_V_PSEUDO:
1022    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1023  case Mips::SZ_B_PSEUDO:
1024    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1025  case Mips::SZ_H_PSEUDO:
1026    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1027  case Mips::SZ_W_PSEUDO:
1028    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1029  case Mips::SZ_D_PSEUDO:
1030    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1031  case Mips::SZ_V_PSEUDO:
1032    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1033  case Mips::COPY_FW_PSEUDO:
1034    return emitCOPY_FW(MI, BB);
1035  case Mips::COPY_FD_PSEUDO:
1036    return emitCOPY_FD(MI, BB);
1037  case Mips::INSERT_FW_PSEUDO:
1038    return emitINSERT_FW(MI, BB);
1039  case Mips::INSERT_FD_PSEUDO:
1040    return emitINSERT_FD(MI, BB);
1041  case Mips::FILL_FW_PSEUDO:
1042    return emitFILL_FW(MI, BB);
1043  case Mips::FILL_FD_PSEUDO:
1044    return emitFILL_FD(MI, BB);
1045  case Mips::FEXP2_W_1_PSEUDO:
1046    return emitFEXP2_W_1(MI, BB);
1047  case Mips::FEXP2_D_1_PSEUDO:
1048    return emitFEXP2_D_1(MI, BB);
1049  }
1050}
1051
1052bool MipsSETargetLowering::
1053isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
1054                                  unsigned NextStackOffset,
1055                                  const MipsFunctionInfo& FI) const {
1056  if (!EnableMipsTailCalls)
1057    return false;
1058
1059  // Return false if either the callee or caller has a byval argument.
1060  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
1061    return false;
1062
1063  // Return true if the callee's argument area is no larger than the
1064  // caller's.
1065  return NextStackOffset <= FI.getIncomingArgSize();
1066}
1067
1068void MipsSETargetLowering::
1069getOpndList(SmallVectorImpl<SDValue> &Ops,
1070            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1071            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
1072            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
1073  // T9 should contain the address of the callee function if
1074  // -reloction-model=pic or it is an indirect call.
1075  if (IsPICCall || !GlobalOrExternal) {
1076    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
1077    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
1078  } else
1079    Ops.push_back(Callee);
1080
1081  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
1082                                  InternalLinkage, CLI, Callee, Chain);
1083}
1084
1085SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1086  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1087
1088  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1089    return MipsTargetLowering::lowerLOAD(Op, DAG);
1090
1091  // Replace a double precision load with two i32 loads and a buildpair64.
1092  SDLoc DL(Op);
1093  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1094  EVT PtrVT = Ptr.getValueType();
1095
1096  // i32 load from lower address.
1097  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1098                           MachinePointerInfo(), Nd.isVolatile(),
1099                           Nd.isNonTemporal(), Nd.isInvariant(),
1100                           Nd.getAlignment());
1101
1102  // i32 load from higher address.
1103  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1104  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1105                           MachinePointerInfo(), Nd.isVolatile(),
1106                           Nd.isNonTemporal(), Nd.isInvariant(),
1107                           std::min(Nd.getAlignment(), 4U));
1108
1109  if (!Subtarget->isLittle())
1110    std::swap(Lo, Hi);
1111
1112  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1113  SDValue Ops[2] = {BP, Hi.getValue(1)};
1114  return DAG.getMergeValues(Ops, 2, DL);
1115}
1116
1117SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1118  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1119
1120  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1121    return MipsTargetLowering::lowerSTORE(Op, DAG);
1122
1123  // Replace a double precision store with two extractelement64s and i32 stores.
1124  SDLoc DL(Op);
1125  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1126  EVT PtrVT = Ptr.getValueType();
1127  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1128                           Val, DAG.getConstant(0, MVT::i32));
1129  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1130                           Val, DAG.getConstant(1, MVT::i32));
1131
1132  if (!Subtarget->isLittle())
1133    std::swap(Lo, Hi);
1134
1135  // i32 store to lower address.
1136  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1137                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
1138                       Nd.getTBAAInfo());
1139
1140  // i32 store to higher address.
1141  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
1142  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
1143                      Nd.isVolatile(), Nd.isNonTemporal(),
1144                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
1145}
1146
1147SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1148                                          bool HasLo, bool HasHi,
1149                                          SelectionDAG &DAG) const {
1150  EVT Ty = Op.getOperand(0).getValueType();
1151  SDLoc DL(Op);
1152  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1153                             Op.getOperand(0), Op.getOperand(1));
1154  SDValue Lo, Hi;
1155
1156  if (HasLo)
1157    Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
1158  if (HasHi)
1159    Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
1160
1161  if (!HasLo || !HasHi)
1162    return HasLo ? Lo : Hi;
1163
1164  SDValue Vals[] = { Lo, Hi };
1165  return DAG.getMergeValues(Vals, 2, DL);
1166}
1167
1168
1169static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
1170  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1171                             DAG.getConstant(0, MVT::i32));
1172  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
1173                             DAG.getConstant(1, MVT::i32));
1174  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
1175}
1176
1177static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
1178  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1179  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
1180  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1181}
1182
1183// This function expands mips intrinsic nodes which have 64-bit input operands
1184// or output values.
1185//
1186// out64 = intrinsic-node in64
1187// =>
1188// lo = copy (extract-element (in64, 0))
1189// hi = copy (extract-element (in64, 1))
1190// mips-specific-node
1191// v0 = copy lo
1192// v1 = copy hi
1193// out64 = merge-values (v0, v1)
1194//
1195static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1196  SDLoc DL(Op);
1197  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1198  SmallVector<SDValue, 3> Ops;
1199  unsigned OpNo = 0;
1200
1201  // See if Op has a chain input.
1202  if (HasChainIn)
1203    Ops.push_back(Op->getOperand(OpNo++));
1204
1205  // The next operand is the intrinsic opcode.
1206  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1207
1208  // See if the next operand has type i64.
1209  SDValue Opnd = Op->getOperand(++OpNo), In64;
1210
1211  if (Opnd.getValueType() == MVT::i64)
1212    In64 = initAccumulator(Opnd, DL, DAG);
1213  else
1214    Ops.push_back(Opnd);
1215
1216  // Push the remaining operands.
1217  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1218    Ops.push_back(Op->getOperand(OpNo));
1219
1220  // Add In64 to the end of the list.
1221  if (In64.getNode())
1222    Ops.push_back(In64);
1223
1224  // Scan output.
1225  SmallVector<EVT, 2> ResTys;
1226
1227  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1228       I != E; ++I)
1229    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1230
1231  // Create node.
1232  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1233  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1234
1235  if (!HasChainIn)
1236    return Out;
1237
1238  assert(Val->getValueType(1) == MVT::Other);
1239  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1240  return DAG.getMergeValues(Vals, 2, DL);
1241}
1242
1243// Lower an MSA copy intrinsic into the specified SelectionDAG node
1244static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1245  SDLoc DL(Op);
1246  SDValue Vec = Op->getOperand(1);
1247  SDValue Idx = Op->getOperand(2);
1248  EVT ResTy = Op->getValueType(0);
1249  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1250
1251  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1252                               DAG.getValueType(EltTy));
1253
1254  return Result;
1255}
1256
1257static SDValue
1258lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1259  EVT ViaVecTy = ResTy;
1260  SmallVector<SDValue, 16> Ops;
1261  SDValue ImmHiOp;
1262
1263  if (ViaVecTy == MVT::v2i64) {
1264    ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1265                          DAG.getConstant(31, MVT::i32));
1266    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1267      Ops.push_back(ImmHiOp);
1268      Ops.push_back(ImmOp);
1269    }
1270    ViaVecTy = MVT::v4i32;
1271  } else {
1272    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1273      Ops.push_back(ImmOp);
1274  }
1275
1276  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1277                               Ops.size());
1278
1279  if (ResTy != ViaVecTy)
1280    Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1281
1282  return Result;
1283}
1284
1285static SDValue
1286lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1287  return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1288                          Op->getOperand(ImmOp), DAG);
1289}
1290
1291static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1292                                        unsigned Opc, SDValue Imm,
1293                                        bool BigEndian) {
1294  EVT VecTy = Op->getValueType(0);
1295  SDValue Exp2Imm;
1296  SDLoc DL(Op);
1297
1298  // The DAG Combiner can't constant fold bitcasted vectors so we must do it
1299  // here.
1300  if (VecTy == MVT::v2i64) {
1301    if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1302      APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1303
1304      SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32);
1305      SDValue BitImmOp = DAG.getConstant(BitImm.trunc(32), MVT::i32);
1306      Exp2Imm = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
1307                            DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32,
1308                                        BitImmHiOp, BitImmOp,
1309                                        BitImmHiOp, BitImmOp));
1310    }
1311  }
1312
1313  if (Exp2Imm.getNode() == NULL) {
1314    // We couldnt constant fold, do a vector shift instead
1315    SDValue One = lowerMSASplatImm(DL, VecTy, DAG.getConstant(1, MVT::i32),
1316                                   DAG);
1317    Exp2Imm = lowerMSASplatImm(DL, VecTy, Imm, DAG);
1318    Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, One, Exp2Imm);
1319  }
1320
1321  return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1322}
1323
1324static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1325  EVT ResTy = Op->getValueType(0);
1326  EVT ViaVecTy = ResTy == MVT::v2i64 ? MVT::v4i32 : ResTy;
1327  SDLoc DL(Op);
1328  SDValue One = lowerMSASplatImm(DL, ResTy, DAG.getConstant(1, MVT::i32), DAG);
1329  SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1330
1331  SDValue AllOnes = DAG.getConstant(-1, MVT::i32);
1332  SDValue AllOnesOperands[16] = { AllOnes, AllOnes, AllOnes, AllOnes,
1333                                  AllOnes, AllOnes, AllOnes, AllOnes,
1334                                  AllOnes, AllOnes, AllOnes, AllOnes,
1335                                  AllOnes, AllOnes, AllOnes, AllOnes };
1336  AllOnes = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, AllOnesOperands,
1337                        ViaVecTy.getVectorNumElements());
1338  if (ResTy != ViaVecTy)
1339    AllOnes = DAG.getNode(ISD::BITCAST, DL, ResTy, AllOnes);
1340
1341  Bit = DAG.getNode(ISD::XOR, DL, ResTy, Bit, AllOnes);
1342
1343  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), Bit);
1344}
1345
1346static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1347  SDLoc DL(Op);
1348  EVT ResTy = Op->getValueType(0);
1349  SDValue SHAmount = Op->getOperand(2);
1350  EVT ImmTy = SHAmount->getValueType(0);
1351  SDValue Bit =
1352      DAG.getNode(ISD::SHL, DL, ImmTy, DAG.getConstant(1, ImmTy), SHAmount);
1353  SDValue BitMask = DAG.getNOT(DL, Bit, ImmTy);
1354
1355  assert(ResTy.getVectorNumElements() <= 16);
1356
1357  BitMask = lowerMSASplatImm(DL, ResTy, BitMask, DAG);
1358
1359  return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1360}
1361
1362SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1363                                                      SelectionDAG &DAG) const {
1364  SDLoc DL(Op);
1365
1366  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1367  default:
1368    return SDValue();
1369  case Intrinsic::mips_shilo:
1370    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1371  case Intrinsic::mips_dpau_h_qbl:
1372    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1373  case Intrinsic::mips_dpau_h_qbr:
1374    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1375  case Intrinsic::mips_dpsu_h_qbl:
1376    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1377  case Intrinsic::mips_dpsu_h_qbr:
1378    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1379  case Intrinsic::mips_dpa_w_ph:
1380    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1381  case Intrinsic::mips_dps_w_ph:
1382    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1383  case Intrinsic::mips_dpax_w_ph:
1384    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1385  case Intrinsic::mips_dpsx_w_ph:
1386    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1387  case Intrinsic::mips_mulsa_w_ph:
1388    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1389  case Intrinsic::mips_mult:
1390    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1391  case Intrinsic::mips_multu:
1392    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1393  case Intrinsic::mips_madd:
1394    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1395  case Intrinsic::mips_maddu:
1396    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1397  case Intrinsic::mips_msub:
1398    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1399  case Intrinsic::mips_msubu:
1400    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1401  case Intrinsic::mips_addv_b:
1402  case Intrinsic::mips_addv_h:
1403  case Intrinsic::mips_addv_w:
1404  case Intrinsic::mips_addv_d:
1405    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1406                       Op->getOperand(2));
1407  case Intrinsic::mips_addvi_b:
1408  case Intrinsic::mips_addvi_h:
1409  case Intrinsic::mips_addvi_w:
1410  case Intrinsic::mips_addvi_d:
1411    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1412                       lowerMSASplatImm(Op, 2, DAG));
1413  case Intrinsic::mips_and_v:
1414    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1415                       Op->getOperand(2));
1416  case Intrinsic::mips_andi_b:
1417    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1418                       lowerMSASplatImm(Op, 2, DAG));
1419  case Intrinsic::mips_bclr_b:
1420  case Intrinsic::mips_bclr_h:
1421  case Intrinsic::mips_bclr_w:
1422  case Intrinsic::mips_bclr_d:
1423    return lowerMSABitClear(Op, DAG);
1424  case Intrinsic::mips_bclri_b:
1425  case Intrinsic::mips_bclri_h:
1426  case Intrinsic::mips_bclri_w:
1427  case Intrinsic::mips_bclri_d:
1428    return lowerMSABitClearImm(Op, DAG);
1429  case Intrinsic::mips_binsli_b:
1430  case Intrinsic::mips_binsli_h:
1431  case Intrinsic::mips_binsli_w:
1432  case Intrinsic::mips_binsli_d: {
1433    EVT VecTy = Op->getValueType(0);
1434    EVT EltTy = VecTy.getVectorElementType();
1435    APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1436                                       Op->getConstantOperandVal(3));
1437    return DAG.getNode(ISD::VSELECT, DL, VecTy,
1438                       DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1439                       Op->getOperand(2));
1440  }
1441  case Intrinsic::mips_binsri_b:
1442  case Intrinsic::mips_binsri_h:
1443  case Intrinsic::mips_binsri_w:
1444  case Intrinsic::mips_binsri_d: {
1445    EVT VecTy = Op->getValueType(0);
1446    EVT EltTy = VecTy.getVectorElementType();
1447    APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1448                                      Op->getConstantOperandVal(3));
1449    return DAG.getNode(ISD::VSELECT, DL, VecTy,
1450                       DAG.getConstant(Mask, VecTy, true), Op->getOperand(1),
1451                       Op->getOperand(2));
1452  }
1453  case Intrinsic::mips_bmnz_v:
1454    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1455                       Op->getOperand(2), Op->getOperand(1));
1456  case Intrinsic::mips_bmnzi_b:
1457    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1458                       lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1459                       Op->getOperand(1));
1460  case Intrinsic::mips_bmz_v:
1461    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1462                       Op->getOperand(1), Op->getOperand(2));
1463  case Intrinsic::mips_bmzi_b:
1464    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1465                       lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1466                       Op->getOperand(2));
1467  case Intrinsic::mips_bneg_b:
1468  case Intrinsic::mips_bneg_h:
1469  case Intrinsic::mips_bneg_w:
1470  case Intrinsic::mips_bneg_d: {
1471    EVT VecTy = Op->getValueType(0);
1472    SDValue One = lowerMSASplatImm(DL, VecTy, DAG.getConstant(1, MVT::i32),
1473                                   DAG);
1474
1475    return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1476                       DAG.getNode(ISD::SHL, DL, VecTy, One,
1477                                   Op->getOperand(2)));
1478  }
1479  case Intrinsic::mips_bnegi_b:
1480  case Intrinsic::mips_bnegi_h:
1481  case Intrinsic::mips_bnegi_w:
1482  case Intrinsic::mips_bnegi_d:
1483    return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
1484                                    !Subtarget->isLittle());
1485  case Intrinsic::mips_bnz_b:
1486  case Intrinsic::mips_bnz_h:
1487  case Intrinsic::mips_bnz_w:
1488  case Intrinsic::mips_bnz_d:
1489    return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1490                       Op->getOperand(1));
1491  case Intrinsic::mips_bnz_v:
1492    return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1493                       Op->getOperand(1));
1494  case Intrinsic::mips_bsel_v:
1495    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1496                       Op->getOperand(1), Op->getOperand(2),
1497                       Op->getOperand(3));
1498  case Intrinsic::mips_bseli_b:
1499    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1500                       Op->getOperand(1), Op->getOperand(2),
1501                       lowerMSASplatImm(Op, 3, DAG));
1502  case Intrinsic::mips_bset_b:
1503  case Intrinsic::mips_bset_h:
1504  case Intrinsic::mips_bset_w:
1505  case Intrinsic::mips_bset_d: {
1506    EVT VecTy = Op->getValueType(0);
1507    SDValue One = lowerMSASplatImm(DL, VecTy, DAG.getConstant(1, MVT::i32),
1508                                   DAG);
1509
1510    return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1511                       DAG.getNode(ISD::SHL, DL, VecTy, One,
1512                                   Op->getOperand(2)));
1513  }
1514  case Intrinsic::mips_bseti_b:
1515  case Intrinsic::mips_bseti_h:
1516  case Intrinsic::mips_bseti_w:
1517  case Intrinsic::mips_bseti_d:
1518    return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
1519                                    !Subtarget->isLittle());
1520  case Intrinsic::mips_bz_b:
1521  case Intrinsic::mips_bz_h:
1522  case Intrinsic::mips_bz_w:
1523  case Intrinsic::mips_bz_d:
1524    return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1525                       Op->getOperand(1));
1526  case Intrinsic::mips_bz_v:
1527    return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1528                       Op->getOperand(1));
1529  case Intrinsic::mips_ceq_b:
1530  case Intrinsic::mips_ceq_h:
1531  case Intrinsic::mips_ceq_w:
1532  case Intrinsic::mips_ceq_d:
1533    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1534                        Op->getOperand(2), ISD::SETEQ);
1535  case Intrinsic::mips_ceqi_b:
1536  case Intrinsic::mips_ceqi_h:
1537  case Intrinsic::mips_ceqi_w:
1538  case Intrinsic::mips_ceqi_d:
1539    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1540                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1541  case Intrinsic::mips_cle_s_b:
1542  case Intrinsic::mips_cle_s_h:
1543  case Intrinsic::mips_cle_s_w:
1544  case Intrinsic::mips_cle_s_d:
1545    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1546                        Op->getOperand(2), ISD::SETLE);
1547  case Intrinsic::mips_clei_s_b:
1548  case Intrinsic::mips_clei_s_h:
1549  case Intrinsic::mips_clei_s_w:
1550  case Intrinsic::mips_clei_s_d:
1551    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1552                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1553  case Intrinsic::mips_cle_u_b:
1554  case Intrinsic::mips_cle_u_h:
1555  case Intrinsic::mips_cle_u_w:
1556  case Intrinsic::mips_cle_u_d:
1557    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1558                        Op->getOperand(2), ISD::SETULE);
1559  case Intrinsic::mips_clei_u_b:
1560  case Intrinsic::mips_clei_u_h:
1561  case Intrinsic::mips_clei_u_w:
1562  case Intrinsic::mips_clei_u_d:
1563    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1564                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1565  case Intrinsic::mips_clt_s_b:
1566  case Intrinsic::mips_clt_s_h:
1567  case Intrinsic::mips_clt_s_w:
1568  case Intrinsic::mips_clt_s_d:
1569    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1570                        Op->getOperand(2), ISD::SETLT);
1571  case Intrinsic::mips_clti_s_b:
1572  case Intrinsic::mips_clti_s_h:
1573  case Intrinsic::mips_clti_s_w:
1574  case Intrinsic::mips_clti_s_d:
1575    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1576                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1577  case Intrinsic::mips_clt_u_b:
1578  case Intrinsic::mips_clt_u_h:
1579  case Intrinsic::mips_clt_u_w:
1580  case Intrinsic::mips_clt_u_d:
1581    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1582                        Op->getOperand(2), ISD::SETULT);
1583  case Intrinsic::mips_clti_u_b:
1584  case Intrinsic::mips_clti_u_h:
1585  case Intrinsic::mips_clti_u_w:
1586  case Intrinsic::mips_clti_u_d:
1587    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1588                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1589  case Intrinsic::mips_copy_s_b:
1590  case Intrinsic::mips_copy_s_h:
1591  case Intrinsic::mips_copy_s_w:
1592    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1593  case Intrinsic::mips_copy_s_d:
1594    // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1595    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1596    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1597    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1598                       Op->getOperand(1), Op->getOperand(2));
1599  case Intrinsic::mips_copy_u_b:
1600  case Intrinsic::mips_copy_u_h:
1601  case Intrinsic::mips_copy_u_w:
1602    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1603  case Intrinsic::mips_copy_u_d:
1604    // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1605    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1606    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1607    //
1608    // Note: When i64 is illegal, this results in copy_s.w instructions instead
1609    // of copy_u.w instructions. This makes no difference to the behaviour
1610    // since i64 is only illegal when the register file is 32-bit.
1611    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1612                       Op->getOperand(1), Op->getOperand(2));
1613  case Intrinsic::mips_div_s_b:
1614  case Intrinsic::mips_div_s_h:
1615  case Intrinsic::mips_div_s_w:
1616  case Intrinsic::mips_div_s_d:
1617    return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1618                       Op->getOperand(2));
1619  case Intrinsic::mips_div_u_b:
1620  case Intrinsic::mips_div_u_h:
1621  case Intrinsic::mips_div_u_w:
1622  case Intrinsic::mips_div_u_d:
1623    return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1624                       Op->getOperand(2));
1625  case Intrinsic::mips_fadd_w:
1626  case Intrinsic::mips_fadd_d:
1627    return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1628                       Op->getOperand(2));
1629  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1630  case Intrinsic::mips_fceq_w:
1631  case Intrinsic::mips_fceq_d:
1632    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1633                        Op->getOperand(2), ISD::SETOEQ);
1634  case Intrinsic::mips_fcle_w:
1635  case Intrinsic::mips_fcle_d:
1636    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1637                        Op->getOperand(2), ISD::SETOLE);
1638  case Intrinsic::mips_fclt_w:
1639  case Intrinsic::mips_fclt_d:
1640    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1641                        Op->getOperand(2), ISD::SETOLT);
1642  case Intrinsic::mips_fcne_w:
1643  case Intrinsic::mips_fcne_d:
1644    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1645                        Op->getOperand(2), ISD::SETONE);
1646  case Intrinsic::mips_fcor_w:
1647  case Intrinsic::mips_fcor_d:
1648    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1649                        Op->getOperand(2), ISD::SETO);
1650  case Intrinsic::mips_fcueq_w:
1651  case Intrinsic::mips_fcueq_d:
1652    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1653                        Op->getOperand(2), ISD::SETUEQ);
1654  case Intrinsic::mips_fcule_w:
1655  case Intrinsic::mips_fcule_d:
1656    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1657                        Op->getOperand(2), ISD::SETULE);
1658  case Intrinsic::mips_fcult_w:
1659  case Intrinsic::mips_fcult_d:
1660    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1661                        Op->getOperand(2), ISD::SETULT);
1662  case Intrinsic::mips_fcun_w:
1663  case Intrinsic::mips_fcun_d:
1664    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1665                        Op->getOperand(2), ISD::SETUO);
1666  case Intrinsic::mips_fcune_w:
1667  case Intrinsic::mips_fcune_d:
1668    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1669                        Op->getOperand(2), ISD::SETUNE);
1670  case Intrinsic::mips_fdiv_w:
1671  case Intrinsic::mips_fdiv_d:
1672    return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1673                       Op->getOperand(2));
1674  case Intrinsic::mips_ffint_u_w:
1675  case Intrinsic::mips_ffint_u_d:
1676    return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1677                       Op->getOperand(1));
1678  case Intrinsic::mips_ffint_s_w:
1679  case Intrinsic::mips_ffint_s_d:
1680    return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1681                       Op->getOperand(1));
1682  case Intrinsic::mips_fill_b:
1683  case Intrinsic::mips_fill_h:
1684  case Intrinsic::mips_fill_w:
1685  case Intrinsic::mips_fill_d: {
1686    SmallVector<SDValue, 16> Ops;
1687    EVT ResTy = Op->getValueType(0);
1688
1689    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1690      Ops.push_back(Op->getOperand(1));
1691
1692    // If ResTy is v2i64 then the type legalizer will break this node down into
1693    // an equivalent v4i32.
1694    return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1695  }
1696  case Intrinsic::mips_fexp2_w:
1697  case Intrinsic::mips_fexp2_d: {
1698    EVT ResTy = Op->getValueType(0);
1699    return DAG.getNode(
1700        ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1701        DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1702  }
1703  case Intrinsic::mips_flog2_w:
1704  case Intrinsic::mips_flog2_d:
1705    return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1706  case Intrinsic::mips_fmadd_w:
1707  case Intrinsic::mips_fmadd_d:
1708    return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1709                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1710  case Intrinsic::mips_fmul_w:
1711  case Intrinsic::mips_fmul_d:
1712    return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1713                       Op->getOperand(2));
1714  case Intrinsic::mips_fmsub_w:
1715  case Intrinsic::mips_fmsub_d: {
1716    EVT ResTy = Op->getValueType(0);
1717    return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1718                       DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1719                                   Op->getOperand(2), Op->getOperand(3)));
1720  }
1721  case Intrinsic::mips_frint_w:
1722  case Intrinsic::mips_frint_d:
1723    return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1724  case Intrinsic::mips_fsqrt_w:
1725  case Intrinsic::mips_fsqrt_d:
1726    return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1727  case Intrinsic::mips_fsub_w:
1728  case Intrinsic::mips_fsub_d:
1729    return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1730                       Op->getOperand(2));
1731  case Intrinsic::mips_ftrunc_u_w:
1732  case Intrinsic::mips_ftrunc_u_d:
1733    return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1734                       Op->getOperand(1));
1735  case Intrinsic::mips_ftrunc_s_w:
1736  case Intrinsic::mips_ftrunc_s_d:
1737    return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1738                       Op->getOperand(1));
1739  case Intrinsic::mips_ilvev_b:
1740  case Intrinsic::mips_ilvev_h:
1741  case Intrinsic::mips_ilvev_w:
1742  case Intrinsic::mips_ilvev_d:
1743    return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1744                       Op->getOperand(1), Op->getOperand(2));
1745  case Intrinsic::mips_ilvl_b:
1746  case Intrinsic::mips_ilvl_h:
1747  case Intrinsic::mips_ilvl_w:
1748  case Intrinsic::mips_ilvl_d:
1749    return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1750                       Op->getOperand(1), Op->getOperand(2));
1751  case Intrinsic::mips_ilvod_b:
1752  case Intrinsic::mips_ilvod_h:
1753  case Intrinsic::mips_ilvod_w:
1754  case Intrinsic::mips_ilvod_d:
1755    return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1756                       Op->getOperand(1), Op->getOperand(2));
1757  case Intrinsic::mips_ilvr_b:
1758  case Intrinsic::mips_ilvr_h:
1759  case Intrinsic::mips_ilvr_w:
1760  case Intrinsic::mips_ilvr_d:
1761    return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1762                       Op->getOperand(1), Op->getOperand(2));
1763  case Intrinsic::mips_insert_b:
1764  case Intrinsic::mips_insert_h:
1765  case Intrinsic::mips_insert_w:
1766  case Intrinsic::mips_insert_d:
1767    return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1768                       Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1769  case Intrinsic::mips_ldi_b:
1770  case Intrinsic::mips_ldi_h:
1771  case Intrinsic::mips_ldi_w:
1772  case Intrinsic::mips_ldi_d:
1773    return lowerMSASplatImm(Op, 1, DAG);
1774  case Intrinsic::mips_lsa: {
1775    EVT ResTy = Op->getValueType(0);
1776    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1777                       DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1778                                   Op->getOperand(2), Op->getOperand(3)));
1779  }
1780  case Intrinsic::mips_maddv_b:
1781  case Intrinsic::mips_maddv_h:
1782  case Intrinsic::mips_maddv_w:
1783  case Intrinsic::mips_maddv_d: {
1784    EVT ResTy = Op->getValueType(0);
1785    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1786                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1787                                   Op->getOperand(2), Op->getOperand(3)));
1788  }
1789  case Intrinsic::mips_max_s_b:
1790  case Intrinsic::mips_max_s_h:
1791  case Intrinsic::mips_max_s_w:
1792  case Intrinsic::mips_max_s_d:
1793    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1794                       Op->getOperand(1), Op->getOperand(2));
1795  case Intrinsic::mips_max_u_b:
1796  case Intrinsic::mips_max_u_h:
1797  case Intrinsic::mips_max_u_w:
1798  case Intrinsic::mips_max_u_d:
1799    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1800                       Op->getOperand(1), Op->getOperand(2));
1801  case Intrinsic::mips_maxi_s_b:
1802  case Intrinsic::mips_maxi_s_h:
1803  case Intrinsic::mips_maxi_s_w:
1804  case Intrinsic::mips_maxi_s_d:
1805    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1806                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1807  case Intrinsic::mips_maxi_u_b:
1808  case Intrinsic::mips_maxi_u_h:
1809  case Intrinsic::mips_maxi_u_w:
1810  case Intrinsic::mips_maxi_u_d:
1811    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1812                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1813  case Intrinsic::mips_min_s_b:
1814  case Intrinsic::mips_min_s_h:
1815  case Intrinsic::mips_min_s_w:
1816  case Intrinsic::mips_min_s_d:
1817    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1818                       Op->getOperand(1), Op->getOperand(2));
1819  case Intrinsic::mips_min_u_b:
1820  case Intrinsic::mips_min_u_h:
1821  case Intrinsic::mips_min_u_w:
1822  case Intrinsic::mips_min_u_d:
1823    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1824                       Op->getOperand(1), Op->getOperand(2));
1825  case Intrinsic::mips_mini_s_b:
1826  case Intrinsic::mips_mini_s_h:
1827  case Intrinsic::mips_mini_s_w:
1828  case Intrinsic::mips_mini_s_d:
1829    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1830                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1831  case Intrinsic::mips_mini_u_b:
1832  case Intrinsic::mips_mini_u_h:
1833  case Intrinsic::mips_mini_u_w:
1834  case Intrinsic::mips_mini_u_d:
1835    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1836                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1837  case Intrinsic::mips_mod_s_b:
1838  case Intrinsic::mips_mod_s_h:
1839  case Intrinsic::mips_mod_s_w:
1840  case Intrinsic::mips_mod_s_d:
1841    return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1842                       Op->getOperand(2));
1843  case Intrinsic::mips_mod_u_b:
1844  case Intrinsic::mips_mod_u_h:
1845  case Intrinsic::mips_mod_u_w:
1846  case Intrinsic::mips_mod_u_d:
1847    return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1848                       Op->getOperand(2));
1849  case Intrinsic::mips_mulv_b:
1850  case Intrinsic::mips_mulv_h:
1851  case Intrinsic::mips_mulv_w:
1852  case Intrinsic::mips_mulv_d:
1853    return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1854                       Op->getOperand(2));
1855  case Intrinsic::mips_msubv_b:
1856  case Intrinsic::mips_msubv_h:
1857  case Intrinsic::mips_msubv_w:
1858  case Intrinsic::mips_msubv_d: {
1859    EVT ResTy = Op->getValueType(0);
1860    return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1861                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1862                                   Op->getOperand(2), Op->getOperand(3)));
1863  }
1864  case Intrinsic::mips_nlzc_b:
1865  case Intrinsic::mips_nlzc_h:
1866  case Intrinsic::mips_nlzc_w:
1867  case Intrinsic::mips_nlzc_d:
1868    return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1869  case Intrinsic::mips_nor_v: {
1870    SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1871                              Op->getOperand(1), Op->getOperand(2));
1872    return DAG.getNOT(DL, Res, Res->getValueType(0));
1873  }
1874  case Intrinsic::mips_nori_b: {
1875    SDValue Res =  DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1876                               Op->getOperand(1),
1877                               lowerMSASplatImm(Op, 2, DAG));
1878    return DAG.getNOT(DL, Res, Res->getValueType(0));
1879  }
1880  case Intrinsic::mips_or_v:
1881    return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1882                       Op->getOperand(2));
1883  case Intrinsic::mips_ori_b:
1884    return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1885                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1886  case Intrinsic::mips_pckev_b:
1887  case Intrinsic::mips_pckev_h:
1888  case Intrinsic::mips_pckev_w:
1889  case Intrinsic::mips_pckev_d:
1890    return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1891                       Op->getOperand(1), Op->getOperand(2));
1892  case Intrinsic::mips_pckod_b:
1893  case Intrinsic::mips_pckod_h:
1894  case Intrinsic::mips_pckod_w:
1895  case Intrinsic::mips_pckod_d:
1896    return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1897                       Op->getOperand(1), Op->getOperand(2));
1898  case Intrinsic::mips_pcnt_b:
1899  case Intrinsic::mips_pcnt_h:
1900  case Intrinsic::mips_pcnt_w:
1901  case Intrinsic::mips_pcnt_d:
1902    return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1903  case Intrinsic::mips_shf_b:
1904  case Intrinsic::mips_shf_h:
1905  case Intrinsic::mips_shf_w:
1906    return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1907                       Op->getOperand(2), Op->getOperand(1));
1908  case Intrinsic::mips_sll_b:
1909  case Intrinsic::mips_sll_h:
1910  case Intrinsic::mips_sll_w:
1911  case Intrinsic::mips_sll_d:
1912    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1913                       Op->getOperand(2));
1914  case Intrinsic::mips_slli_b:
1915  case Intrinsic::mips_slli_h:
1916  case Intrinsic::mips_slli_w:
1917  case Intrinsic::mips_slli_d:
1918    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1919                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1920  case Intrinsic::mips_splat_b:
1921  case Intrinsic::mips_splat_h:
1922  case Intrinsic::mips_splat_w:
1923  case Intrinsic::mips_splat_d:
1924    // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1925    // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1926    // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1927    // Instead we lower to MipsISD::VSHF and match from there.
1928    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1929                       lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1930                       Op->getOperand(1));
1931  case Intrinsic::mips_splati_b:
1932  case Intrinsic::mips_splati_h:
1933  case Intrinsic::mips_splati_w:
1934  case Intrinsic::mips_splati_d:
1935    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1936                       lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1937                       Op->getOperand(1));
1938  case Intrinsic::mips_sra_b:
1939  case Intrinsic::mips_sra_h:
1940  case Intrinsic::mips_sra_w:
1941  case Intrinsic::mips_sra_d:
1942    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1943                       Op->getOperand(2));
1944  case Intrinsic::mips_srai_b:
1945  case Intrinsic::mips_srai_h:
1946  case Intrinsic::mips_srai_w:
1947  case Intrinsic::mips_srai_d:
1948    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1949                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1950  case Intrinsic::mips_srl_b:
1951  case Intrinsic::mips_srl_h:
1952  case Intrinsic::mips_srl_w:
1953  case Intrinsic::mips_srl_d:
1954    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1955                       Op->getOperand(2));
1956  case Intrinsic::mips_srli_b:
1957  case Intrinsic::mips_srli_h:
1958  case Intrinsic::mips_srli_w:
1959  case Intrinsic::mips_srli_d:
1960    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1961                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1962  case Intrinsic::mips_subv_b:
1963  case Intrinsic::mips_subv_h:
1964  case Intrinsic::mips_subv_w:
1965  case Intrinsic::mips_subv_d:
1966    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1967                       Op->getOperand(2));
1968  case Intrinsic::mips_subvi_b:
1969  case Intrinsic::mips_subvi_h:
1970  case Intrinsic::mips_subvi_w:
1971  case Intrinsic::mips_subvi_d:
1972    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1973                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1974  case Intrinsic::mips_vshf_b:
1975  case Intrinsic::mips_vshf_h:
1976  case Intrinsic::mips_vshf_w:
1977  case Intrinsic::mips_vshf_d:
1978    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1979                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1980  case Intrinsic::mips_xor_v:
1981    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1982                       Op->getOperand(2));
1983  case Intrinsic::mips_xori_b:
1984    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1985                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1986  }
1987}
1988
1989static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1990  SDLoc DL(Op);
1991  SDValue ChainIn = Op->getOperand(0);
1992  SDValue Address = Op->getOperand(2);
1993  SDValue Offset  = Op->getOperand(3);
1994  EVT ResTy = Op->getValueType(0);
1995  EVT PtrTy = Address->getValueType(0);
1996
1997  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1998
1999  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2000                     false, false, 16);
2001}
2002
2003SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2004                                                     SelectionDAG &DAG) const {
2005  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2006  switch (Intr) {
2007  default:
2008    return SDValue();
2009  case Intrinsic::mips_extp:
2010    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2011  case Intrinsic::mips_extpdp:
2012    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2013  case Intrinsic::mips_extr_w:
2014    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2015  case Intrinsic::mips_extr_r_w:
2016    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2017  case Intrinsic::mips_extr_rs_w:
2018    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2019  case Intrinsic::mips_extr_s_h:
2020    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2021  case Intrinsic::mips_mthlip:
2022    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2023  case Intrinsic::mips_mulsaq_s_w_ph:
2024    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2025  case Intrinsic::mips_maq_s_w_phl:
2026    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2027  case Intrinsic::mips_maq_s_w_phr:
2028    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2029  case Intrinsic::mips_maq_sa_w_phl:
2030    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2031  case Intrinsic::mips_maq_sa_w_phr:
2032    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2033  case Intrinsic::mips_dpaq_s_w_ph:
2034    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2035  case Intrinsic::mips_dpsq_s_w_ph:
2036    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2037  case Intrinsic::mips_dpaq_sa_l_w:
2038    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2039  case Intrinsic::mips_dpsq_sa_l_w:
2040    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2041  case Intrinsic::mips_dpaqx_s_w_ph:
2042    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2043  case Intrinsic::mips_dpaqx_sa_w_ph:
2044    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2045  case Intrinsic::mips_dpsqx_s_w_ph:
2046    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2047  case Intrinsic::mips_dpsqx_sa_w_ph:
2048    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
2049  case Intrinsic::mips_ld_b:
2050  case Intrinsic::mips_ld_h:
2051  case Intrinsic::mips_ld_w:
2052  case Intrinsic::mips_ld_d:
2053   return lowerMSALoadIntr(Op, DAG, Intr);
2054  }
2055}
2056
2057static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2058  SDLoc DL(Op);
2059  SDValue ChainIn = Op->getOperand(0);
2060  SDValue Value   = Op->getOperand(2);
2061  SDValue Address = Op->getOperand(3);
2062  SDValue Offset  = Op->getOperand(4);
2063  EVT PtrTy = Address->getValueType(0);
2064
2065  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2066
2067  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2068                      false, 16);
2069}
2070
2071SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2072                                                  SelectionDAG &DAG) const {
2073  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2074  switch (Intr) {
2075  default:
2076    return SDValue();
2077  case Intrinsic::mips_st_b:
2078  case Intrinsic::mips_st_h:
2079  case Intrinsic::mips_st_w:
2080  case Intrinsic::mips_st_d:
2081    return lowerMSAStoreIntr(Op, DAG, Intr);
2082  }
2083}
2084
2085/// \brief Check if the given BuildVectorSDNode is a splat.
2086/// This method currently relies on DAG nodes being reused when equivalent,
2087/// so it's possible for this to return false even when isConstantSplat returns
2088/// true.
2089static bool isSplatVector(const BuildVectorSDNode *N) {
2090  unsigned int nOps = N->getNumOperands();
2091  assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
2092
2093  SDValue Operand0 = N->getOperand(0);
2094
2095  for (unsigned int i = 1; i < nOps; ++i) {
2096    if (N->getOperand(i) != Operand0)
2097      return false;
2098  }
2099
2100  return true;
2101}
2102
2103// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2104//
2105// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2106// choose to sign-extend but we could have equally chosen zero-extend. The
2107// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2108// result into this node later (possibly changing it to a zero-extend in the
2109// process).
2110SDValue MipsSETargetLowering::
2111lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2112  SDLoc DL(Op);
2113  EVT ResTy = Op->getValueType(0);
2114  SDValue Op0 = Op->getOperand(0);
2115  EVT VecTy = Op0->getValueType(0);
2116
2117  if (!VecTy.is128BitVector())
2118    return SDValue();
2119
2120  if (ResTy.isInteger()) {
2121    SDValue Op1 = Op->getOperand(1);
2122    EVT EltTy = VecTy.getVectorElementType();
2123    return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2124                       DAG.getValueType(EltTy));
2125  }
2126
2127  return Op;
2128}
2129
2130static bool isConstantOrUndef(const SDValue Op) {
2131  if (Op->getOpcode() == ISD::UNDEF)
2132    return true;
2133  if (dyn_cast<ConstantSDNode>(Op))
2134    return true;
2135  if (dyn_cast<ConstantFPSDNode>(Op))
2136    return true;
2137  return false;
2138}
2139
2140static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2141  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2142    if (isConstantOrUndef(Op->getOperand(i)))
2143      return true;
2144  return false;
2145}
2146
2147// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2148// backend.
2149//
2150// Lowers according to the following rules:
2151// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2152//   2 less than or equal to 64 and the value fits into a signed 10-bit
2153//   immediate
2154// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2155//   is a power of 2 less than or equal to 64 and the value does not fit into a
2156//   signed 10-bit immediate
2157// - Non-constant splats are legal as-is.
2158// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2159// - All others are illegal and must be expanded.
2160SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2161                                                SelectionDAG &DAG) const {
2162  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2163  EVT ResTy = Op->getValueType(0);
2164  SDLoc DL(Op);
2165  APInt SplatValue, SplatUndef;
2166  unsigned SplatBitSize;
2167  bool HasAnyUndefs;
2168
2169  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
2170    return SDValue();
2171
2172  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2173                            HasAnyUndefs, 8,
2174                            !Subtarget->isLittle()) && SplatBitSize <= 64) {
2175    // We can only cope with 8, 16, 32, or 64-bit elements
2176    if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2177        SplatBitSize != 64)
2178      return SDValue();
2179
2180    // If the value fits into a simm10 then we can use ldi.[bhwd]
2181    if (SplatValue.isSignedIntN(10))
2182      return Op;
2183
2184    EVT ViaVecTy;
2185
2186    switch (SplatBitSize) {
2187    default:
2188      return SDValue();
2189    case 8:
2190      ViaVecTy = MVT::v16i8;
2191      break;
2192    case 16:
2193      ViaVecTy = MVT::v8i16;
2194      break;
2195    case 32:
2196      ViaVecTy = MVT::v4i32;
2197      break;
2198    case 64:
2199      // There's no fill.d to fall back on for 64-bit values
2200      return SDValue();
2201    }
2202
2203    SmallVector<SDValue, 16> Ops;
2204    SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
2205
2206    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
2207      Ops.push_back(Constant);
2208
2209    SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
2210                                 &Ops[0], Ops.size());
2211
2212    if (ViaVecTy != ResTy)
2213      Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2214
2215    return Result;
2216  } else if (isSplatVector(Node))
2217    return Op;
2218  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
2219    // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2220    // The resulting code is the same length as the expansion, but it doesn't
2221    // use memory operations
2222    EVT ResTy = Node->getValueType(0);
2223
2224    assert(ResTy.isVector());
2225
2226    unsigned NumElts = ResTy.getVectorNumElements();
2227    SDValue Vector = DAG.getUNDEF(ResTy);
2228    for (unsigned i = 0; i < NumElts; ++i) {
2229      Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2230                           Node->getOperand(i),
2231                           DAG.getConstant(i, MVT::i32));
2232    }
2233    return Vector;
2234  }
2235
2236  return SDValue();
2237}
2238
2239// Lower VECTOR_SHUFFLE into SHF (if possible).
2240//
2241// SHF splits the vector into blocks of four elements, then shuffles these
2242// elements according to a <4 x i2> constant (encoded as an integer immediate).
2243//
2244// It is therefore possible to lower into SHF when the mask takes the form:
2245//   <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2246// When undef's appear they are treated as if they were whatever value is
2247// necessary in order to fit the above form.
2248//
2249// For example:
2250//   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2251//                      <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2252//                                 i32 7, i32 6, i32 5, i32 4>
2253// is lowered to:
2254//   (SHF_H $w0, $w1, 27)
2255// where the 27 comes from:
2256//   3 + (2 << 2) + (1 << 4) + (0 << 6)
2257static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2258                                       SmallVector<int, 16> Indices,
2259                                       SelectionDAG &DAG) {
2260  int SHFIndices[4] = { -1, -1, -1, -1 };
2261
2262  if (Indices.size() < 4)
2263    return SDValue();
2264
2265  for (unsigned i = 0; i < 4; ++i) {
2266    for (unsigned j = i; j < Indices.size(); j += 4) {
2267      int Idx = Indices[j];
2268
2269      // Convert from vector index to 4-element subvector index
2270      // If an index refers to an element outside of the subvector then give up
2271      if (Idx != -1) {
2272        Idx -= 4 * (j / 4);
2273        if (Idx < 0 || Idx >= 4)
2274          return SDValue();
2275      }
2276
2277      // If the mask has an undef, replace it with the current index.
2278      // Note that it might still be undef if the current index is also undef
2279      if (SHFIndices[i] == -1)
2280        SHFIndices[i] = Idx;
2281
2282      // Check that non-undef values are the same as in the mask. If they
2283      // aren't then give up
2284      if (!(Idx == -1 || Idx == SHFIndices[i]))
2285        return SDValue();
2286    }
2287  }
2288
2289  // Calculate the immediate. Replace any remaining undefs with zero
2290  APInt Imm(32, 0);
2291  for (int i = 3; i >= 0; --i) {
2292    int Idx = SHFIndices[i];
2293
2294    if (Idx == -1)
2295      Idx = 0;
2296
2297    Imm <<= 2;
2298    Imm |= Idx & 0x3;
2299  }
2300
2301  return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
2302                     DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
2303}
2304
2305// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2306//
2307// ILVEV interleaves the even elements from each vector.
2308//
2309// It is possible to lower into ILVEV when the mask takes the form:
2310//   <0, n, 2, n+2, 4, n+4, ...>
2311// where n is the number of elements in the vector.
2312//
2313// When undef's appear in the mask they are treated as if they were whatever
2314// value is necessary in order to fit the above form.
2315static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2316                                         SmallVector<int, 16> Indices,
2317                                         SelectionDAG &DAG) {
2318  assert ((Indices.size() % 2) == 0);
2319  int WsIdx = 0;
2320  int WtIdx = ResTy.getVectorNumElements();
2321
2322  for (unsigned i = 0; i < Indices.size(); i += 2) {
2323    if (Indices[i] != -1 && Indices[i] != WsIdx)
2324      return SDValue();
2325    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2326      return SDValue();
2327    WsIdx += 2;
2328    WtIdx += 2;
2329  }
2330
2331  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
2332                     Op->getOperand(1));
2333}
2334
2335// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2336//
2337// ILVOD interleaves the odd elements from each vector.
2338//
2339// It is possible to lower into ILVOD when the mask takes the form:
2340//   <1, n+1, 3, n+3, 5, n+5, ...>
2341// where n is the number of elements in the vector.
2342//
2343// When undef's appear in the mask they are treated as if they were whatever
2344// value is necessary in order to fit the above form.
2345static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2346                                         SmallVector<int, 16> Indices,
2347                                         SelectionDAG &DAG) {
2348  assert ((Indices.size() % 2) == 0);
2349  int WsIdx = 1;
2350  int WtIdx = ResTy.getVectorNumElements() + 1;
2351
2352  for (unsigned i = 0; i < Indices.size(); i += 2) {
2353    if (Indices[i] != -1 && Indices[i] != WsIdx)
2354      return SDValue();
2355    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2356      return SDValue();
2357    WsIdx += 2;
2358    WtIdx += 2;
2359  }
2360
2361  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2362                     Op->getOperand(1));
2363}
2364
2365// Lower VECTOR_SHUFFLE into ILVL (if possible).
2366//
2367// ILVL interleaves consecutive elements from the left half of each vector.
2368//
2369// It is possible to lower into ILVL when the mask takes the form:
2370//   <0, n, 1, n+1, 2, n+2, ...>
2371// where n is the number of elements in the vector.
2372//
2373// When undef's appear in the mask they are treated as if they were whatever
2374// value is necessary in order to fit the above form.
2375static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2376                                        SmallVector<int, 16> Indices,
2377                                        SelectionDAG &DAG) {
2378  assert ((Indices.size() % 2) == 0);
2379  int WsIdx = 0;
2380  int WtIdx = ResTy.getVectorNumElements();
2381
2382  for (unsigned i = 0; i < Indices.size(); i += 2) {
2383    if (Indices[i] != -1 && Indices[i] != WsIdx)
2384      return SDValue();
2385    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2386      return SDValue();
2387    WsIdx ++;
2388    WtIdx ++;
2389  }
2390
2391  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2392                     Op->getOperand(1));
2393}
2394
2395// Lower VECTOR_SHUFFLE into ILVR (if possible).
2396//
2397// ILVR interleaves consecutive elements from the right half of each vector.
2398//
2399// It is possible to lower into ILVR when the mask takes the form:
2400//   <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2401// where n is the number of elements in the vector and x is half n.
2402//
2403// When undef's appear in the mask they are treated as if they were whatever
2404// value is necessary in order to fit the above form.
2405static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2406                                        SmallVector<int, 16> Indices,
2407                                        SelectionDAG &DAG) {
2408  assert ((Indices.size() % 2) == 0);
2409  unsigned NumElts = ResTy.getVectorNumElements();
2410  int WsIdx = NumElts / 2;
2411  int WtIdx = NumElts + NumElts / 2;
2412
2413  for (unsigned i = 0; i < Indices.size(); i += 2) {
2414    if (Indices[i] != -1 && Indices[i] != WsIdx)
2415      return SDValue();
2416    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2417      return SDValue();
2418    WsIdx ++;
2419    WtIdx ++;
2420  }
2421
2422  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2423                     Op->getOperand(1));
2424}
2425
2426// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2427//
2428// PCKEV copies the even elements of each vector into the result vector.
2429//
2430// It is possible to lower into PCKEV when the mask takes the form:
2431//   <0, 2, 4, ..., n, n+2, n+4, ...>
2432// where n is the number of elements in the vector.
2433//
2434// When undef's appear in the mask they are treated as if they were whatever
2435// value is necessary in order to fit the above form.
2436static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2437                                         SmallVector<int, 16> Indices,
2438                                         SelectionDAG &DAG) {
2439  assert ((Indices.size() % 2) == 0);
2440  int Idx = 0;
2441
2442  for (unsigned i = 0; i < Indices.size(); ++i) {
2443    if (Indices[i] != -1 && Indices[i] != Idx)
2444      return SDValue();
2445    Idx += 2;
2446  }
2447
2448  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2449                     Op->getOperand(1));
2450}
2451
2452// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2453//
2454// PCKOD copies the odd elements of each vector into the result vector.
2455//
2456// It is possible to lower into PCKOD when the mask takes the form:
2457//   <1, 3, 5, ..., n+1, n+3, n+5, ...>
2458// where n is the number of elements in the vector.
2459//
2460// When undef's appear in the mask they are treated as if they were whatever
2461// value is necessary in order to fit the above form.
2462static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2463                                         SmallVector<int, 16> Indices,
2464                                         SelectionDAG &DAG) {
2465  assert ((Indices.size() % 2) == 0);
2466  int Idx = 1;
2467
2468  for (unsigned i = 0; i < Indices.size(); ++i) {
2469    if (Indices[i] != -1 && Indices[i] != Idx)
2470      return SDValue();
2471    Idx += 2;
2472  }
2473
2474  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2475                     Op->getOperand(1));
2476}
2477
2478// Lower VECTOR_SHUFFLE into VSHF.
2479//
2480// This mostly consists of converting the shuffle indices in Indices into a
2481// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2482// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2483// if the type is v8i16 and all the indices are less than 8 then the second
2484// operand is unused and can be replaced with anything. We choose to replace it
2485// with the used operand since this reduces the number of instructions overall.
2486static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2487                                        SmallVector<int, 16> Indices,
2488                                        SelectionDAG &DAG) {
2489  SmallVector<SDValue, 16> Ops;
2490  SDValue Op0;
2491  SDValue Op1;
2492  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2493  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2494  bool Using1stVec = false;
2495  bool Using2ndVec = false;
2496  SDLoc DL(Op);
2497  int ResTyNumElts = ResTy.getVectorNumElements();
2498
2499  for (int i = 0; i < ResTyNumElts; ++i) {
2500    // Idx == -1 means UNDEF
2501    int Idx = Indices[i];
2502
2503    if (0 <= Idx && Idx < ResTyNumElts)
2504      Using1stVec = true;
2505    if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2506      Using2ndVec = true;
2507  }
2508
2509  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2510       ++I)
2511    Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2512
2513  SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2514                                Ops.size());
2515
2516  if (Using1stVec && Using2ndVec) {
2517    Op0 = Op->getOperand(0);
2518    Op1 = Op->getOperand(1);
2519  } else if (Using1stVec)
2520    Op0 = Op1 = Op->getOperand(0);
2521  else if (Using2ndVec)
2522    Op0 = Op1 = Op->getOperand(1);
2523  else
2524    llvm_unreachable("shuffle vector mask references neither vector operand?");
2525
2526  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2527}
2528
2529// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2530// indices in the shuffle.
2531SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2532                                                  SelectionDAG &DAG) const {
2533  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2534  EVT ResTy = Op->getValueType(0);
2535
2536  if (!ResTy.is128BitVector())
2537    return SDValue();
2538
2539  int ResTyNumElts = ResTy.getVectorNumElements();
2540  SmallVector<int, 16> Indices;
2541
2542  for (int i = 0; i < ResTyNumElts; ++i)
2543    Indices.push_back(Node->getMaskElt(i));
2544
2545  SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2546  if (Result.getNode())
2547    return Result;
2548  Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2549  if (Result.getNode())
2550    return Result;
2551  Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2552  if (Result.getNode())
2553    return Result;
2554  Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2555  if (Result.getNode())
2556    return Result;
2557  Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2558  if (Result.getNode())
2559    return Result;
2560  Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2561  if (Result.getNode())
2562    return Result;
2563  Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2564  if (Result.getNode())
2565    return Result;
2566  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2567}
2568
2569MachineBasicBlock * MipsSETargetLowering::
2570emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2571  // $bb:
2572  //  bposge32_pseudo $vr0
2573  //  =>
2574  // $bb:
2575  //  bposge32 $tbb
2576  // $fbb:
2577  //  li $vr2, 0
2578  //  b $sink
2579  // $tbb:
2580  //  li $vr1, 1
2581  // $sink:
2582  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2583
2584  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2585  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2586  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2587  DebugLoc DL = MI->getDebugLoc();
2588  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2589  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2590  MachineFunction *F = BB->getParent();
2591  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2592  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2593  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2594  F->insert(It, FBB);
2595  F->insert(It, TBB);
2596  F->insert(It, Sink);
2597
2598  // Transfer the remainder of BB and its successor edges to Sink.
2599  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2600               BB->end());
2601  Sink->transferSuccessorsAndUpdatePHIs(BB);
2602
2603  // Add successors.
2604  BB->addSuccessor(FBB);
2605  BB->addSuccessor(TBB);
2606  FBB->addSuccessor(Sink);
2607  TBB->addSuccessor(Sink);
2608
2609  // Insert the real bposge32 instruction to $BB.
2610  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2611
2612  // Fill $FBB.
2613  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2614  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2615    .addReg(Mips::ZERO).addImm(0);
2616  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2617
2618  // Fill $TBB.
2619  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2620  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2621    .addReg(Mips::ZERO).addImm(1);
2622
2623  // Insert phi function to $Sink.
2624  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2625          MI->getOperand(0).getReg())
2626    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2627
2628  MI->eraseFromParent();   // The pseudo instruction is gone now.
2629  return Sink;
2630}
2631
2632MachineBasicBlock * MipsSETargetLowering::
2633emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2634                     unsigned BranchOp) const{
2635  // $bb:
2636  //  vany_nonzero $rd, $ws
2637  //  =>
2638  // $bb:
2639  //  bnz.b $ws, $tbb
2640  //  b $fbb
2641  // $fbb:
2642  //  li $rd1, 0
2643  //  b $sink
2644  // $tbb:
2645  //  li $rd2, 1
2646  // $sink:
2647  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
2648
2649  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2650  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2651  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2652  DebugLoc DL = MI->getDebugLoc();
2653  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2654  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2655  MachineFunction *F = BB->getParent();
2656  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2657  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2658  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2659  F->insert(It, FBB);
2660  F->insert(It, TBB);
2661  F->insert(It, Sink);
2662
2663  // Transfer the remainder of BB and its successor edges to Sink.
2664  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2665               BB->end());
2666  Sink->transferSuccessorsAndUpdatePHIs(BB);
2667
2668  // Add successors.
2669  BB->addSuccessor(FBB);
2670  BB->addSuccessor(TBB);
2671  FBB->addSuccessor(Sink);
2672  TBB->addSuccessor(Sink);
2673
2674  // Insert the real bnz.b instruction to $BB.
2675  BuildMI(BB, DL, TII->get(BranchOp))
2676    .addReg(MI->getOperand(1).getReg())
2677    .addMBB(TBB);
2678
2679  // Fill $FBB.
2680  unsigned RD1 = RegInfo.createVirtualRegister(RC);
2681  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2682    .addReg(Mips::ZERO).addImm(0);
2683  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2684
2685  // Fill $TBB.
2686  unsigned RD2 = RegInfo.createVirtualRegister(RC);
2687  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2688    .addReg(Mips::ZERO).addImm(1);
2689
2690  // Insert phi function to $Sink.
2691  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2692          MI->getOperand(0).getReg())
2693    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2694
2695  MI->eraseFromParent();   // The pseudo instruction is gone now.
2696  return Sink;
2697}
2698
2699// Emit the COPY_FW pseudo instruction.
2700//
2701// copy_fw_pseudo $fd, $ws, n
2702// =>
2703// copy_u_w $rt, $ws, $n
2704// mtc1     $rt, $fd
2705//
2706// When n is zero, the equivalent operation can be performed with (potentially)
2707// zero instructions due to register overlaps. This optimization is never valid
2708// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2709MachineBasicBlock * MipsSETargetLowering::
2710emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2711  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2712  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2713  DebugLoc DL = MI->getDebugLoc();
2714  unsigned Fd = MI->getOperand(0).getReg();
2715  unsigned Ws = MI->getOperand(1).getReg();
2716  unsigned Lane = MI->getOperand(2).getImm();
2717
2718  if (Lane == 0)
2719    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2720  else {
2721    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2722
2723    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2724    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2725  }
2726
2727  MI->eraseFromParent();   // The pseudo instruction is gone now.
2728  return BB;
2729}
2730
2731// Emit the COPY_FD pseudo instruction.
2732//
2733// copy_fd_pseudo $fd, $ws, n
2734// =>
2735// splati.d $wt, $ws, $n
2736// copy $fd, $wt:sub_64
2737//
2738// When n is zero, the equivalent operation can be performed with (potentially)
2739// zero instructions due to register overlaps. This optimization is always
2740// valid because FR=1 mode which is the only supported mode in MSA.
2741MachineBasicBlock * MipsSETargetLowering::
2742emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2743  assert(Subtarget->isFP64bit());
2744
2745  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2746  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2747  unsigned Fd  = MI->getOperand(0).getReg();
2748  unsigned Ws  = MI->getOperand(1).getReg();
2749  unsigned Lane = MI->getOperand(2).getImm() * 2;
2750  DebugLoc DL = MI->getDebugLoc();
2751
2752  if (Lane == 0)
2753    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2754  else {
2755    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2756
2757    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2758    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2759  }
2760
2761  MI->eraseFromParent();   // The pseudo instruction is gone now.
2762  return BB;
2763}
2764
2765// Emit the INSERT_FW pseudo instruction.
2766//
2767// insert_fw_pseudo $wd, $wd_in, $n, $fs
2768// =>
2769// subreg_to_reg $wt:sub_lo, $fs
2770// insve_w $wd[$n], $wd_in, $wt[0]
2771MachineBasicBlock *
2772MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2773                                    MachineBasicBlock *BB) const {
2774  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2775  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2776  DebugLoc DL = MI->getDebugLoc();
2777  unsigned Wd = MI->getOperand(0).getReg();
2778  unsigned Wd_in = MI->getOperand(1).getReg();
2779  unsigned Lane = MI->getOperand(2).getImm();
2780  unsigned Fs = MI->getOperand(3).getReg();
2781  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2782
2783  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2784      .addImm(0)
2785      .addReg(Fs)
2786      .addImm(Mips::sub_lo);
2787  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2788      .addReg(Wd_in)
2789      .addImm(Lane)
2790      .addReg(Wt);
2791
2792  MI->eraseFromParent(); // The pseudo instruction is gone now.
2793  return BB;
2794}
2795
2796// Emit the INSERT_FD pseudo instruction.
2797//
2798// insert_fd_pseudo $wd, $fs, n
2799// =>
2800// subreg_to_reg $wt:sub_64, $fs
2801// insve_d $wd[$n], $wd_in, $wt[0]
2802MachineBasicBlock *
2803MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2804                                    MachineBasicBlock *BB) const {
2805  assert(Subtarget->isFP64bit());
2806
2807  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2808  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2809  DebugLoc DL = MI->getDebugLoc();
2810  unsigned Wd = MI->getOperand(0).getReg();
2811  unsigned Wd_in = MI->getOperand(1).getReg();
2812  unsigned Lane = MI->getOperand(2).getImm();
2813  unsigned Fs = MI->getOperand(3).getReg();
2814  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2815
2816  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2817      .addImm(0)
2818      .addReg(Fs)
2819      .addImm(Mips::sub_64);
2820  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2821      .addReg(Wd_in)
2822      .addImm(Lane)
2823      .addReg(Wt);
2824
2825  MI->eraseFromParent(); // The pseudo instruction is gone now.
2826  return BB;
2827}
2828
2829// Emit the FILL_FW pseudo instruction.
2830//
2831// fill_fw_pseudo $wd, $fs
2832// =>
2833// implicit_def $wt1
2834// insert_subreg $wt2:subreg_lo, $wt1, $fs
2835// splati.w $wd, $wt2[0]
2836MachineBasicBlock *
2837MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2838                                  MachineBasicBlock *BB) const {
2839  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2840  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2841  DebugLoc DL = MI->getDebugLoc();
2842  unsigned Wd = MI->getOperand(0).getReg();
2843  unsigned Fs = MI->getOperand(1).getReg();
2844  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2845  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2846
2847  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2848  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2849      .addReg(Wt1)
2850      .addReg(Fs)
2851      .addImm(Mips::sub_lo);
2852  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2853
2854  MI->eraseFromParent(); // The pseudo instruction is gone now.
2855  return BB;
2856}
2857
2858// Emit the FILL_FD pseudo instruction.
2859//
2860// fill_fd_pseudo $wd, $fs
2861// =>
2862// implicit_def $wt1
2863// insert_subreg $wt2:subreg_64, $wt1, $fs
2864// splati.d $wd, $wt2[0]
2865MachineBasicBlock *
2866MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2867                                  MachineBasicBlock *BB) const {
2868  assert(Subtarget->isFP64bit());
2869
2870  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2871  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2872  DebugLoc DL = MI->getDebugLoc();
2873  unsigned Wd = MI->getOperand(0).getReg();
2874  unsigned Fs = MI->getOperand(1).getReg();
2875  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2876  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2877
2878  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2879  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2880      .addReg(Wt1)
2881      .addReg(Fs)
2882      .addImm(Mips::sub_64);
2883  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2884
2885  MI->eraseFromParent();   // The pseudo instruction is gone now.
2886  return BB;
2887}
2888
2889// Emit the FEXP2_W_1 pseudo instructions.
2890//
2891// fexp2_w_1_pseudo $wd, $wt
2892// =>
2893// ldi.w $ws, 1
2894// fexp2.w $wd, $ws, $wt
2895MachineBasicBlock *
2896MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2897                                    MachineBasicBlock *BB) const {
2898  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2899  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2900  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2901  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2902  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2903  DebugLoc DL = MI->getDebugLoc();
2904
2905  // Splat 1.0 into a vector
2906  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2907  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2908
2909  // Emit 1.0 * fexp2(Wt)
2910  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2911      .addReg(Ws2)
2912      .addReg(MI->getOperand(1).getReg());
2913
2914  MI->eraseFromParent(); // The pseudo instruction is gone now.
2915  return BB;
2916}
2917
2918// Emit the FEXP2_D_1 pseudo instructions.
2919//
2920// fexp2_d_1_pseudo $wd, $wt
2921// =>
2922// ldi.d $ws, 1
2923// fexp2.d $wd, $ws, $wt
2924MachineBasicBlock *
2925MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2926                                    MachineBasicBlock *BB) const {
2927  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2928  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2929  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2930  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2931  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2932  DebugLoc DL = MI->getDebugLoc();
2933
2934  // Splat 1.0 into a vector
2935  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2936  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2937
2938  // Emit 1.0 * fexp2(Wt)
2939  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2940      .addReg(Ws2)
2941      .addReg(MI->getOperand(1).getReg());
2942
2943  MI->eraseFromParent(); // The pseudo instruction is gone now.
2944  return BB;
2945}
2946