MipsSEISelLowering.cpp revision acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93
94    setTargetDAGCombine(ISD::AND);
95    setTargetDAGCombine(ISD::SRA);
96    setTargetDAGCombine(ISD::VSELECT);
97    setTargetDAGCombine(ISD::XOR);
98  }
99
100  if (!Subtarget->mipsSEUsesSoftFloat()) {
101    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
102
103    // When dealing with single precision only, use libcalls
104    if (!Subtarget->isSingleFloat()) {
105      if (Subtarget->isFP64bit())
106        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
107      else
108        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
109    }
110  }
111
112  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
113  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
114  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
115  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
116
117  if (HasMips64) {
118    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
119    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
120    setOperationAction(ISD::MUL,              MVT::i64, Custom);
121  }
122
123  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
124  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
125
126  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
127  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
128  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
129  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
130  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
131  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
132  setOperationAction(ISD::STORE,              MVT::i32, Custom);
133
134  setTargetDAGCombine(ISD::ADDE);
135  setTargetDAGCombine(ISD::SUBE);
136  setTargetDAGCombine(ISD::MUL);
137
138  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
139  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
140  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141
142  if (NoDPLoadStore) {
143    setOperationAction(ISD::LOAD, MVT::f64, Custom);
144    setOperationAction(ISD::STORE, MVT::f64, Custom);
145  }
146
147  computeRegisterProperties();
148}
149
150const MipsTargetLowering *
151llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
152  return new MipsSETargetLowering(TM);
153}
154
155// Enable MSA support for the given integer type and Register class.
156void MipsSETargetLowering::
157addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
158  addRegisterClass(Ty, RC);
159
160  // Expand all builtin opcodes.
161  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
162    setOperationAction(Opc, Ty, Expand);
163
164  setOperationAction(ISD::BITCAST, Ty, Legal);
165  setOperationAction(ISD::LOAD, Ty, Legal);
166  setOperationAction(ISD::STORE, Ty, Legal);
167  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
168  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
169  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
170
171  setOperationAction(ISD::ADD, Ty, Legal);
172  setOperationAction(ISD::AND, Ty, Legal);
173  setOperationAction(ISD::CTLZ, Ty, Legal);
174  setOperationAction(ISD::CTPOP, Ty, Legal);
175  setOperationAction(ISD::MUL, Ty, Legal);
176  setOperationAction(ISD::OR, Ty, Legal);
177  setOperationAction(ISD::SDIV, Ty, Legal);
178  setOperationAction(ISD::SHL, Ty, Legal);
179  setOperationAction(ISD::SRA, Ty, Legal);
180  setOperationAction(ISD::SRL, Ty, Legal);
181  setOperationAction(ISD::SUB, Ty, Legal);
182  setOperationAction(ISD::UDIV, Ty, Legal);
183  setOperationAction(ISD::VSELECT, Ty, Legal);
184  setOperationAction(ISD::XOR, Ty, Legal);
185
186  setOperationAction(ISD::SETCC, Ty, Legal);
187  setCondCodeAction(ISD::SETNE, Ty, Expand);
188  setCondCodeAction(ISD::SETGE, Ty, Expand);
189  setCondCodeAction(ISD::SETGT, Ty, Expand);
190  setCondCodeAction(ISD::SETUGE, Ty, Expand);
191  setCondCodeAction(ISD::SETUGT, Ty, Expand);
192}
193
194// Enable MSA support for the given floating-point type and Register class.
195void MipsSETargetLowering::
196addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
197  addRegisterClass(Ty, RC);
198
199  // Expand all builtin opcodes.
200  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
201    setOperationAction(Opc, Ty, Expand);
202
203  setOperationAction(ISD::LOAD, Ty, Legal);
204  setOperationAction(ISD::STORE, Ty, Legal);
205  setOperationAction(ISD::BITCAST, Ty, Legal);
206  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
207
208  if (Ty != MVT::v8f16) {
209    setOperationAction(ISD::FABS,  Ty, Legal);
210    setOperationAction(ISD::FADD,  Ty, Legal);
211    setOperationAction(ISD::FDIV,  Ty, Legal);
212    setOperationAction(ISD::FLOG2, Ty, Legal);
213    setOperationAction(ISD::FMUL,  Ty, Legal);
214    setOperationAction(ISD::FRINT, Ty, Legal);
215    setOperationAction(ISD::FSQRT, Ty, Legal);
216    setOperationAction(ISD::FSUB,  Ty, Legal);
217    setOperationAction(ISD::VSELECT, Ty, Legal);
218
219    setOperationAction(ISD::SETCC, Ty, Legal);
220    setCondCodeAction(ISD::SETOGE, Ty, Expand);
221    setCondCodeAction(ISD::SETOGT, Ty, Expand);
222    setCondCodeAction(ISD::SETUGE, Ty, Expand);
223    setCondCodeAction(ISD::SETUGT, Ty, Expand);
224    setCondCodeAction(ISD::SETGE,  Ty, Expand);
225    setCondCodeAction(ISD::SETGT,  Ty, Expand);
226  }
227}
228
229bool
230MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
231  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
232
233  switch (SVT) {
234  case MVT::i64:
235  case MVT::i32:
236    if (Fast)
237      *Fast = true;
238    return true;
239  default:
240    return false;
241  }
242}
243
244SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
245                                             SelectionDAG &DAG) const {
246  switch(Op.getOpcode()) {
247  case ISD::LOAD:  return lowerLOAD(Op, DAG);
248  case ISD::STORE: return lowerSTORE(Op, DAG);
249  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
250  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
251  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
252  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
253  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
254  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
255  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
256                                          DAG);
257  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
258  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
259  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
260  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
261  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
262  }
263
264  return MipsTargetLowering::LowerOperation(Op, DAG);
265}
266
267// selectMADD -
268// Transforms a subgraph in CurDAG if the following pattern is found:
269//  (addc multLo, Lo0), (adde multHi, Hi0),
270// where,
271//  multHi/Lo: product of multiplication
272//  Lo0: initial value of Lo register
273//  Hi0: initial value of Hi register
274// Return true if pattern matching was successful.
275static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
276  // ADDENode's second operand must be a flag output of an ADDC node in order
277  // for the matching to be successful.
278  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
279
280  if (ADDCNode->getOpcode() != ISD::ADDC)
281    return false;
282
283  SDValue MultHi = ADDENode->getOperand(0);
284  SDValue MultLo = ADDCNode->getOperand(0);
285  SDNode *MultNode = MultHi.getNode();
286  unsigned MultOpc = MultHi.getOpcode();
287
288  // MultHi and MultLo must be generated by the same node,
289  if (MultLo.getNode() != MultNode)
290    return false;
291
292  // and it must be a multiplication.
293  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
294    return false;
295
296  // MultLo amd MultHi must be the first and second output of MultNode
297  // respectively.
298  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
299    return false;
300
301  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
302  // of the values of MultNode, in which case MultNode will be removed in later
303  // phases.
304  // If there exist users other than ADDENode or ADDCNode, this function returns
305  // here, which will result in MultNode being mapped to a single MULT
306  // instruction node rather than a pair of MULT and MADD instructions being
307  // produced.
308  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
309    return false;
310
311  SDLoc DL(ADDENode);
312
313  // Initialize accumulator.
314  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
315                                  ADDCNode->getOperand(1),
316                                  ADDENode->getOperand(1));
317
318  // create MipsMAdd(u) node
319  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
320
321  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
322                                 MultNode->getOperand(0),// Factor 0
323                                 MultNode->getOperand(1),// Factor 1
324                                 ACCIn);
325
326  // replace uses of adde and addc here
327  if (!SDValue(ADDCNode, 0).use_empty()) {
328    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
329    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
330                                    LoIdx);
331    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
332  }
333  if (!SDValue(ADDENode, 0).use_empty()) {
334    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
335    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
336                                    HiIdx);
337    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
338  }
339
340  return true;
341}
342
343// selectMSUB -
344// Transforms a subgraph in CurDAG if the following pattern is found:
345//  (addc Lo0, multLo), (sube Hi0, multHi),
346// where,
347//  multHi/Lo: product of multiplication
348//  Lo0: initial value of Lo register
349//  Hi0: initial value of Hi register
350// Return true if pattern matching was successful.
351static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
352  // SUBENode's second operand must be a flag output of an SUBC node in order
353  // for the matching to be successful.
354  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
355
356  if (SUBCNode->getOpcode() != ISD::SUBC)
357    return false;
358
359  SDValue MultHi = SUBENode->getOperand(1);
360  SDValue MultLo = SUBCNode->getOperand(1);
361  SDNode *MultNode = MultHi.getNode();
362  unsigned MultOpc = MultHi.getOpcode();
363
364  // MultHi and MultLo must be generated by the same node,
365  if (MultLo.getNode() != MultNode)
366    return false;
367
368  // and it must be a multiplication.
369  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
370    return false;
371
372  // MultLo amd MultHi must be the first and second output of MultNode
373  // respectively.
374  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
375    return false;
376
377  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
378  // of the values of MultNode, in which case MultNode will be removed in later
379  // phases.
380  // If there exist users other than SUBENode or SUBCNode, this function returns
381  // here, which will result in MultNode being mapped to a single MULT
382  // instruction node rather than a pair of MULT and MSUB instructions being
383  // produced.
384  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
385    return false;
386
387  SDLoc DL(SUBENode);
388
389  // Initialize accumulator.
390  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
391                                  SUBCNode->getOperand(0),
392                                  SUBENode->getOperand(0));
393
394  // create MipsSub(u) node
395  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
396
397  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
398                                 MultNode->getOperand(0),// Factor 0
399                                 MultNode->getOperand(1),// Factor 1
400                                 ACCIn);
401
402  // replace uses of sube and subc here
403  if (!SDValue(SUBCNode, 0).use_empty()) {
404    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
405    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
406                                    LoIdx);
407    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
408  }
409  if (!SDValue(SUBENode, 0).use_empty()) {
410    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
411    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
412                                    HiIdx);
413    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
414  }
415
416  return true;
417}
418
419static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
420                                  TargetLowering::DAGCombinerInfo &DCI,
421                                  const MipsSubtarget *Subtarget) {
422  if (DCI.isBeforeLegalize())
423    return SDValue();
424
425  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
426      selectMADD(N, &DAG))
427    return SDValue(N, 0);
428
429  return SDValue();
430}
431
432// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
433//
434// Performs the following transformations:
435// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
436//   sign/zero-extension is completely overwritten by the new one performed by
437//   the ISD::AND.
438// - Removes redundant zero extensions performed by an ISD::AND.
439static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
440                                 TargetLowering::DAGCombinerInfo &DCI,
441                                 const MipsSubtarget *Subtarget) {
442  if (!Subtarget->hasMSA())
443    return SDValue();
444
445  SDValue Op0 = N->getOperand(0);
446  SDValue Op1 = N->getOperand(1);
447  unsigned Op0Opcode = Op0->getOpcode();
448
449  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
450  // where $d + 1 == 2^n and n == 32
451  // or    $d + 1 == 2^n and n <= 32 and ZExt
452  // -> (MipsVExtractZExt $a, $b, $c)
453  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
454      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
455    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
456
457    if (!Mask)
458      return SDValue();
459
460    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
461
462    if (Log2IfPositive <= 0)
463      return SDValue(); // Mask+1 is not a power of 2
464
465    SDValue Op0Op2 = Op0->getOperand(2);
466    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
467    unsigned ExtendTySize = ExtendTy.getSizeInBits();
468    unsigned Log2 = Log2IfPositive;
469
470    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
471        Log2 == ExtendTySize) {
472      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
473      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
474                      Op0->getVTList(), Ops, Op0->getNumOperands());
475      return Op0;
476    }
477  }
478
479  return SDValue();
480}
481
482static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
483                                  TargetLowering::DAGCombinerInfo &DCI,
484                                  const MipsSubtarget *Subtarget) {
485  if (DCI.isBeforeLegalize())
486    return SDValue();
487
488  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
489      selectMSUB(N, &DAG))
490    return SDValue(N, 0);
491
492  return SDValue();
493}
494
495static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
496                            EVT ShiftTy, SelectionDAG &DAG) {
497  // Clear the upper (64 - VT.sizeInBits) bits.
498  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
499
500  // Return 0.
501  if (C == 0)
502    return DAG.getConstant(0, VT);
503
504  // Return x.
505  if (C == 1)
506    return X;
507
508  // If c is power of 2, return (shl x, log2(c)).
509  if (isPowerOf2_64(C))
510    return DAG.getNode(ISD::SHL, DL, VT, X,
511                       DAG.getConstant(Log2_64(C), ShiftTy));
512
513  unsigned Log2Ceil = Log2_64_Ceil(C);
514  uint64_t Floor = 1LL << Log2_64(C);
515  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
516
517  // If |c - floor_c| <= |c - ceil_c|,
518  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
519  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
520  if (C - Floor <= Ceil - C) {
521    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
522    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
523    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
524  }
525
526  // If |c - floor_c| > |c - ceil_c|,
527  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
528  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
529  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
530  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
531}
532
533static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
534                                 const TargetLowering::DAGCombinerInfo &DCI,
535                                 const MipsSETargetLowering *TL) {
536  EVT VT = N->getValueType(0);
537
538  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
539    if (!VT.isVector())
540      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
541                          VT, TL->getScalarShiftAmountTy(VT), DAG);
542
543  return SDValue(N, 0);
544}
545
546static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
547                                      SelectionDAG &DAG,
548                                      const MipsSubtarget *Subtarget) {
549  // See if this is a vector splat immediate node.
550  APInt SplatValue, SplatUndef;
551  unsigned SplatBitSize;
552  bool HasAnyUndefs;
553  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
554  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
555
556  if (!BV ||
557      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
558                           EltSize, !Subtarget->isLittle()) ||
559      (SplatBitSize != EltSize) ||
560      (SplatValue.getZExtValue() >= EltSize))
561    return SDValue();
562
563  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
564                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
565}
566
567static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
568                                 TargetLowering::DAGCombinerInfo &DCI,
569                                 const MipsSubtarget *Subtarget) {
570  EVT Ty = N->getValueType(0);
571
572  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
573    return SDValue();
574
575  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
576}
577
578// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
579// constant splats into MipsISD::SHRA_DSP for DSPr2.
580//
581// Performs the following transformations:
582// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
583//   sign/zero-extension is completely overwritten by the new one performed by
584//   the ISD::SRA and ISD::SHL nodes.
585// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
586//   sequence.
587//
588// See performDSPShiftCombine for more information about the transformation
589// used for DSPr2.
590static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
591                                 TargetLowering::DAGCombinerInfo &DCI,
592                                 const MipsSubtarget *Subtarget) {
593  EVT Ty = N->getValueType(0);
594
595  if (Subtarget->hasMSA()) {
596    SDValue Op0 = N->getOperand(0);
597    SDValue Op1 = N->getOperand(1);
598
599    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
600    // where $d + sizeof($c) == 32
601    // or    $d + sizeof($c) <= 32 and SExt
602    // -> (MipsVExtractSExt $a, $b, $c)
603    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
604      SDValue Op0Op0 = Op0->getOperand(0);
605      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
606
607      if (!ShAmount)
608        return SDValue();
609
610      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
611      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
612
613      if (TotalBits == 32 ||
614          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
615           TotalBits <= 32)) {
616        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
617                          Op0Op0->getOperand(2) };
618        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
619                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
620        return Op0Op0;
621      }
622    }
623  }
624
625  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
626    return SDValue();
627
628  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
629}
630
631
632static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
633                                 TargetLowering::DAGCombinerInfo &DCI,
634                                 const MipsSubtarget *Subtarget) {
635  EVT Ty = N->getValueType(0);
636
637  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
638    return SDValue();
639
640  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
641}
642
643static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
644  bool IsV216 = (Ty == MVT::v2i16);
645
646  switch (CC) {
647  case ISD::SETEQ:
648  case ISD::SETNE:  return true;
649  case ISD::SETLT:
650  case ISD::SETLE:
651  case ISD::SETGT:
652  case ISD::SETGE:  return IsV216;
653  case ISD::SETULT:
654  case ISD::SETULE:
655  case ISD::SETUGT:
656  case ISD::SETUGE: return !IsV216;
657  default:          return false;
658  }
659}
660
661static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
662  EVT Ty = N->getValueType(0);
663
664  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
665    return SDValue();
666
667  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
668    return SDValue();
669
670  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
671                     N->getOperand(1), N->getOperand(2));
672}
673
674static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
675  EVT Ty = N->getValueType(0);
676
677  if (Ty.is128BitVector() && Ty.isInteger()) {
678    // Try the following combines:
679    //   (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
680    //   (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
681    //   (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
682    //   (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
683    //   (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
684    //   (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
685    //   (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
686    //   (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
687    // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
688    // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
689    // legalizer.
690    SDValue Op0 = N->getOperand(0);
691
692    if (Op0->getOpcode() != ISD::SETCC)
693      return SDValue();
694
695    ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
696    bool Signed;
697
698    if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)
699      Signed = true;
700    else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
701      Signed = false;
702    else
703      return SDValue();
704
705    SDValue Op1 = N->getOperand(1);
706    SDValue Op2 = N->getOperand(2);
707    SDValue Op0Op0 = Op0->getOperand(0);
708    SDValue Op0Op1 = Op0->getOperand(1);
709
710    if (Op1 == Op0Op0 && Op2 == Op0Op1)
711      return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
712                         Ty, Op1, Op2);
713    else if (Op1 == Op0Op1 && Op2 == Op0Op0)
714      return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
715                         Ty, Op1, Op2);
716  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
717    SDValue SetCC = N->getOperand(0);
718
719    if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
720      return SDValue();
721
722    return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
723                       SetCC.getOperand(0), SetCC.getOperand(1),
724                       N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
725  }
726
727  return SDValue();
728}
729
730static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
731                                 const MipsSubtarget *Subtarget) {
732  EVT Ty = N->getValueType(0);
733
734  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
735    // Try the following combines:
736    //   (xor (or $a, $b), (build_vector allones))
737    //   (xor (or $a, $b), (bitcast (build_vector allones)))
738    SDValue Op0 = N->getOperand(0);
739    SDValue Op1 = N->getOperand(1);
740    SDValue NotOp;
741
742    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
743      NotOp = Op1;
744    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
745      NotOp = Op0;
746    else
747      return SDValue();
748
749    if (NotOp->getOpcode() == ISD::OR)
750      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
751                         NotOp->getOperand(1));
752  }
753
754  return SDValue();
755}
756
757SDValue
758MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
759  SelectionDAG &DAG = DCI.DAG;
760  SDValue Val;
761
762  switch (N->getOpcode()) {
763  case ISD::ADDE:
764    return performADDECombine(N, DAG, DCI, Subtarget);
765  case ISD::AND:
766    Val = performANDCombine(N, DAG, DCI, Subtarget);
767    break;
768  case ISD::SUBE:
769    return performSUBECombine(N, DAG, DCI, Subtarget);
770  case ISD::MUL:
771    return performMULCombine(N, DAG, DCI, this);
772  case ISD::SHL:
773    return performSHLCombine(N, DAG, DCI, Subtarget);
774  case ISD::SRA:
775    return performSRACombine(N, DAG, DCI, Subtarget);
776  case ISD::SRL:
777    return performSRLCombine(N, DAG, DCI, Subtarget);
778  case ISD::VSELECT:
779    return performVSELECTCombine(N, DAG);
780  case ISD::XOR:
781    Val = performXORCombine(N, DAG, Subtarget);
782    break;
783  case ISD::SETCC:
784    Val = performSETCCCombine(N, DAG);
785    break;
786  }
787
788  if (Val.getNode())
789    return Val;
790
791  return MipsTargetLowering::PerformDAGCombine(N, DCI);
792}
793
794MachineBasicBlock *
795MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
796                                                  MachineBasicBlock *BB) const {
797  switch (MI->getOpcode()) {
798  default:
799    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
800  case Mips::BPOSGE32_PSEUDO:
801    return emitBPOSGE32(MI, BB);
802  case Mips::SNZ_B_PSEUDO:
803    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
804  case Mips::SNZ_H_PSEUDO:
805    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
806  case Mips::SNZ_W_PSEUDO:
807    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
808  case Mips::SNZ_D_PSEUDO:
809    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
810  case Mips::SNZ_V_PSEUDO:
811    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
812  case Mips::SZ_B_PSEUDO:
813    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
814  case Mips::SZ_H_PSEUDO:
815    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
816  case Mips::SZ_W_PSEUDO:
817    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
818  case Mips::SZ_D_PSEUDO:
819    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
820  case Mips::SZ_V_PSEUDO:
821    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
822  }
823}
824
825bool MipsSETargetLowering::
826isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
827                                  unsigned NextStackOffset,
828                                  const MipsFunctionInfo& FI) const {
829  if (!EnableMipsTailCalls)
830    return false;
831
832  // Return false if either the callee or caller has a byval argument.
833  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
834    return false;
835
836  // Return true if the callee's argument area is no larger than the
837  // caller's.
838  return NextStackOffset <= FI.getIncomingArgSize();
839}
840
841void MipsSETargetLowering::
842getOpndList(SmallVectorImpl<SDValue> &Ops,
843            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
844            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
845            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
846  // T9 should contain the address of the callee function if
847  // -reloction-model=pic or it is an indirect call.
848  if (IsPICCall || !GlobalOrExternal) {
849    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
850    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
851  } else
852    Ops.push_back(Callee);
853
854  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
855                                  InternalLinkage, CLI, Callee, Chain);
856}
857
858SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
859  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
860
861  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
862    return MipsTargetLowering::lowerLOAD(Op, DAG);
863
864  // Replace a double precision load with two i32 loads and a buildpair64.
865  SDLoc DL(Op);
866  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
867  EVT PtrVT = Ptr.getValueType();
868
869  // i32 load from lower address.
870  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
871                           MachinePointerInfo(), Nd.isVolatile(),
872                           Nd.isNonTemporal(), Nd.isInvariant(),
873                           Nd.getAlignment());
874
875  // i32 load from higher address.
876  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
877  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
878                           MachinePointerInfo(), Nd.isVolatile(),
879                           Nd.isNonTemporal(), Nd.isInvariant(),
880                           std::min(Nd.getAlignment(), 4U));
881
882  if (!Subtarget->isLittle())
883    std::swap(Lo, Hi);
884
885  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
886  SDValue Ops[2] = {BP, Hi.getValue(1)};
887  return DAG.getMergeValues(Ops, 2, DL);
888}
889
890SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
891  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
892
893  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
894    return MipsTargetLowering::lowerSTORE(Op, DAG);
895
896  // Replace a double precision store with two extractelement64s and i32 stores.
897  SDLoc DL(Op);
898  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
899  EVT PtrVT = Ptr.getValueType();
900  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
901                           Val, DAG.getConstant(0, MVT::i32));
902  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
903                           Val, DAG.getConstant(1, MVT::i32));
904
905  if (!Subtarget->isLittle())
906    std::swap(Lo, Hi);
907
908  // i32 store to lower address.
909  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
910                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
911                       Nd.getTBAAInfo());
912
913  // i32 store to higher address.
914  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
915  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
916                      Nd.isVolatile(), Nd.isNonTemporal(),
917                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
918}
919
920SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
921                                          bool HasLo, bool HasHi,
922                                          SelectionDAG &DAG) const {
923  EVT Ty = Op.getOperand(0).getValueType();
924  SDLoc DL(Op);
925  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
926                             Op.getOperand(0), Op.getOperand(1));
927  SDValue Lo, Hi;
928
929  if (HasLo)
930    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
931                     DAG.getConstant(Mips::sub_lo, MVT::i32));
932  if (HasHi)
933    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
934                     DAG.getConstant(Mips::sub_hi, MVT::i32));
935
936  if (!HasLo || !HasHi)
937    return HasLo ? Lo : Hi;
938
939  SDValue Vals[] = { Lo, Hi };
940  return DAG.getMergeValues(Vals, 2, DL);
941}
942
943
944static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
945  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
946                             DAG.getConstant(0, MVT::i32));
947  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
948                             DAG.getConstant(1, MVT::i32));
949  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
950}
951
952static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
953  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
954                           DAG.getConstant(Mips::sub_lo, MVT::i32));
955  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
956                           DAG.getConstant(Mips::sub_hi, MVT::i32));
957  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
958}
959
960// This function expands mips intrinsic nodes which have 64-bit input operands
961// or output values.
962//
963// out64 = intrinsic-node in64
964// =>
965// lo = copy (extract-element (in64, 0))
966// hi = copy (extract-element (in64, 1))
967// mips-specific-node
968// v0 = copy lo
969// v1 = copy hi
970// out64 = merge-values (v0, v1)
971//
972static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
973  SDLoc DL(Op);
974  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
975  SmallVector<SDValue, 3> Ops;
976  unsigned OpNo = 0;
977
978  // See if Op has a chain input.
979  if (HasChainIn)
980    Ops.push_back(Op->getOperand(OpNo++));
981
982  // The next operand is the intrinsic opcode.
983  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
984
985  // See if the next operand has type i64.
986  SDValue Opnd = Op->getOperand(++OpNo), In64;
987
988  if (Opnd.getValueType() == MVT::i64)
989    In64 = initAccumulator(Opnd, DL, DAG);
990  else
991    Ops.push_back(Opnd);
992
993  // Push the remaining operands.
994  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
995    Ops.push_back(Op->getOperand(OpNo));
996
997  // Add In64 to the end of the list.
998  if (In64.getNode())
999    Ops.push_back(In64);
1000
1001  // Scan output.
1002  SmallVector<EVT, 2> ResTys;
1003
1004  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1005       I != E; ++I)
1006    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1007
1008  // Create node.
1009  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1010  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1011
1012  if (!HasChainIn)
1013    return Out;
1014
1015  assert(Val->getValueType(1) == MVT::Other);
1016  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1017  return DAG.getMergeValues(Vals, 2, DL);
1018}
1019
1020static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1021  SDLoc DL(Op);
1022  SDValue LHS = Op->getOperand(1);
1023  SDValue RHS = Op->getOperand(2);
1024  EVT ResTy = Op->getValueType(0);
1025
1026  SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
1027
1028  return Result;
1029}
1030
1031static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
1032                                     unsigned Opc, SDValue RHS) {
1033  SDValue LHS = Op->getOperand(1);
1034  EVT ResTy = Op->getValueType(0);
1035
1036  return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
1037}
1038
1039static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1040  SDLoc DL(Op);
1041  SDValue Value = Op->getOperand(1);
1042  EVT ResTy = Op->getValueType(0);
1043
1044  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1045
1046  return Result;
1047}
1048
1049// Lower an MSA copy intrinsic into the specified SelectionDAG node
1050static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1051  SDLoc DL(Op);
1052  SDValue Vec = Op->getOperand(1);
1053  SDValue Idx = Op->getOperand(2);
1054  EVT ResTy = Op->getValueType(0);
1055  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1056
1057  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1058                               DAG.getValueType(EltTy));
1059
1060  return Result;
1061}
1062
1063// Lower an MSA insert intrinsic into the specified SelectionDAG node
1064static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1065  SDLoc DL(Op);
1066  SDValue Op0 = Op->getOperand(1);
1067  SDValue Op1 = Op->getOperand(2);
1068  SDValue Op2 = Op->getOperand(3);
1069  EVT ResTy = Op->getValueType(0);
1070
1071  SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
1072
1073  return Result;
1074}
1075
1076static SDValue lowerMSASplatImm(SDValue Op, SDValue ImmOp, SelectionDAG &DAG) {
1077  EVT ResTy = Op->getValueType(0);
1078  EVT ViaVecTy = ResTy;
1079  SmallVector<SDValue, 16> Ops;
1080  SDValue ImmHiOp;
1081  SDLoc DL(Op);
1082
1083  if (ViaVecTy == MVT::v2i64) {
1084    ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1085                          DAG.getConstant(31, MVT::i32));
1086    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1087      Ops.push_back(ImmHiOp);
1088      Ops.push_back(ImmOp);
1089    }
1090    ViaVecTy = MVT::v4i32;
1091  } else {
1092    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1093      Ops.push_back(ImmOp);
1094  }
1095
1096  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1097                               Ops.size());
1098
1099  if (ResTy != ViaVecTy)
1100    Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1101
1102  return Result;
1103}
1104
1105static SDValue
1106lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1107  return lowerMSASplatImm(Op, Op->getOperand(ImmOp), DAG);
1108}
1109
1110static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1111  SDLoc DL(Op);
1112  SDValue Value = Op->getOperand(1);
1113  EVT ResTy = Op->getValueType(0);
1114
1115  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1116
1117  return Result;
1118}
1119
1120SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1121                                                      SelectionDAG &DAG) const {
1122  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1123  default:
1124    return SDValue();
1125  case Intrinsic::mips_shilo:
1126    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1127  case Intrinsic::mips_dpau_h_qbl:
1128    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1129  case Intrinsic::mips_dpau_h_qbr:
1130    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1131  case Intrinsic::mips_dpsu_h_qbl:
1132    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1133  case Intrinsic::mips_dpsu_h_qbr:
1134    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1135  case Intrinsic::mips_dpa_w_ph:
1136    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1137  case Intrinsic::mips_dps_w_ph:
1138    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1139  case Intrinsic::mips_dpax_w_ph:
1140    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1141  case Intrinsic::mips_dpsx_w_ph:
1142    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1143  case Intrinsic::mips_mulsa_w_ph:
1144    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1145  case Intrinsic::mips_mult:
1146    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1147  case Intrinsic::mips_multu:
1148    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1149  case Intrinsic::mips_madd:
1150    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1151  case Intrinsic::mips_maddu:
1152    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1153  case Intrinsic::mips_msub:
1154    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1155  case Intrinsic::mips_msubu:
1156    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1157  case Intrinsic::mips_addv_b:
1158  case Intrinsic::mips_addv_h:
1159  case Intrinsic::mips_addv_w:
1160  case Intrinsic::mips_addv_d:
1161    return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
1162  case Intrinsic::mips_addvi_b:
1163  case Intrinsic::mips_addvi_h:
1164  case Intrinsic::mips_addvi_w:
1165  case Intrinsic::mips_addvi_d:
1166    return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
1167                                 lowerMSASplatImm(Op, 2, DAG));
1168  case Intrinsic::mips_and_v:
1169    return lowerMSABinaryIntr(Op, DAG, ISD::AND);
1170  case Intrinsic::mips_andi_b:
1171    return lowerMSABinaryImmIntr(Op, DAG, ISD::AND,
1172                                 lowerMSASplatImm(Op, 2, DAG));
1173  case Intrinsic::mips_bnz_b:
1174  case Intrinsic::mips_bnz_h:
1175  case Intrinsic::mips_bnz_w:
1176  case Intrinsic::mips_bnz_d:
1177    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
1178  case Intrinsic::mips_bnz_v:
1179    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
1180  case Intrinsic::mips_bsel_v:
1181    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1182                       Op->getOperand(1), Op->getOperand(2),
1183                       Op->getOperand(3));
1184  case Intrinsic::mips_bseli_b:
1185    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1186                       Op->getOperand(1), Op->getOperand(2),
1187                       lowerMSASplatImm(Op, 3, DAG));
1188  case Intrinsic::mips_bz_b:
1189  case Intrinsic::mips_bz_h:
1190  case Intrinsic::mips_bz_w:
1191  case Intrinsic::mips_bz_d:
1192    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
1193  case Intrinsic::mips_bz_v:
1194    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
1195  case Intrinsic::mips_ceq_b:
1196  case Intrinsic::mips_ceq_h:
1197  case Intrinsic::mips_ceq_w:
1198  case Intrinsic::mips_ceq_d:
1199    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1200                        Op->getOperand(2), ISD::SETEQ);
1201  case Intrinsic::mips_ceqi_b:
1202  case Intrinsic::mips_ceqi_h:
1203  case Intrinsic::mips_ceqi_w:
1204  case Intrinsic::mips_ceqi_d:
1205    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1206                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1207  case Intrinsic::mips_cle_s_b:
1208  case Intrinsic::mips_cle_s_h:
1209  case Intrinsic::mips_cle_s_w:
1210  case Intrinsic::mips_cle_s_d:
1211    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1212                        Op->getOperand(2), ISD::SETLE);
1213  case Intrinsic::mips_clei_s_b:
1214  case Intrinsic::mips_clei_s_h:
1215  case Intrinsic::mips_clei_s_w:
1216  case Intrinsic::mips_clei_s_d:
1217    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1218                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1219  case Intrinsic::mips_cle_u_b:
1220  case Intrinsic::mips_cle_u_h:
1221  case Intrinsic::mips_cle_u_w:
1222  case Intrinsic::mips_cle_u_d:
1223    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1224                        Op->getOperand(2), ISD::SETULE);
1225  case Intrinsic::mips_clei_u_b:
1226  case Intrinsic::mips_clei_u_h:
1227  case Intrinsic::mips_clei_u_w:
1228  case Intrinsic::mips_clei_u_d:
1229    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1230                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1231  case Intrinsic::mips_clt_s_b:
1232  case Intrinsic::mips_clt_s_h:
1233  case Intrinsic::mips_clt_s_w:
1234  case Intrinsic::mips_clt_s_d:
1235    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1236                        Op->getOperand(2), ISD::SETLT);
1237  case Intrinsic::mips_clti_s_b:
1238  case Intrinsic::mips_clti_s_h:
1239  case Intrinsic::mips_clti_s_w:
1240  case Intrinsic::mips_clti_s_d:
1241    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1242                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1243  case Intrinsic::mips_clt_u_b:
1244  case Intrinsic::mips_clt_u_h:
1245  case Intrinsic::mips_clt_u_w:
1246  case Intrinsic::mips_clt_u_d:
1247    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1248                        Op->getOperand(2), ISD::SETULT);
1249  case Intrinsic::mips_clti_u_b:
1250  case Intrinsic::mips_clti_u_h:
1251  case Intrinsic::mips_clti_u_w:
1252  case Intrinsic::mips_clti_u_d:
1253    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1254                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1255  case Intrinsic::mips_copy_s_b:
1256  case Intrinsic::mips_copy_s_h:
1257  case Intrinsic::mips_copy_s_w:
1258    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1259  case Intrinsic::mips_copy_u_b:
1260  case Intrinsic::mips_copy_u_h:
1261  case Intrinsic::mips_copy_u_w:
1262    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1263  case Intrinsic::mips_div_s_b:
1264  case Intrinsic::mips_div_s_h:
1265  case Intrinsic::mips_div_s_w:
1266  case Intrinsic::mips_div_s_d:
1267    return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
1268  case Intrinsic::mips_div_u_b:
1269  case Intrinsic::mips_div_u_h:
1270  case Intrinsic::mips_div_u_w:
1271  case Intrinsic::mips_div_u_d:
1272    return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
1273  case Intrinsic::mips_fadd_w:
1274  case Intrinsic::mips_fadd_d:
1275    return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
1276  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1277  case Intrinsic::mips_fceq_w:
1278  case Intrinsic::mips_fceq_d:
1279    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1280                        Op->getOperand(2), ISD::SETOEQ);
1281  case Intrinsic::mips_fcle_w:
1282  case Intrinsic::mips_fcle_d:
1283    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1284                        Op->getOperand(2), ISD::SETOLE);
1285  case Intrinsic::mips_fclt_w:
1286  case Intrinsic::mips_fclt_d:
1287    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1288                        Op->getOperand(2), ISD::SETOLT);
1289  case Intrinsic::mips_fcne_w:
1290  case Intrinsic::mips_fcne_d:
1291    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1292                        Op->getOperand(2), ISD::SETONE);
1293  case Intrinsic::mips_fcor_w:
1294  case Intrinsic::mips_fcor_d:
1295    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1296                        Op->getOperand(2), ISD::SETO);
1297  case Intrinsic::mips_fcueq_w:
1298  case Intrinsic::mips_fcueq_d:
1299    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1300                        Op->getOperand(2), ISD::SETUEQ);
1301  case Intrinsic::mips_fcule_w:
1302  case Intrinsic::mips_fcule_d:
1303    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1304                        Op->getOperand(2), ISD::SETULE);
1305  case Intrinsic::mips_fcult_w:
1306  case Intrinsic::mips_fcult_d:
1307    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1308                        Op->getOperand(2), ISD::SETULT);
1309  case Intrinsic::mips_fcun_w:
1310  case Intrinsic::mips_fcun_d:
1311    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1312                        Op->getOperand(2), ISD::SETUO);
1313  case Intrinsic::mips_fcune_w:
1314  case Intrinsic::mips_fcune_d:
1315    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1316                        Op->getOperand(2), ISD::SETUNE);
1317  case Intrinsic::mips_fdiv_w:
1318  case Intrinsic::mips_fdiv_d:
1319    return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
1320  case Intrinsic::mips_fill_b:
1321  case Intrinsic::mips_fill_h:
1322  case Intrinsic::mips_fill_w: {
1323    SmallVector<SDValue, 16> Ops;
1324    EVT ResTy = Op->getValueType(0);
1325
1326    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1327      Ops.push_back(Op->getOperand(1));
1328
1329    return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), ResTy, &Ops[0],
1330                       Ops.size());
1331  }
1332  case Intrinsic::mips_flog2_w:
1333  case Intrinsic::mips_flog2_d:
1334    return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
1335  case Intrinsic::mips_fmul_w:
1336  case Intrinsic::mips_fmul_d:
1337    return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
1338  case Intrinsic::mips_frint_w:
1339  case Intrinsic::mips_frint_d:
1340    return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
1341  case Intrinsic::mips_fsqrt_w:
1342  case Intrinsic::mips_fsqrt_d:
1343    return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
1344  case Intrinsic::mips_fsub_w:
1345  case Intrinsic::mips_fsub_d:
1346    return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
1347  case Intrinsic::mips_insert_b:
1348  case Intrinsic::mips_insert_h:
1349  case Intrinsic::mips_insert_w:
1350    return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
1351  case Intrinsic::mips_ldi_b:
1352  case Intrinsic::mips_ldi_h:
1353  case Intrinsic::mips_ldi_w:
1354  case Intrinsic::mips_ldi_d:
1355    return lowerMSASplatImm(Op, 1, DAG);
1356  case Intrinsic::mips_max_s_b:
1357  case Intrinsic::mips_max_s_h:
1358  case Intrinsic::mips_max_s_w:
1359  case Intrinsic::mips_max_s_d:
1360    return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMAX);
1361  case Intrinsic::mips_max_u_b:
1362  case Intrinsic::mips_max_u_h:
1363  case Intrinsic::mips_max_u_w:
1364  case Intrinsic::mips_max_u_d:
1365    return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMAX);
1366  case Intrinsic::mips_maxi_s_b:
1367  case Intrinsic::mips_maxi_s_h:
1368  case Intrinsic::mips_maxi_s_w:
1369  case Intrinsic::mips_maxi_s_d:
1370    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMAX,
1371                                 lowerMSASplatImm(Op, 2, DAG));
1372  case Intrinsic::mips_maxi_u_b:
1373  case Intrinsic::mips_maxi_u_h:
1374  case Intrinsic::mips_maxi_u_w:
1375  case Intrinsic::mips_maxi_u_d:
1376    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMAX,
1377                                 lowerMSASplatImm(Op, 2, DAG));
1378  case Intrinsic::mips_min_s_b:
1379  case Intrinsic::mips_min_s_h:
1380  case Intrinsic::mips_min_s_w:
1381  case Intrinsic::mips_min_s_d:
1382    return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMIN);
1383  case Intrinsic::mips_min_u_b:
1384  case Intrinsic::mips_min_u_h:
1385  case Intrinsic::mips_min_u_w:
1386  case Intrinsic::mips_min_u_d:
1387    return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMIN);
1388  case Intrinsic::mips_mini_s_b:
1389  case Intrinsic::mips_mini_s_h:
1390  case Intrinsic::mips_mini_s_w:
1391  case Intrinsic::mips_mini_s_d:
1392    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMIN,
1393                                 lowerMSASplatImm(Op, 2, DAG));
1394  case Intrinsic::mips_mini_u_b:
1395  case Intrinsic::mips_mini_u_h:
1396  case Intrinsic::mips_mini_u_w:
1397  case Intrinsic::mips_mini_u_d:
1398    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMIN,
1399                                 lowerMSASplatImm(Op, 2, DAG));
1400  case Intrinsic::mips_mulv_b:
1401  case Intrinsic::mips_mulv_h:
1402  case Intrinsic::mips_mulv_w:
1403  case Intrinsic::mips_mulv_d:
1404    return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
1405  case Intrinsic::mips_nlzc_b:
1406  case Intrinsic::mips_nlzc_h:
1407  case Intrinsic::mips_nlzc_w:
1408  case Intrinsic::mips_nlzc_d:
1409    return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
1410  case Intrinsic::mips_nor_v: {
1411    SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
1412    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1413  }
1414  case Intrinsic::mips_nori_b: {
1415    SDValue Res = lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
1416                                        lowerMSASplatImm(Op, 2, DAG));
1417    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1418  }
1419  case Intrinsic::mips_or_v:
1420    return lowerMSABinaryIntr(Op, DAG, ISD::OR);
1421  case Intrinsic::mips_ori_b:
1422    return lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
1423                                 lowerMSASplatImm(Op, 2, DAG));
1424  case Intrinsic::mips_pcnt_b:
1425  case Intrinsic::mips_pcnt_h:
1426  case Intrinsic::mips_pcnt_w:
1427  case Intrinsic::mips_pcnt_d:
1428    return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
1429  case Intrinsic::mips_sll_b:
1430  case Intrinsic::mips_sll_h:
1431  case Intrinsic::mips_sll_w:
1432  case Intrinsic::mips_sll_d:
1433    return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
1434  case Intrinsic::mips_slli_b:
1435  case Intrinsic::mips_slli_h:
1436  case Intrinsic::mips_slli_w:
1437  case Intrinsic::mips_slli_d:
1438    return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
1439                                 lowerMSASplatImm(Op, 2, DAG));
1440  case Intrinsic::mips_sra_b:
1441  case Intrinsic::mips_sra_h:
1442  case Intrinsic::mips_sra_w:
1443  case Intrinsic::mips_sra_d:
1444    return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
1445  case Intrinsic::mips_srai_b:
1446  case Intrinsic::mips_srai_h:
1447  case Intrinsic::mips_srai_w:
1448  case Intrinsic::mips_srai_d:
1449    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
1450                                 lowerMSASplatImm(Op, 2, DAG));
1451  case Intrinsic::mips_srl_b:
1452  case Intrinsic::mips_srl_h:
1453  case Intrinsic::mips_srl_w:
1454  case Intrinsic::mips_srl_d:
1455    return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
1456  case Intrinsic::mips_srli_b:
1457  case Intrinsic::mips_srli_h:
1458  case Intrinsic::mips_srli_w:
1459  case Intrinsic::mips_srli_d:
1460    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
1461                                 lowerMSASplatImm(Op, 2, DAG));
1462  case Intrinsic::mips_subv_b:
1463  case Intrinsic::mips_subv_h:
1464  case Intrinsic::mips_subv_w:
1465  case Intrinsic::mips_subv_d:
1466    return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
1467  case Intrinsic::mips_subvi_b:
1468  case Intrinsic::mips_subvi_h:
1469  case Intrinsic::mips_subvi_w:
1470  case Intrinsic::mips_subvi_d:
1471    return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
1472                                 lowerMSASplatImm(Op, 2, DAG));
1473  case Intrinsic::mips_xor_v:
1474    return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
1475  case Intrinsic::mips_xori_b:
1476    return lowerMSABinaryImmIntr(Op, DAG, ISD::XOR,
1477                                 lowerMSASplatImm(Op, 2, DAG));
1478  }
1479}
1480
1481static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1482  SDLoc DL(Op);
1483  SDValue ChainIn = Op->getOperand(0);
1484  SDValue Address = Op->getOperand(2);
1485  SDValue Offset  = Op->getOperand(3);
1486  EVT ResTy = Op->getValueType(0);
1487  EVT PtrTy = Address->getValueType(0);
1488
1489  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1490
1491  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1492                     false, false, 16);
1493}
1494
1495SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1496                                                     SelectionDAG &DAG) const {
1497  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1498  switch (Intr) {
1499  default:
1500    return SDValue();
1501  case Intrinsic::mips_extp:
1502    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1503  case Intrinsic::mips_extpdp:
1504    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1505  case Intrinsic::mips_extr_w:
1506    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1507  case Intrinsic::mips_extr_r_w:
1508    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1509  case Intrinsic::mips_extr_rs_w:
1510    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1511  case Intrinsic::mips_extr_s_h:
1512    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1513  case Intrinsic::mips_mthlip:
1514    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1515  case Intrinsic::mips_mulsaq_s_w_ph:
1516    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1517  case Intrinsic::mips_maq_s_w_phl:
1518    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1519  case Intrinsic::mips_maq_s_w_phr:
1520    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1521  case Intrinsic::mips_maq_sa_w_phl:
1522    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1523  case Intrinsic::mips_maq_sa_w_phr:
1524    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1525  case Intrinsic::mips_dpaq_s_w_ph:
1526    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1527  case Intrinsic::mips_dpsq_s_w_ph:
1528    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1529  case Intrinsic::mips_dpaq_sa_l_w:
1530    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1531  case Intrinsic::mips_dpsq_sa_l_w:
1532    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1533  case Intrinsic::mips_dpaqx_s_w_ph:
1534    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1535  case Intrinsic::mips_dpaqx_sa_w_ph:
1536    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1537  case Intrinsic::mips_dpsqx_s_w_ph:
1538    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1539  case Intrinsic::mips_dpsqx_sa_w_ph:
1540    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1541  case Intrinsic::mips_ld_b:
1542  case Intrinsic::mips_ld_h:
1543  case Intrinsic::mips_ld_w:
1544  case Intrinsic::mips_ld_d:
1545  case Intrinsic::mips_ldx_b:
1546  case Intrinsic::mips_ldx_h:
1547  case Intrinsic::mips_ldx_w:
1548  case Intrinsic::mips_ldx_d:
1549   return lowerMSALoadIntr(Op, DAG, Intr);
1550  }
1551}
1552
1553static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1554  SDLoc DL(Op);
1555  SDValue ChainIn = Op->getOperand(0);
1556  SDValue Value   = Op->getOperand(2);
1557  SDValue Address = Op->getOperand(3);
1558  SDValue Offset  = Op->getOperand(4);
1559  EVT PtrTy = Address->getValueType(0);
1560
1561  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1562
1563  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1564                      false, 16);
1565}
1566
1567SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1568                                                  SelectionDAG &DAG) const {
1569  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1570  switch (Intr) {
1571  default:
1572    return SDValue();
1573  case Intrinsic::mips_st_b:
1574  case Intrinsic::mips_st_h:
1575  case Intrinsic::mips_st_w:
1576  case Intrinsic::mips_st_d:
1577  case Intrinsic::mips_stx_b:
1578  case Intrinsic::mips_stx_h:
1579  case Intrinsic::mips_stx_w:
1580  case Intrinsic::mips_stx_d:
1581    return lowerMSAStoreIntr(Op, DAG, Intr);
1582  }
1583}
1584
1585/// \brief Check if the given BuildVectorSDNode is a splat.
1586/// This method currently relies on DAG nodes being reused when equivalent,
1587/// so it's possible for this to return false even when isConstantSplat returns
1588/// true.
1589static bool isSplatVector(const BuildVectorSDNode *N) {
1590  unsigned int nOps = N->getNumOperands();
1591  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1592
1593  SDValue Operand0 = N->getOperand(0);
1594
1595  for (unsigned int i = 1; i < nOps; ++i) {
1596    if (N->getOperand(i) != Operand0)
1597      return false;
1598  }
1599
1600  return true;
1601}
1602
1603// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1604//
1605// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1606// choose to sign-extend but we could have equally chosen zero-extend. The
1607// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1608// result into this node later (possibly changing it to a zero-extend in the
1609// process).
1610SDValue MipsSETargetLowering::
1611lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1612  SDLoc DL(Op);
1613  EVT ResTy = Op->getValueType(0);
1614  SDValue Op0 = Op->getOperand(0);
1615  SDValue Op1 = Op->getOperand(1);
1616  EVT EltTy = Op0->getValueType(0).getVectorElementType();
1617  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1618                     DAG.getValueType(EltTy));
1619}
1620
1621static bool isConstantOrUndef(const SDValue Op) {
1622  if (Op->getOpcode() == ISD::UNDEF)
1623    return true;
1624  if (dyn_cast<ConstantSDNode>(Op))
1625    return true;
1626  if (dyn_cast<ConstantFPSDNode>(Op))
1627    return true;
1628  return false;
1629}
1630
1631static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1632  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1633    if (isConstantOrUndef(Op->getOperand(i)))
1634      return true;
1635  return false;
1636}
1637
1638// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1639// backend.
1640//
1641// Lowers according to the following rules:
1642// - Constant splats are legal as-is as long as the SplatBitSize is a power of
1643//   2 less than or equal to 64 and the value fits into a signed 10-bit
1644//   immediate
1645// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1646//   is a power of 2 less than or equal to 64 and the value does not fit into a
1647//   signed 10-bit immediate
1648// - Non-constant splats are legal as-is.
1649// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1650// - All others are illegal and must be expanded.
1651SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1652                                                SelectionDAG &DAG) const {
1653  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1654  EVT ResTy = Op->getValueType(0);
1655  SDLoc DL(Op);
1656  APInt SplatValue, SplatUndef;
1657  unsigned SplatBitSize;
1658  bool HasAnyUndefs;
1659
1660  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1661    return SDValue();
1662
1663  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1664                            HasAnyUndefs, 8,
1665                            !Subtarget->isLittle()) && SplatBitSize <= 64) {
1666    // We can only cope with 8, 16, 32, or 64-bit elements
1667    if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1668        SplatBitSize != 64)
1669      return SDValue();
1670
1671    // If the value fits into a simm10 then we can use ldi.[bhwd]
1672    if (SplatValue.isSignedIntN(10))
1673      return Op;
1674
1675    EVT ViaVecTy;
1676
1677    switch (SplatBitSize) {
1678    default:
1679      return SDValue();
1680    case 8:
1681      ViaVecTy = MVT::v16i8;
1682      break;
1683    case 16:
1684      ViaVecTy = MVT::v8i16;
1685      break;
1686    case 32:
1687      ViaVecTy = MVT::v4i32;
1688      break;
1689    case 64:
1690      // There's no fill.d to fall back on for 64-bit values
1691      return SDValue();
1692    }
1693
1694    SmallVector<SDValue, 16> Ops;
1695    SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1696
1697    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1698      Ops.push_back(Constant);
1699
1700    SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1701                                 &Ops[0], Ops.size());
1702
1703    if (ViaVecTy != ResTy)
1704      Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1705
1706    return Result;
1707  } else if (isSplatVector(Node))
1708    return Op;
1709  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1710    // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1711    // The resulting code is the same length as the expansion, but it doesn't
1712    // use memory operations
1713    EVT ResTy = Node->getValueType(0);
1714
1715    assert(ResTy.isVector());
1716
1717    unsigned NumElts = ResTy.getVectorNumElements();
1718    SDValue Vector = DAG.getUNDEF(ResTy);
1719    for (unsigned i = 0; i < NumElts; ++i) {
1720      Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1721                           Node->getOperand(i),
1722                           DAG.getConstant(i, MVT::i32));
1723    }
1724    return Vector;
1725  }
1726
1727  return SDValue();
1728}
1729
1730MachineBasicBlock * MipsSETargetLowering::
1731emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1732  // $bb:
1733  //  bposge32_pseudo $vr0
1734  //  =>
1735  // $bb:
1736  //  bposge32 $tbb
1737  // $fbb:
1738  //  li $vr2, 0
1739  //  b $sink
1740  // $tbb:
1741  //  li $vr1, 1
1742  // $sink:
1743  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1744
1745  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1746  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1747  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1748  DebugLoc DL = MI->getDebugLoc();
1749  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1750  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1751  MachineFunction *F = BB->getParent();
1752  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1753  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1754  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1755  F->insert(It, FBB);
1756  F->insert(It, TBB);
1757  F->insert(It, Sink);
1758
1759  // Transfer the remainder of BB and its successor edges to Sink.
1760  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1761               BB->end());
1762  Sink->transferSuccessorsAndUpdatePHIs(BB);
1763
1764  // Add successors.
1765  BB->addSuccessor(FBB);
1766  BB->addSuccessor(TBB);
1767  FBB->addSuccessor(Sink);
1768  TBB->addSuccessor(Sink);
1769
1770  // Insert the real bposge32 instruction to $BB.
1771  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1772
1773  // Fill $FBB.
1774  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1775  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1776    .addReg(Mips::ZERO).addImm(0);
1777  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1778
1779  // Fill $TBB.
1780  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1781  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1782    .addReg(Mips::ZERO).addImm(1);
1783
1784  // Insert phi function to $Sink.
1785  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1786          MI->getOperand(0).getReg())
1787    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1788
1789  MI->eraseFromParent();   // The pseudo instruction is gone now.
1790  return Sink;
1791}
1792
1793MachineBasicBlock * MipsSETargetLowering::
1794emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1795                     unsigned BranchOp) const{
1796  // $bb:
1797  //  vany_nonzero $rd, $ws
1798  //  =>
1799  // $bb:
1800  //  bnz.b $ws, $tbb
1801  //  b $fbb
1802  // $fbb:
1803  //  li $rd1, 0
1804  //  b $sink
1805  // $tbb:
1806  //  li $rd2, 1
1807  // $sink:
1808  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1809
1810  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1811  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1812  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1813  DebugLoc DL = MI->getDebugLoc();
1814  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1815  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1816  MachineFunction *F = BB->getParent();
1817  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1818  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1819  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1820  F->insert(It, FBB);
1821  F->insert(It, TBB);
1822  F->insert(It, Sink);
1823
1824  // Transfer the remainder of BB and its successor edges to Sink.
1825  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1826               BB->end());
1827  Sink->transferSuccessorsAndUpdatePHIs(BB);
1828
1829  // Add successors.
1830  BB->addSuccessor(FBB);
1831  BB->addSuccessor(TBB);
1832  FBB->addSuccessor(Sink);
1833  TBB->addSuccessor(Sink);
1834
1835  // Insert the real bnz.b instruction to $BB.
1836  BuildMI(BB, DL, TII->get(BranchOp))
1837    .addReg(MI->getOperand(1).getReg())
1838    .addMBB(TBB);
1839
1840  // Fill $FBB.
1841  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1842  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1843    .addReg(Mips::ZERO).addImm(0);
1844  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1845
1846  // Fill $TBB.
1847  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1848  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1849    .addReg(Mips::ZERO).addImm(1);
1850
1851  // Insert phi function to $Sink.
1852  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1853          MI->getOperand(0).getReg())
1854    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1855
1856  MI->eraseFromParent();   // The pseudo instruction is gone now.
1857  return Sink;
1858}
1859