MipsSEISelLowering.cpp revision aed9334acfdd8fa7548dc540fe865a5a641cb208
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips32/64. 11// 12//===----------------------------------------------------------------------===// 13#define DEBUG_TYPE "mips-isel" 14#include "MipsSEISelLowering.h" 15#include "MipsRegisterInfo.h" 16#include "MipsTargetMachine.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19#include "llvm/IR/Intrinsics.h" 20#include "llvm/Support/CommandLine.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Target/TargetInstrInfo.h" 23 24using namespace llvm; 25 26static cl::opt<bool> 27EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 28 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 29 30static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 31 cl::desc("Expand double precision loads and " 32 "stores to their single precision " 33 "counterparts")); 34 35MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) 36 : MipsTargetLowering(TM) { 37 // Set up the register classes 38 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 39 40 if (HasMips64) 41 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 42 43 if (Subtarget->hasDSP() || Subtarget->hasMSA()) { 44 // Expand all truncating stores and extending loads. 45 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 46 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 47 48 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { 49 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) 50 setTruncStoreAction((MVT::SimpleValueType)VT0, 51 (MVT::SimpleValueType)VT1, Expand); 52 53 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 54 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 55 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); 56 } 57 } 58 59 if (Subtarget->hasDSP()) { 60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 61 62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 64 65 // Expand all builtin opcodes. 66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 67 setOperationAction(Opc, VecTys[i], Expand); 68 69 setOperationAction(ISD::ADD, VecTys[i], Legal); 70 setOperationAction(ISD::SUB, VecTys[i], Legal); 71 setOperationAction(ISD::LOAD, VecTys[i], Legal); 72 setOperationAction(ISD::STORE, VecTys[i], Legal); 73 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 74 } 75 76 setTargetDAGCombine(ISD::SHL); 77 setTargetDAGCombine(ISD::SRA); 78 setTargetDAGCombine(ISD::SRL); 79 setTargetDAGCombine(ISD::SETCC); 80 setTargetDAGCombine(ISD::VSELECT); 81 } 82 83 if (Subtarget->hasDSPR2()) 84 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 85 86 if (Subtarget->hasMSA()) { 87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 94 95 setTargetDAGCombine(ISD::AND); 96 setTargetDAGCombine(ISD::SRA); 97 setTargetDAGCombine(ISD::VSELECT); 98 setTargetDAGCombine(ISD::XOR); 99 } 100 101 if (!Subtarget->mipsSEUsesSoftFloat()) { 102 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 103 104 // When dealing with single precision only, use libcalls 105 if (!Subtarget->isSingleFloat()) { 106 if (Subtarget->isFP64bit()) 107 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 108 else 109 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 110 } 111 } 112 113 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 115 setOperationAction(ISD::MULHS, MVT::i32, Custom); 116 setOperationAction(ISD::MULHU, MVT::i32, Custom); 117 118 if (HasMips64) { 119 setOperationAction(ISD::MULHS, MVT::i64, Custom); 120 setOperationAction(ISD::MULHU, MVT::i64, Custom); 121 setOperationAction(ISD::MUL, MVT::i64, Custom); 122 } 123 124 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 125 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 126 127 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 128 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 131 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 132 setOperationAction(ISD::LOAD, MVT::i32, Custom); 133 setOperationAction(ISD::STORE, MVT::i32, Custom); 134 135 setTargetDAGCombine(ISD::ADDE); 136 setTargetDAGCombine(ISD::SUBE); 137 setTargetDAGCombine(ISD::MUL); 138 139 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 140 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 141 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 142 143 if (NoDPLoadStore) { 144 setOperationAction(ISD::LOAD, MVT::f64, Custom); 145 setOperationAction(ISD::STORE, MVT::f64, Custom); 146 } 147 148 computeRegisterProperties(); 149} 150 151const MipsTargetLowering * 152llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { 153 return new MipsSETargetLowering(TM); 154} 155 156// Enable MSA support for the given integer type and Register class. 157void MipsSETargetLowering:: 158addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 159 addRegisterClass(Ty, RC); 160 161 // Expand all builtin opcodes. 162 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 163 setOperationAction(Opc, Ty, Expand); 164 165 setOperationAction(ISD::BITCAST, Ty, Legal); 166 setOperationAction(ISD::LOAD, Ty, Legal); 167 setOperationAction(ISD::STORE, Ty, Legal); 168 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 169 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 170 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 171 172 setOperationAction(ISD::ADD, Ty, Legal); 173 setOperationAction(ISD::AND, Ty, Legal); 174 setOperationAction(ISD::CTLZ, Ty, Legal); 175 setOperationAction(ISD::CTPOP, Ty, Legal); 176 setOperationAction(ISD::MUL, Ty, Legal); 177 setOperationAction(ISD::OR, Ty, Legal); 178 setOperationAction(ISD::SDIV, Ty, Legal); 179 setOperationAction(ISD::SREM, Ty, Legal); 180 setOperationAction(ISD::SHL, Ty, Legal); 181 setOperationAction(ISD::SRA, Ty, Legal); 182 setOperationAction(ISD::SRL, Ty, Legal); 183 setOperationAction(ISD::SUB, Ty, Legal); 184 setOperationAction(ISD::UDIV, Ty, Legal); 185 setOperationAction(ISD::UREM, Ty, Legal); 186 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 187 setOperationAction(ISD::VSELECT, Ty, Legal); 188 setOperationAction(ISD::XOR, Ty, Legal); 189 190 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 191 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); 192 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); 193 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 194 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 195 } 196 197 setOperationAction(ISD::SETCC, Ty, Legal); 198 setCondCodeAction(ISD::SETNE, Ty, Expand); 199 setCondCodeAction(ISD::SETGE, Ty, Expand); 200 setCondCodeAction(ISD::SETGT, Ty, Expand); 201 setCondCodeAction(ISD::SETUGE, Ty, Expand); 202 setCondCodeAction(ISD::SETUGT, Ty, Expand); 203} 204 205// Enable MSA support for the given floating-point type and Register class. 206void MipsSETargetLowering:: 207addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 208 addRegisterClass(Ty, RC); 209 210 // Expand all builtin opcodes. 211 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 212 setOperationAction(Opc, Ty, Expand); 213 214 setOperationAction(ISD::LOAD, Ty, Legal); 215 setOperationAction(ISD::STORE, Ty, Legal); 216 setOperationAction(ISD::BITCAST, Ty, Legal); 217 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 218 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 219 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 220 221 if (Ty != MVT::v8f16) { 222 setOperationAction(ISD::FABS, Ty, Legal); 223 setOperationAction(ISD::FADD, Ty, Legal); 224 setOperationAction(ISD::FDIV, Ty, Legal); 225 setOperationAction(ISD::FEXP2, Ty, Legal); 226 setOperationAction(ISD::FLOG2, Ty, Legal); 227 setOperationAction(ISD::FMA, Ty, Legal); 228 setOperationAction(ISD::FMUL, Ty, Legal); 229 setOperationAction(ISD::FRINT, Ty, Legal); 230 setOperationAction(ISD::FSQRT, Ty, Legal); 231 setOperationAction(ISD::FSUB, Ty, Legal); 232 setOperationAction(ISD::VSELECT, Ty, Legal); 233 234 setOperationAction(ISD::SETCC, Ty, Legal); 235 setCondCodeAction(ISD::SETOGE, Ty, Expand); 236 setCondCodeAction(ISD::SETOGT, Ty, Expand); 237 setCondCodeAction(ISD::SETUGE, Ty, Expand); 238 setCondCodeAction(ISD::SETUGT, Ty, Expand); 239 setCondCodeAction(ISD::SETGE, Ty, Expand); 240 setCondCodeAction(ISD::SETGT, Ty, Expand); 241 } 242} 243 244bool 245MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 246 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 247 248 switch (SVT) { 249 case MVT::i64: 250 case MVT::i32: 251 if (Fast) 252 *Fast = true; 253 return true; 254 default: 255 return false; 256 } 257} 258 259SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 260 SelectionDAG &DAG) const { 261 switch(Op.getOpcode()) { 262 case ISD::LOAD: return lowerLOAD(Op, DAG); 263 case ISD::STORE: return lowerSTORE(Op, DAG); 264 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 265 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 266 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 267 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 268 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 269 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 270 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 271 DAG); 272 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 273 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 274 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 275 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 276 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 277 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 278 } 279 280 return MipsTargetLowering::LowerOperation(Op, DAG); 281} 282 283// selectMADD - 284// Transforms a subgraph in CurDAG if the following pattern is found: 285// (addc multLo, Lo0), (adde multHi, Hi0), 286// where, 287// multHi/Lo: product of multiplication 288// Lo0: initial value of Lo register 289// Hi0: initial value of Hi register 290// Return true if pattern matching was successful. 291static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 292 // ADDENode's second operand must be a flag output of an ADDC node in order 293 // for the matching to be successful. 294 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 295 296 if (ADDCNode->getOpcode() != ISD::ADDC) 297 return false; 298 299 SDValue MultHi = ADDENode->getOperand(0); 300 SDValue MultLo = ADDCNode->getOperand(0); 301 SDNode *MultNode = MultHi.getNode(); 302 unsigned MultOpc = MultHi.getOpcode(); 303 304 // MultHi and MultLo must be generated by the same node, 305 if (MultLo.getNode() != MultNode) 306 return false; 307 308 // and it must be a multiplication. 309 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 310 return false; 311 312 // MultLo amd MultHi must be the first and second output of MultNode 313 // respectively. 314 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 315 return false; 316 317 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 318 // of the values of MultNode, in which case MultNode will be removed in later 319 // phases. 320 // If there exist users other than ADDENode or ADDCNode, this function returns 321 // here, which will result in MultNode being mapped to a single MULT 322 // instruction node rather than a pair of MULT and MADD instructions being 323 // produced. 324 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 325 return false; 326 327 SDLoc DL(ADDENode); 328 329 // Initialize accumulator. 330 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 331 ADDCNode->getOperand(1), 332 ADDENode->getOperand(1)); 333 334 // create MipsMAdd(u) node 335 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 336 337 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 338 MultNode->getOperand(0),// Factor 0 339 MultNode->getOperand(1),// Factor 1 340 ACCIn); 341 342 // replace uses of adde and addc here 343 if (!SDValue(ADDCNode, 0).use_empty()) { 344 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 345 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 346 } 347 if (!SDValue(ADDENode, 0).use_empty()) { 348 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 349 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 350 } 351 352 return true; 353} 354 355// selectMSUB - 356// Transforms a subgraph in CurDAG if the following pattern is found: 357// (addc Lo0, multLo), (sube Hi0, multHi), 358// where, 359// multHi/Lo: product of multiplication 360// Lo0: initial value of Lo register 361// Hi0: initial value of Hi register 362// Return true if pattern matching was successful. 363static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 364 // SUBENode's second operand must be a flag output of an SUBC node in order 365 // for the matching to be successful. 366 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 367 368 if (SUBCNode->getOpcode() != ISD::SUBC) 369 return false; 370 371 SDValue MultHi = SUBENode->getOperand(1); 372 SDValue MultLo = SUBCNode->getOperand(1); 373 SDNode *MultNode = MultHi.getNode(); 374 unsigned MultOpc = MultHi.getOpcode(); 375 376 // MultHi and MultLo must be generated by the same node, 377 if (MultLo.getNode() != MultNode) 378 return false; 379 380 // and it must be a multiplication. 381 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 382 return false; 383 384 // MultLo amd MultHi must be the first and second output of MultNode 385 // respectively. 386 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 387 return false; 388 389 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 390 // of the values of MultNode, in which case MultNode will be removed in later 391 // phases. 392 // If there exist users other than SUBENode or SUBCNode, this function returns 393 // here, which will result in MultNode being mapped to a single MULT 394 // instruction node rather than a pair of MULT and MSUB instructions being 395 // produced. 396 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 397 return false; 398 399 SDLoc DL(SUBENode); 400 401 // Initialize accumulator. 402 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 403 SUBCNode->getOperand(0), 404 SUBENode->getOperand(0)); 405 406 // create MipsSub(u) node 407 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 408 409 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 410 MultNode->getOperand(0),// Factor 0 411 MultNode->getOperand(1),// Factor 1 412 ACCIn); 413 414 // replace uses of sube and subc here 415 if (!SDValue(SUBCNode, 0).use_empty()) { 416 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); 417 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 418 } 419 if (!SDValue(SUBENode, 0).use_empty()) { 420 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); 421 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 422 } 423 424 return true; 425} 426 427static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 428 TargetLowering::DAGCombinerInfo &DCI, 429 const MipsSubtarget *Subtarget) { 430 if (DCI.isBeforeLegalize()) 431 return SDValue(); 432 433 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 434 selectMADD(N, &DAG)) 435 return SDValue(N, 0); 436 437 return SDValue(); 438} 439 440// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 441// 442// Performs the following transformations: 443// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 444// sign/zero-extension is completely overwritten by the new one performed by 445// the ISD::AND. 446// - Removes redundant zero extensions performed by an ISD::AND. 447static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 448 TargetLowering::DAGCombinerInfo &DCI, 449 const MipsSubtarget *Subtarget) { 450 if (!Subtarget->hasMSA()) 451 return SDValue(); 452 453 SDValue Op0 = N->getOperand(0); 454 SDValue Op1 = N->getOperand(1); 455 unsigned Op0Opcode = Op0->getOpcode(); 456 457 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 458 // where $d + 1 == 2^n and n == 32 459 // or $d + 1 == 2^n and n <= 32 and ZExt 460 // -> (MipsVExtractZExt $a, $b, $c) 461 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 462 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 463 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 464 465 if (!Mask) 466 return SDValue(); 467 468 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 469 470 if (Log2IfPositive <= 0) 471 return SDValue(); // Mask+1 is not a power of 2 472 473 SDValue Op0Op2 = Op0->getOperand(2); 474 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 475 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 476 unsigned Log2 = Log2IfPositive; 477 478 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 479 Log2 == ExtendTySize) { 480 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 481 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 482 Op0->getVTList(), Ops, Op0->getNumOperands()); 483 return Op0; 484 } 485 } 486 487 return SDValue(); 488} 489 490static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 491 TargetLowering::DAGCombinerInfo &DCI, 492 const MipsSubtarget *Subtarget) { 493 if (DCI.isBeforeLegalize()) 494 return SDValue(); 495 496 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 497 selectMSUB(N, &DAG)) 498 return SDValue(N, 0); 499 500 return SDValue(); 501} 502 503static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 504 EVT ShiftTy, SelectionDAG &DAG) { 505 // Clear the upper (64 - VT.sizeInBits) bits. 506 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 507 508 // Return 0. 509 if (C == 0) 510 return DAG.getConstant(0, VT); 511 512 // Return x. 513 if (C == 1) 514 return X; 515 516 // If c is power of 2, return (shl x, log2(c)). 517 if (isPowerOf2_64(C)) 518 return DAG.getNode(ISD::SHL, DL, VT, X, 519 DAG.getConstant(Log2_64(C), ShiftTy)); 520 521 unsigned Log2Ceil = Log2_64_Ceil(C); 522 uint64_t Floor = 1LL << Log2_64(C); 523 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 524 525 // If |c - floor_c| <= |c - ceil_c|, 526 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 527 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 528 if (C - Floor <= Ceil - C) { 529 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 530 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 531 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 532 } 533 534 // If |c - floor_c| > |c - ceil_c|, 535 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 536 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 537 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 538 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 539} 540 541static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 542 const TargetLowering::DAGCombinerInfo &DCI, 543 const MipsSETargetLowering *TL) { 544 EVT VT = N->getValueType(0); 545 546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 547 if (!VT.isVector()) 548 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 549 VT, TL->getScalarShiftAmountTy(VT), DAG); 550 551 return SDValue(N, 0); 552} 553 554static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 555 SelectionDAG &DAG, 556 const MipsSubtarget *Subtarget) { 557 // See if this is a vector splat immediate node. 558 APInt SplatValue, SplatUndef; 559 unsigned SplatBitSize; 560 bool HasAnyUndefs; 561 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 562 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 563 564 if (!BV || 565 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 566 EltSize, !Subtarget->isLittle()) || 567 (SplatBitSize != EltSize) || 568 (SplatValue.getZExtValue() >= EltSize)) 569 return SDValue(); 570 571 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 572 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 573} 574 575static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 576 TargetLowering::DAGCombinerInfo &DCI, 577 const MipsSubtarget *Subtarget) { 578 EVT Ty = N->getValueType(0); 579 580 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 581 return SDValue(); 582 583 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 584} 585 586// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 587// constant splats into MipsISD::SHRA_DSP for DSPr2. 588// 589// Performs the following transformations: 590// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 591// sign/zero-extension is completely overwritten by the new one performed by 592// the ISD::SRA and ISD::SHL nodes. 593// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 594// sequence. 595// 596// See performDSPShiftCombine for more information about the transformation 597// used for DSPr2. 598static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 599 TargetLowering::DAGCombinerInfo &DCI, 600 const MipsSubtarget *Subtarget) { 601 EVT Ty = N->getValueType(0); 602 603 if (Subtarget->hasMSA()) { 604 SDValue Op0 = N->getOperand(0); 605 SDValue Op1 = N->getOperand(1); 606 607 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 608 // where $d + sizeof($c) == 32 609 // or $d + sizeof($c) <= 32 and SExt 610 // -> (MipsVExtractSExt $a, $b, $c) 611 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 612 SDValue Op0Op0 = Op0->getOperand(0); 613 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 614 615 if (!ShAmount) 616 return SDValue(); 617 618 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 619 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 620 return SDValue(); 621 622 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 623 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 624 625 if (TotalBits == 32 || 626 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 627 TotalBits <= 32)) { 628 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 629 Op0Op0->getOperand(2) }; 630 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, 631 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands()); 632 return Op0Op0; 633 } 634 } 635 } 636 637 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) 638 return SDValue(); 639 640 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 641} 642 643 644static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 645 TargetLowering::DAGCombinerInfo &DCI, 646 const MipsSubtarget *Subtarget) { 647 EVT Ty = N->getValueType(0); 648 649 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) 650 return SDValue(); 651 652 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 653} 654 655static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 656 bool IsV216 = (Ty == MVT::v2i16); 657 658 switch (CC) { 659 case ISD::SETEQ: 660 case ISD::SETNE: return true; 661 case ISD::SETLT: 662 case ISD::SETLE: 663 case ISD::SETGT: 664 case ISD::SETGE: return IsV216; 665 case ISD::SETULT: 666 case ISD::SETULE: 667 case ISD::SETUGT: 668 case ISD::SETUGE: return !IsV216; 669 default: return false; 670 } 671} 672 673static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 674 EVT Ty = N->getValueType(0); 675 676 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 677 return SDValue(); 678 679 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 680 return SDValue(); 681 682 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 683 N->getOperand(1), N->getOperand(2)); 684} 685 686static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 687 EVT Ty = N->getValueType(0); 688 689 if (Ty.is128BitVector() && Ty.isInteger()) { 690 // Try the following combines: 691 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 692 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 693 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 694 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 695 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 696 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 697 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 698 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 699 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 700 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 701 // legalizer. 702 SDValue Op0 = N->getOperand(0); 703 704 if (Op0->getOpcode() != ISD::SETCC) 705 return SDValue(); 706 707 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 708 bool Signed; 709 710 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 711 Signed = true; 712 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 713 Signed = false; 714 else 715 return SDValue(); 716 717 SDValue Op1 = N->getOperand(1); 718 SDValue Op2 = N->getOperand(2); 719 SDValue Op0Op0 = Op0->getOperand(0); 720 SDValue Op0Op1 = Op0->getOperand(1); 721 722 if (Op1 == Op0Op0 && Op2 == Op0Op1) 723 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 724 Ty, Op1, Op2); 725 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 726 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 727 Ty, Op1, Op2); 728 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 729 SDValue SetCC = N->getOperand(0); 730 731 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 732 return SDValue(); 733 734 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 735 SetCC.getOperand(0), SetCC.getOperand(1), 736 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 737 } 738 739 return SDValue(); 740} 741 742static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 743 const MipsSubtarget *Subtarget) { 744 EVT Ty = N->getValueType(0); 745 746 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 747 // Try the following combines: 748 // (xor (or $a, $b), (build_vector allones)) 749 // (xor (or $a, $b), (bitcast (build_vector allones))) 750 SDValue Op0 = N->getOperand(0); 751 SDValue Op1 = N->getOperand(1); 752 SDValue NotOp; 753 754 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 755 NotOp = Op1; 756 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 757 NotOp = Op0; 758 else 759 return SDValue(); 760 761 if (NotOp->getOpcode() == ISD::OR) 762 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 763 NotOp->getOperand(1)); 764 } 765 766 return SDValue(); 767} 768 769SDValue 770MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 771 SelectionDAG &DAG = DCI.DAG; 772 SDValue Val; 773 774 switch (N->getOpcode()) { 775 case ISD::ADDE: 776 return performADDECombine(N, DAG, DCI, Subtarget); 777 case ISD::AND: 778 Val = performANDCombine(N, DAG, DCI, Subtarget); 779 break; 780 case ISD::SUBE: 781 return performSUBECombine(N, DAG, DCI, Subtarget); 782 case ISD::MUL: 783 return performMULCombine(N, DAG, DCI, this); 784 case ISD::SHL: 785 return performSHLCombine(N, DAG, DCI, Subtarget); 786 case ISD::SRA: 787 return performSRACombine(N, DAG, DCI, Subtarget); 788 case ISD::SRL: 789 return performSRLCombine(N, DAG, DCI, Subtarget); 790 case ISD::VSELECT: 791 return performVSELECTCombine(N, DAG); 792 case ISD::XOR: 793 Val = performXORCombine(N, DAG, Subtarget); 794 break; 795 case ISD::SETCC: 796 Val = performSETCCCombine(N, DAG); 797 break; 798 } 799 800 if (Val.getNode()) { 801 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; 802 N->printrWithDepth(dbgs(), &DAG); 803 dbgs() << "\n=> \n"; 804 Val.getNode()->printrWithDepth(dbgs(), &DAG); 805 dbgs() << "\n"); 806 return Val; 807 } 808 809 return MipsTargetLowering::PerformDAGCombine(N, DCI); 810} 811 812MachineBasicBlock * 813MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 814 MachineBasicBlock *BB) const { 815 switch (MI->getOpcode()) { 816 default: 817 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 818 case Mips::BPOSGE32_PSEUDO: 819 return emitBPOSGE32(MI, BB); 820 case Mips::SNZ_B_PSEUDO: 821 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 822 case Mips::SNZ_H_PSEUDO: 823 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 824 case Mips::SNZ_W_PSEUDO: 825 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 826 case Mips::SNZ_D_PSEUDO: 827 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 828 case Mips::SNZ_V_PSEUDO: 829 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 830 case Mips::SZ_B_PSEUDO: 831 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 832 case Mips::SZ_H_PSEUDO: 833 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 834 case Mips::SZ_W_PSEUDO: 835 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 836 case Mips::SZ_D_PSEUDO: 837 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 838 case Mips::SZ_V_PSEUDO: 839 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 840 case Mips::COPY_FW_PSEUDO: 841 return emitCOPY_FW(MI, BB); 842 case Mips::COPY_FD_PSEUDO: 843 return emitCOPY_FD(MI, BB); 844 case Mips::INSERT_FW_PSEUDO: 845 return emitINSERT_FW(MI, BB); 846 case Mips::INSERT_FD_PSEUDO: 847 return emitINSERT_FD(MI, BB); 848 case Mips::FILL_FW_PSEUDO: 849 return emitFILL_FW(MI, BB); 850 case Mips::FILL_FD_PSEUDO: 851 return emitFILL_FD(MI, BB); 852 case Mips::FEXP2_W_1_PSEUDO: 853 return emitFEXP2_W_1(MI, BB); 854 case Mips::FEXP2_D_1_PSEUDO: 855 return emitFEXP2_D_1(MI, BB); 856 } 857} 858 859bool MipsSETargetLowering:: 860isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 861 unsigned NextStackOffset, 862 const MipsFunctionInfo& FI) const { 863 if (!EnableMipsTailCalls) 864 return false; 865 866 // Return false if either the callee or caller has a byval argument. 867 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 868 return false; 869 870 // Return true if the callee's argument area is no larger than the 871 // caller's. 872 return NextStackOffset <= FI.getIncomingArgSize(); 873} 874 875void MipsSETargetLowering:: 876getOpndList(SmallVectorImpl<SDValue> &Ops, 877 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 878 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 879 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 880 // T9 should contain the address of the callee function if 881 // -reloction-model=pic or it is an indirect call. 882 if (IsPICCall || !GlobalOrExternal) { 883 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9; 884 RegsToPass.push_front(std::make_pair(T9Reg, Callee)); 885 } else 886 Ops.push_back(Callee); 887 888 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 889 InternalLinkage, CLI, Callee, Chain); 890} 891 892SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 893 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 894 895 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 896 return MipsTargetLowering::lowerLOAD(Op, DAG); 897 898 // Replace a double precision load with two i32 loads and a buildpair64. 899 SDLoc DL(Op); 900 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 901 EVT PtrVT = Ptr.getValueType(); 902 903 // i32 load from lower address. 904 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 905 MachinePointerInfo(), Nd.isVolatile(), 906 Nd.isNonTemporal(), Nd.isInvariant(), 907 Nd.getAlignment()); 908 909 // i32 load from higher address. 910 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 911 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 912 MachinePointerInfo(), Nd.isVolatile(), 913 Nd.isNonTemporal(), Nd.isInvariant(), 914 std::min(Nd.getAlignment(), 4U)); 915 916 if (!Subtarget->isLittle()) 917 std::swap(Lo, Hi); 918 919 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 920 SDValue Ops[2] = {BP, Hi.getValue(1)}; 921 return DAG.getMergeValues(Ops, 2, DL); 922} 923 924SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 925 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 926 927 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 928 return MipsTargetLowering::lowerSTORE(Op, DAG); 929 930 // Replace a double precision store with two extractelement64s and i32 stores. 931 SDLoc DL(Op); 932 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 933 EVT PtrVT = Ptr.getValueType(); 934 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 935 Val, DAG.getConstant(0, MVT::i32)); 936 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 937 Val, DAG.getConstant(1, MVT::i32)); 938 939 if (!Subtarget->isLittle()) 940 std::swap(Lo, Hi); 941 942 // i32 store to lower address. 943 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 944 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 945 Nd.getTBAAInfo()); 946 947 // i32 store to higher address. 948 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 949 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 950 Nd.isVolatile(), Nd.isNonTemporal(), 951 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); 952} 953 954SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 955 bool HasLo, bool HasHi, 956 SelectionDAG &DAG) const { 957 EVT Ty = Op.getOperand(0).getValueType(); 958 SDLoc DL(Op); 959 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 960 Op.getOperand(0), Op.getOperand(1)); 961 SDValue Lo, Hi; 962 963 if (HasLo) 964 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); 965 if (HasHi) 966 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); 967 968 if (!HasLo || !HasHi) 969 return HasLo ? Lo : Hi; 970 971 SDValue Vals[] = { Lo, Hi }; 972 return DAG.getMergeValues(Vals, 2, DL); 973} 974 975 976static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 977 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 978 DAG.getConstant(0, MVT::i32)); 979 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 980 DAG.getConstant(1, MVT::i32)); 981 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); 982} 983 984static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 985 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); 986 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); 987 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 988} 989 990// This function expands mips intrinsic nodes which have 64-bit input operands 991// or output values. 992// 993// out64 = intrinsic-node in64 994// => 995// lo = copy (extract-element (in64, 0)) 996// hi = copy (extract-element (in64, 1)) 997// mips-specific-node 998// v0 = copy lo 999// v1 = copy hi 1000// out64 = merge-values (v0, v1) 1001// 1002static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1003 SDLoc DL(Op); 1004 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 1005 SmallVector<SDValue, 3> Ops; 1006 unsigned OpNo = 0; 1007 1008 // See if Op has a chain input. 1009 if (HasChainIn) 1010 Ops.push_back(Op->getOperand(OpNo++)); 1011 1012 // The next operand is the intrinsic opcode. 1013 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1014 1015 // See if the next operand has type i64. 1016 SDValue Opnd = Op->getOperand(++OpNo), In64; 1017 1018 if (Opnd.getValueType() == MVT::i64) 1019 In64 = initAccumulator(Opnd, DL, DAG); 1020 else 1021 Ops.push_back(Opnd); 1022 1023 // Push the remaining operands. 1024 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1025 Ops.push_back(Op->getOperand(OpNo)); 1026 1027 // Add In64 to the end of the list. 1028 if (In64.getNode()) 1029 Ops.push_back(In64); 1030 1031 // Scan output. 1032 SmallVector<EVT, 2> ResTys; 1033 1034 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1035 I != E; ++I) 1036 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1037 1038 // Create node. 1039 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); 1040 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1041 1042 if (!HasChainIn) 1043 return Out; 1044 1045 assert(Val->getValueType(1) == MVT::Other); 1046 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1047 return DAG.getMergeValues(Vals, 2, DL); 1048} 1049 1050// Lower an MSA copy intrinsic into the specified SelectionDAG node 1051static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1052 SDLoc DL(Op); 1053 SDValue Vec = Op->getOperand(1); 1054 SDValue Idx = Op->getOperand(2); 1055 EVT ResTy = Op->getValueType(0); 1056 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1057 1058 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1059 DAG.getValueType(EltTy)); 1060 1061 return Result; 1062} 1063 1064static SDValue 1065lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) { 1066 EVT ViaVecTy = ResTy; 1067 SmallVector<SDValue, 16> Ops; 1068 SDValue ImmHiOp; 1069 1070 if (ViaVecTy == MVT::v2i64) { 1071 ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp, 1072 DAG.getConstant(31, MVT::i32)); 1073 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) { 1074 Ops.push_back(ImmHiOp); 1075 Ops.push_back(ImmOp); 1076 } 1077 ViaVecTy = MVT::v4i32; 1078 } else { 1079 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1080 Ops.push_back(ImmOp); 1081 } 1082 1083 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0], 1084 Ops.size()); 1085 1086 if (ResTy != ViaVecTy) 1087 Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result); 1088 1089 return Result; 1090} 1091 1092static SDValue 1093lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1094 return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0), 1095 Op->getOperand(ImmOp), DAG); 1096} 1097 1098SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1099 SelectionDAG &DAG) const { 1100 SDLoc DL(Op); 1101 1102 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1103 default: 1104 return SDValue(); 1105 case Intrinsic::mips_shilo: 1106 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1107 case Intrinsic::mips_dpau_h_qbl: 1108 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1109 case Intrinsic::mips_dpau_h_qbr: 1110 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1111 case Intrinsic::mips_dpsu_h_qbl: 1112 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1113 case Intrinsic::mips_dpsu_h_qbr: 1114 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1115 case Intrinsic::mips_dpa_w_ph: 1116 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1117 case Intrinsic::mips_dps_w_ph: 1118 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1119 case Intrinsic::mips_dpax_w_ph: 1120 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1121 case Intrinsic::mips_dpsx_w_ph: 1122 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1123 case Intrinsic::mips_mulsa_w_ph: 1124 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1125 case Intrinsic::mips_mult: 1126 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1127 case Intrinsic::mips_multu: 1128 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1129 case Intrinsic::mips_madd: 1130 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1131 case Intrinsic::mips_maddu: 1132 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1133 case Intrinsic::mips_msub: 1134 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1135 case Intrinsic::mips_msubu: 1136 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1137 case Intrinsic::mips_addv_b: 1138 case Intrinsic::mips_addv_h: 1139 case Intrinsic::mips_addv_w: 1140 case Intrinsic::mips_addv_d: 1141 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1142 Op->getOperand(2)); 1143 case Intrinsic::mips_addvi_b: 1144 case Intrinsic::mips_addvi_h: 1145 case Intrinsic::mips_addvi_w: 1146 case Intrinsic::mips_addvi_d: 1147 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1148 lowerMSASplatImm(Op, 2, DAG)); 1149 case Intrinsic::mips_and_v: 1150 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1151 Op->getOperand(2)); 1152 case Intrinsic::mips_andi_b: 1153 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1154 lowerMSASplatImm(Op, 2, DAG)); 1155 case Intrinsic::mips_bnz_b: 1156 case Intrinsic::mips_bnz_h: 1157 case Intrinsic::mips_bnz_w: 1158 case Intrinsic::mips_bnz_d: 1159 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1160 Op->getOperand(1)); 1161 case Intrinsic::mips_bnz_v: 1162 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1163 Op->getOperand(1)); 1164 case Intrinsic::mips_bsel_v: 1165 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1166 Op->getOperand(1), Op->getOperand(2), 1167 Op->getOperand(3)); 1168 case Intrinsic::mips_bseli_b: 1169 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1170 Op->getOperand(1), Op->getOperand(2), 1171 lowerMSASplatImm(Op, 3, DAG)); 1172 case Intrinsic::mips_bz_b: 1173 case Intrinsic::mips_bz_h: 1174 case Intrinsic::mips_bz_w: 1175 case Intrinsic::mips_bz_d: 1176 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1177 Op->getOperand(1)); 1178 case Intrinsic::mips_bz_v: 1179 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1180 Op->getOperand(1)); 1181 case Intrinsic::mips_ceq_b: 1182 case Intrinsic::mips_ceq_h: 1183 case Intrinsic::mips_ceq_w: 1184 case Intrinsic::mips_ceq_d: 1185 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1186 Op->getOperand(2), ISD::SETEQ); 1187 case Intrinsic::mips_ceqi_b: 1188 case Intrinsic::mips_ceqi_h: 1189 case Intrinsic::mips_ceqi_w: 1190 case Intrinsic::mips_ceqi_d: 1191 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1192 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1193 case Intrinsic::mips_cle_s_b: 1194 case Intrinsic::mips_cle_s_h: 1195 case Intrinsic::mips_cle_s_w: 1196 case Intrinsic::mips_cle_s_d: 1197 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1198 Op->getOperand(2), ISD::SETLE); 1199 case Intrinsic::mips_clei_s_b: 1200 case Intrinsic::mips_clei_s_h: 1201 case Intrinsic::mips_clei_s_w: 1202 case Intrinsic::mips_clei_s_d: 1203 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1204 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1205 case Intrinsic::mips_cle_u_b: 1206 case Intrinsic::mips_cle_u_h: 1207 case Intrinsic::mips_cle_u_w: 1208 case Intrinsic::mips_cle_u_d: 1209 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1210 Op->getOperand(2), ISD::SETULE); 1211 case Intrinsic::mips_clei_u_b: 1212 case Intrinsic::mips_clei_u_h: 1213 case Intrinsic::mips_clei_u_w: 1214 case Intrinsic::mips_clei_u_d: 1215 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1216 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1217 case Intrinsic::mips_clt_s_b: 1218 case Intrinsic::mips_clt_s_h: 1219 case Intrinsic::mips_clt_s_w: 1220 case Intrinsic::mips_clt_s_d: 1221 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1222 Op->getOperand(2), ISD::SETLT); 1223 case Intrinsic::mips_clti_s_b: 1224 case Intrinsic::mips_clti_s_h: 1225 case Intrinsic::mips_clti_s_w: 1226 case Intrinsic::mips_clti_s_d: 1227 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1228 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1229 case Intrinsic::mips_clt_u_b: 1230 case Intrinsic::mips_clt_u_h: 1231 case Intrinsic::mips_clt_u_w: 1232 case Intrinsic::mips_clt_u_d: 1233 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1234 Op->getOperand(2), ISD::SETULT); 1235 case Intrinsic::mips_clti_u_b: 1236 case Intrinsic::mips_clti_u_h: 1237 case Intrinsic::mips_clti_u_w: 1238 case Intrinsic::mips_clti_u_d: 1239 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1240 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1241 case Intrinsic::mips_copy_s_b: 1242 case Intrinsic::mips_copy_s_h: 1243 case Intrinsic::mips_copy_s_w: 1244 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1245 case Intrinsic::mips_copy_s_d: 1246 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal. 1247 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1248 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1249 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1250 Op->getOperand(1), Op->getOperand(2)); 1251 case Intrinsic::mips_copy_u_b: 1252 case Intrinsic::mips_copy_u_h: 1253 case Intrinsic::mips_copy_u_w: 1254 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1255 case Intrinsic::mips_copy_u_d: 1256 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal. 1257 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1258 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1259 // 1260 // Note: When i64 is illegal, this results in copy_s.w instructions instead 1261 // of copy_u.w instructions. This makes no difference to the behaviour 1262 // since i64 is only illegal when the register file is 32-bit. 1263 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1264 Op->getOperand(1), Op->getOperand(2)); 1265 case Intrinsic::mips_div_s_b: 1266 case Intrinsic::mips_div_s_h: 1267 case Intrinsic::mips_div_s_w: 1268 case Intrinsic::mips_div_s_d: 1269 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1270 Op->getOperand(2)); 1271 case Intrinsic::mips_div_u_b: 1272 case Intrinsic::mips_div_u_h: 1273 case Intrinsic::mips_div_u_w: 1274 case Intrinsic::mips_div_u_d: 1275 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1276 Op->getOperand(2)); 1277 case Intrinsic::mips_fadd_w: 1278 case Intrinsic::mips_fadd_d: 1279 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1280 Op->getOperand(2)); 1281 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1282 case Intrinsic::mips_fceq_w: 1283 case Intrinsic::mips_fceq_d: 1284 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1285 Op->getOperand(2), ISD::SETOEQ); 1286 case Intrinsic::mips_fcle_w: 1287 case Intrinsic::mips_fcle_d: 1288 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1289 Op->getOperand(2), ISD::SETOLE); 1290 case Intrinsic::mips_fclt_w: 1291 case Intrinsic::mips_fclt_d: 1292 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1293 Op->getOperand(2), ISD::SETOLT); 1294 case Intrinsic::mips_fcne_w: 1295 case Intrinsic::mips_fcne_d: 1296 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1297 Op->getOperand(2), ISD::SETONE); 1298 case Intrinsic::mips_fcor_w: 1299 case Intrinsic::mips_fcor_d: 1300 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1301 Op->getOperand(2), ISD::SETO); 1302 case Intrinsic::mips_fcueq_w: 1303 case Intrinsic::mips_fcueq_d: 1304 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1305 Op->getOperand(2), ISD::SETUEQ); 1306 case Intrinsic::mips_fcule_w: 1307 case Intrinsic::mips_fcule_d: 1308 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1309 Op->getOperand(2), ISD::SETULE); 1310 case Intrinsic::mips_fcult_w: 1311 case Intrinsic::mips_fcult_d: 1312 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1313 Op->getOperand(2), ISD::SETULT); 1314 case Intrinsic::mips_fcun_w: 1315 case Intrinsic::mips_fcun_d: 1316 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1317 Op->getOperand(2), ISD::SETUO); 1318 case Intrinsic::mips_fcune_w: 1319 case Intrinsic::mips_fcune_d: 1320 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1321 Op->getOperand(2), ISD::SETUNE); 1322 case Intrinsic::mips_fdiv_w: 1323 case Intrinsic::mips_fdiv_d: 1324 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1325 Op->getOperand(2)); 1326 case Intrinsic::mips_ffint_u_w: 1327 case Intrinsic::mips_ffint_u_d: 1328 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), 1329 Op->getOperand(1)); 1330 case Intrinsic::mips_ffint_s_w: 1331 case Intrinsic::mips_ffint_s_d: 1332 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), 1333 Op->getOperand(1)); 1334 case Intrinsic::mips_fill_b: 1335 case Intrinsic::mips_fill_h: 1336 case Intrinsic::mips_fill_w: 1337 case Intrinsic::mips_fill_d: { 1338 SmallVector<SDValue, 16> Ops; 1339 EVT ResTy = Op->getValueType(0); 1340 1341 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1342 Ops.push_back(Op->getOperand(1)); 1343 1344 // If ResTy is v2i64 then the type legalizer will break this node down into 1345 // an equivalent v4i32. 1346 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); 1347 } 1348 case Intrinsic::mips_fexp2_w: 1349 case Intrinsic::mips_fexp2_d: { 1350 EVT ResTy = Op->getValueType(0); 1351 return DAG.getNode( 1352 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), 1353 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); 1354 } 1355 case Intrinsic::mips_flog2_w: 1356 case Intrinsic::mips_flog2_d: 1357 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1358 case Intrinsic::mips_fmadd_w: 1359 case Intrinsic::mips_fmadd_d: 1360 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), 1361 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1362 case Intrinsic::mips_fmul_w: 1363 case Intrinsic::mips_fmul_d: 1364 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1365 Op->getOperand(2)); 1366 case Intrinsic::mips_fmsub_w: 1367 case Intrinsic::mips_fmsub_d: { 1368 EVT ResTy = Op->getValueType(0); 1369 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1), 1370 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, 1371 Op->getOperand(2), Op->getOperand(3))); 1372 } 1373 case Intrinsic::mips_frint_w: 1374 case Intrinsic::mips_frint_d: 1375 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1376 case Intrinsic::mips_fsqrt_w: 1377 case Intrinsic::mips_fsqrt_d: 1378 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1379 case Intrinsic::mips_fsub_w: 1380 case Intrinsic::mips_fsub_d: 1381 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1382 Op->getOperand(2)); 1383 case Intrinsic::mips_ftrunc_u_w: 1384 case Intrinsic::mips_ftrunc_u_d: 1385 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), 1386 Op->getOperand(1)); 1387 case Intrinsic::mips_ftrunc_s_w: 1388 case Intrinsic::mips_ftrunc_s_d: 1389 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), 1390 Op->getOperand(1)); 1391 case Intrinsic::mips_ilvev_b: 1392 case Intrinsic::mips_ilvev_h: 1393 case Intrinsic::mips_ilvev_w: 1394 case Intrinsic::mips_ilvev_d: 1395 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1396 Op->getOperand(1), Op->getOperand(2)); 1397 case Intrinsic::mips_ilvl_b: 1398 case Intrinsic::mips_ilvl_h: 1399 case Intrinsic::mips_ilvl_w: 1400 case Intrinsic::mips_ilvl_d: 1401 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1402 Op->getOperand(1), Op->getOperand(2)); 1403 case Intrinsic::mips_ilvod_b: 1404 case Intrinsic::mips_ilvod_h: 1405 case Intrinsic::mips_ilvod_w: 1406 case Intrinsic::mips_ilvod_d: 1407 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1408 Op->getOperand(1), Op->getOperand(2)); 1409 case Intrinsic::mips_ilvr_b: 1410 case Intrinsic::mips_ilvr_h: 1411 case Intrinsic::mips_ilvr_w: 1412 case Intrinsic::mips_ilvr_d: 1413 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1414 Op->getOperand(1), Op->getOperand(2)); 1415 case Intrinsic::mips_insert_b: 1416 case Intrinsic::mips_insert_h: 1417 case Intrinsic::mips_insert_w: 1418 case Intrinsic::mips_insert_d: 1419 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1420 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1421 case Intrinsic::mips_ldi_b: 1422 case Intrinsic::mips_ldi_h: 1423 case Intrinsic::mips_ldi_w: 1424 case Intrinsic::mips_ldi_d: 1425 return lowerMSASplatImm(Op, 1, DAG); 1426 case Intrinsic::mips_lsa: { 1427 EVT ResTy = Op->getValueType(0); 1428 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1429 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, 1430 Op->getOperand(2), Op->getOperand(3))); 1431 } 1432 case Intrinsic::mips_maddv_b: 1433 case Intrinsic::mips_maddv_h: 1434 case Intrinsic::mips_maddv_w: 1435 case Intrinsic::mips_maddv_d: { 1436 EVT ResTy = Op->getValueType(0); 1437 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1438 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1439 Op->getOperand(2), Op->getOperand(3))); 1440 } 1441 case Intrinsic::mips_max_s_b: 1442 case Intrinsic::mips_max_s_h: 1443 case Intrinsic::mips_max_s_w: 1444 case Intrinsic::mips_max_s_d: 1445 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1446 Op->getOperand(1), Op->getOperand(2)); 1447 case Intrinsic::mips_max_u_b: 1448 case Intrinsic::mips_max_u_h: 1449 case Intrinsic::mips_max_u_w: 1450 case Intrinsic::mips_max_u_d: 1451 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1452 Op->getOperand(1), Op->getOperand(2)); 1453 case Intrinsic::mips_maxi_s_b: 1454 case Intrinsic::mips_maxi_s_h: 1455 case Intrinsic::mips_maxi_s_w: 1456 case Intrinsic::mips_maxi_s_d: 1457 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1458 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1459 case Intrinsic::mips_maxi_u_b: 1460 case Intrinsic::mips_maxi_u_h: 1461 case Intrinsic::mips_maxi_u_w: 1462 case Intrinsic::mips_maxi_u_d: 1463 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1464 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1465 case Intrinsic::mips_min_s_b: 1466 case Intrinsic::mips_min_s_h: 1467 case Intrinsic::mips_min_s_w: 1468 case Intrinsic::mips_min_s_d: 1469 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1470 Op->getOperand(1), Op->getOperand(2)); 1471 case Intrinsic::mips_min_u_b: 1472 case Intrinsic::mips_min_u_h: 1473 case Intrinsic::mips_min_u_w: 1474 case Intrinsic::mips_min_u_d: 1475 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1476 Op->getOperand(1), Op->getOperand(2)); 1477 case Intrinsic::mips_mini_s_b: 1478 case Intrinsic::mips_mini_s_h: 1479 case Intrinsic::mips_mini_s_w: 1480 case Intrinsic::mips_mini_s_d: 1481 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1482 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1483 case Intrinsic::mips_mini_u_b: 1484 case Intrinsic::mips_mini_u_h: 1485 case Intrinsic::mips_mini_u_w: 1486 case Intrinsic::mips_mini_u_d: 1487 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1488 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1489 case Intrinsic::mips_mod_s_b: 1490 case Intrinsic::mips_mod_s_h: 1491 case Intrinsic::mips_mod_s_w: 1492 case Intrinsic::mips_mod_s_d: 1493 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), 1494 Op->getOperand(2)); 1495 case Intrinsic::mips_mod_u_b: 1496 case Intrinsic::mips_mod_u_h: 1497 case Intrinsic::mips_mod_u_w: 1498 case Intrinsic::mips_mod_u_d: 1499 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), 1500 Op->getOperand(2)); 1501 case Intrinsic::mips_mulv_b: 1502 case Intrinsic::mips_mulv_h: 1503 case Intrinsic::mips_mulv_w: 1504 case Intrinsic::mips_mulv_d: 1505 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 1506 Op->getOperand(2)); 1507 case Intrinsic::mips_msubv_b: 1508 case Intrinsic::mips_msubv_h: 1509 case Intrinsic::mips_msubv_w: 1510 case Intrinsic::mips_msubv_d: { 1511 EVT ResTy = Op->getValueType(0); 1512 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), 1513 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1514 Op->getOperand(2), Op->getOperand(3))); 1515 } 1516 case Intrinsic::mips_nlzc_b: 1517 case Intrinsic::mips_nlzc_h: 1518 case Intrinsic::mips_nlzc_w: 1519 case Intrinsic::mips_nlzc_d: 1520 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 1521 case Intrinsic::mips_nor_v: { 1522 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1523 Op->getOperand(1), Op->getOperand(2)); 1524 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1525 } 1526 case Intrinsic::mips_nori_b: { 1527 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1528 Op->getOperand(1), 1529 lowerMSASplatImm(Op, 2, DAG)); 1530 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1531 } 1532 case Intrinsic::mips_or_v: 1533 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 1534 Op->getOperand(2)); 1535 case Intrinsic::mips_ori_b: 1536 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1537 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1538 case Intrinsic::mips_pckev_b: 1539 case Intrinsic::mips_pckev_h: 1540 case Intrinsic::mips_pckev_w: 1541 case Intrinsic::mips_pckev_d: 1542 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 1543 Op->getOperand(1), Op->getOperand(2)); 1544 case Intrinsic::mips_pckod_b: 1545 case Intrinsic::mips_pckod_h: 1546 case Intrinsic::mips_pckod_w: 1547 case Intrinsic::mips_pckod_d: 1548 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 1549 Op->getOperand(1), Op->getOperand(2)); 1550 case Intrinsic::mips_pcnt_b: 1551 case Intrinsic::mips_pcnt_h: 1552 case Intrinsic::mips_pcnt_w: 1553 case Intrinsic::mips_pcnt_d: 1554 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 1555 case Intrinsic::mips_shf_b: 1556 case Intrinsic::mips_shf_h: 1557 case Intrinsic::mips_shf_w: 1558 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 1559 Op->getOperand(2), Op->getOperand(1)); 1560 case Intrinsic::mips_sll_b: 1561 case Intrinsic::mips_sll_h: 1562 case Intrinsic::mips_sll_w: 1563 case Intrinsic::mips_sll_d: 1564 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 1565 Op->getOperand(2)); 1566 case Intrinsic::mips_slli_b: 1567 case Intrinsic::mips_slli_h: 1568 case Intrinsic::mips_slli_w: 1569 case Intrinsic::mips_slli_d: 1570 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 1571 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1572 case Intrinsic::mips_splat_b: 1573 case Intrinsic::mips_splat_h: 1574 case Intrinsic::mips_splat_w: 1575 case Intrinsic::mips_splat_d: 1576 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle 1577 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because 1578 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32. 1579 // Instead we lower to MipsISD::VSHF and match from there. 1580 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1581 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1582 Op->getOperand(1)); 1583 case Intrinsic::mips_splati_b: 1584 case Intrinsic::mips_splati_h: 1585 case Intrinsic::mips_splati_w: 1586 case Intrinsic::mips_splati_d: 1587 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1588 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1589 Op->getOperand(1)); 1590 case Intrinsic::mips_sra_b: 1591 case Intrinsic::mips_sra_h: 1592 case Intrinsic::mips_sra_w: 1593 case Intrinsic::mips_sra_d: 1594 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 1595 Op->getOperand(2)); 1596 case Intrinsic::mips_srai_b: 1597 case Intrinsic::mips_srai_h: 1598 case Intrinsic::mips_srai_w: 1599 case Intrinsic::mips_srai_d: 1600 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 1601 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1602 case Intrinsic::mips_srl_b: 1603 case Intrinsic::mips_srl_h: 1604 case Intrinsic::mips_srl_w: 1605 case Intrinsic::mips_srl_d: 1606 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 1607 Op->getOperand(2)); 1608 case Intrinsic::mips_srli_b: 1609 case Intrinsic::mips_srli_h: 1610 case Intrinsic::mips_srli_w: 1611 case Intrinsic::mips_srli_d: 1612 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 1613 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1614 case Intrinsic::mips_subv_b: 1615 case Intrinsic::mips_subv_h: 1616 case Intrinsic::mips_subv_w: 1617 case Intrinsic::mips_subv_d: 1618 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 1619 Op->getOperand(2)); 1620 case Intrinsic::mips_subvi_b: 1621 case Intrinsic::mips_subvi_h: 1622 case Intrinsic::mips_subvi_w: 1623 case Intrinsic::mips_subvi_d: 1624 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 1625 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1626 case Intrinsic::mips_vshf_b: 1627 case Intrinsic::mips_vshf_h: 1628 case Intrinsic::mips_vshf_w: 1629 case Intrinsic::mips_vshf_d: 1630 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1631 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1632 case Intrinsic::mips_xor_v: 1633 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 1634 Op->getOperand(2)); 1635 case Intrinsic::mips_xori_b: 1636 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 1637 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1638 } 1639} 1640 1641static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1642 SDLoc DL(Op); 1643 SDValue ChainIn = Op->getOperand(0); 1644 SDValue Address = Op->getOperand(2); 1645 SDValue Offset = Op->getOperand(3); 1646 EVT ResTy = Op->getValueType(0); 1647 EVT PtrTy = Address->getValueType(0); 1648 1649 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1650 1651 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 1652 false, false, 16); 1653} 1654 1655SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 1656 SelectionDAG &DAG) const { 1657 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1658 switch (Intr) { 1659 default: 1660 return SDValue(); 1661 case Intrinsic::mips_extp: 1662 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 1663 case Intrinsic::mips_extpdp: 1664 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 1665 case Intrinsic::mips_extr_w: 1666 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 1667 case Intrinsic::mips_extr_r_w: 1668 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 1669 case Intrinsic::mips_extr_rs_w: 1670 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 1671 case Intrinsic::mips_extr_s_h: 1672 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 1673 case Intrinsic::mips_mthlip: 1674 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 1675 case Intrinsic::mips_mulsaq_s_w_ph: 1676 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 1677 case Intrinsic::mips_maq_s_w_phl: 1678 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 1679 case Intrinsic::mips_maq_s_w_phr: 1680 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 1681 case Intrinsic::mips_maq_sa_w_phl: 1682 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 1683 case Intrinsic::mips_maq_sa_w_phr: 1684 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 1685 case Intrinsic::mips_dpaq_s_w_ph: 1686 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 1687 case Intrinsic::mips_dpsq_s_w_ph: 1688 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 1689 case Intrinsic::mips_dpaq_sa_l_w: 1690 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 1691 case Intrinsic::mips_dpsq_sa_l_w: 1692 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 1693 case Intrinsic::mips_dpaqx_s_w_ph: 1694 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 1695 case Intrinsic::mips_dpaqx_sa_w_ph: 1696 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 1697 case Intrinsic::mips_dpsqx_s_w_ph: 1698 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 1699 case Intrinsic::mips_dpsqx_sa_w_ph: 1700 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 1701 case Intrinsic::mips_ld_b: 1702 case Intrinsic::mips_ld_h: 1703 case Intrinsic::mips_ld_w: 1704 case Intrinsic::mips_ld_d: 1705 return lowerMSALoadIntr(Op, DAG, Intr); 1706 } 1707} 1708 1709static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 1710 SDLoc DL(Op); 1711 SDValue ChainIn = Op->getOperand(0); 1712 SDValue Value = Op->getOperand(2); 1713 SDValue Address = Op->getOperand(3); 1714 SDValue Offset = Op->getOperand(4); 1715 EVT PtrTy = Address->getValueType(0); 1716 1717 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 1718 1719 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 1720 false, 16); 1721} 1722 1723SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 1724 SelectionDAG &DAG) const { 1725 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 1726 switch (Intr) { 1727 default: 1728 return SDValue(); 1729 case Intrinsic::mips_st_b: 1730 case Intrinsic::mips_st_h: 1731 case Intrinsic::mips_st_w: 1732 case Intrinsic::mips_st_d: 1733 return lowerMSAStoreIntr(Op, DAG, Intr); 1734 } 1735} 1736 1737/// \brief Check if the given BuildVectorSDNode is a splat. 1738/// This method currently relies on DAG nodes being reused when equivalent, 1739/// so it's possible for this to return false even when isConstantSplat returns 1740/// true. 1741static bool isSplatVector(const BuildVectorSDNode *N) { 1742 unsigned int nOps = N->getNumOperands(); 1743 assert(nOps > 1 && "isSplat has 0 or 1 sized build vector"); 1744 1745 SDValue Operand0 = N->getOperand(0); 1746 1747 for (unsigned int i = 1; i < nOps; ++i) { 1748 if (N->getOperand(i) != Operand0) 1749 return false; 1750 } 1751 1752 return true; 1753} 1754 1755// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 1756// 1757// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 1758// choose to sign-extend but we could have equally chosen zero-extend. The 1759// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 1760// result into this node later (possibly changing it to a zero-extend in the 1761// process). 1762SDValue MipsSETargetLowering:: 1763lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 1764 SDLoc DL(Op); 1765 EVT ResTy = Op->getValueType(0); 1766 SDValue Op0 = Op->getOperand(0); 1767 EVT VecTy = Op0->getValueType(0); 1768 1769 if (!VecTy.is128BitVector()) 1770 return SDValue(); 1771 1772 if (ResTy.isInteger()) { 1773 SDValue Op1 = Op->getOperand(1); 1774 EVT EltTy = VecTy.getVectorElementType(); 1775 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 1776 DAG.getValueType(EltTy)); 1777 } 1778 1779 return Op; 1780} 1781 1782static bool isConstantOrUndef(const SDValue Op) { 1783 if (Op->getOpcode() == ISD::UNDEF) 1784 return true; 1785 if (dyn_cast<ConstantSDNode>(Op)) 1786 return true; 1787 if (dyn_cast<ConstantFPSDNode>(Op)) 1788 return true; 1789 return false; 1790} 1791 1792static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 1793 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 1794 if (isConstantOrUndef(Op->getOperand(i))) 1795 return true; 1796 return false; 1797} 1798 1799// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 1800// backend. 1801// 1802// Lowers according to the following rules: 1803// - Constant splats are legal as-is as long as the SplatBitSize is a power of 1804// 2 less than or equal to 64 and the value fits into a signed 10-bit 1805// immediate 1806// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 1807// is a power of 2 less than or equal to 64 and the value does not fit into a 1808// signed 10-bit immediate 1809// - Non-constant splats are legal as-is. 1810// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 1811// - All others are illegal and must be expanded. 1812SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 1813 SelectionDAG &DAG) const { 1814 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 1815 EVT ResTy = Op->getValueType(0); 1816 SDLoc DL(Op); 1817 APInt SplatValue, SplatUndef; 1818 unsigned SplatBitSize; 1819 bool HasAnyUndefs; 1820 1821 if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) 1822 return SDValue(); 1823 1824 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 1825 HasAnyUndefs, 8, 1826 !Subtarget->isLittle()) && SplatBitSize <= 64) { 1827 // We can only cope with 8, 16, 32, or 64-bit elements 1828 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 1829 SplatBitSize != 64) 1830 return SDValue(); 1831 1832 // If the value fits into a simm10 then we can use ldi.[bhwd] 1833 if (SplatValue.isSignedIntN(10)) 1834 return Op; 1835 1836 EVT ViaVecTy; 1837 1838 switch (SplatBitSize) { 1839 default: 1840 return SDValue(); 1841 case 8: 1842 ViaVecTy = MVT::v16i8; 1843 break; 1844 case 16: 1845 ViaVecTy = MVT::v8i16; 1846 break; 1847 case 32: 1848 ViaVecTy = MVT::v4i32; 1849 break; 1850 case 64: 1851 // There's no fill.d to fall back on for 64-bit values 1852 return SDValue(); 1853 } 1854 1855 SmallVector<SDValue, 16> Ops; 1856 SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32); 1857 1858 for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) 1859 Ops.push_back(Constant); 1860 1861 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy, 1862 &Ops[0], Ops.size()); 1863 1864 if (ViaVecTy != ResTy) 1865 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 1866 1867 return Result; 1868 } else if (isSplatVector(Node)) 1869 return Op; 1870 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 1871 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 1872 // The resulting code is the same length as the expansion, but it doesn't 1873 // use memory operations 1874 EVT ResTy = Node->getValueType(0); 1875 1876 assert(ResTy.isVector()); 1877 1878 unsigned NumElts = ResTy.getVectorNumElements(); 1879 SDValue Vector = DAG.getUNDEF(ResTy); 1880 for (unsigned i = 0; i < NumElts; ++i) { 1881 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 1882 Node->getOperand(i), 1883 DAG.getConstant(i, MVT::i32)); 1884 } 1885 return Vector; 1886 } 1887 1888 return SDValue(); 1889} 1890 1891// Lower VECTOR_SHUFFLE into SHF (if possible). 1892// 1893// SHF splits the vector into blocks of four elements, then shuffles these 1894// elements according to a <4 x i2> constant (encoded as an integer immediate). 1895// 1896// It is therefore possible to lower into SHF when the mask takes the form: 1897// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 1898// When undef's appear they are treated as if they were whatever value is 1899// necessary in order to fit the above form. 1900// 1901// For example: 1902// %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 1903// <8 x i32> <i32 3, i32 2, i32 1, i32 0, 1904// i32 7, i32 6, i32 5, i32 4> 1905// is lowered to: 1906// (SHF_H $w0, $w1, 27) 1907// where the 27 comes from: 1908// 3 + (2 << 2) + (1 << 4) + (0 << 6) 1909static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 1910 SmallVector<int, 16> Indices, 1911 SelectionDAG &DAG) { 1912 int SHFIndices[4] = { -1, -1, -1, -1 }; 1913 1914 if (Indices.size() < 4) 1915 return SDValue(); 1916 1917 for (unsigned i = 0; i < 4; ++i) { 1918 for (unsigned j = i; j < Indices.size(); j += 4) { 1919 int Idx = Indices[j]; 1920 1921 // Convert from vector index to 4-element subvector index 1922 // If an index refers to an element outside of the subvector then give up 1923 if (Idx != -1) { 1924 Idx -= 4 * (j / 4); 1925 if (Idx < 0 || Idx >= 4) 1926 return SDValue(); 1927 } 1928 1929 // If the mask has an undef, replace it with the current index. 1930 // Note that it might still be undef if the current index is also undef 1931 if (SHFIndices[i] == -1) 1932 SHFIndices[i] = Idx; 1933 1934 // Check that non-undef values are the same as in the mask. If they 1935 // aren't then give up 1936 if (!(Idx == -1 || Idx == SHFIndices[i])) 1937 return SDValue(); 1938 } 1939 } 1940 1941 // Calculate the immediate. Replace any remaining undefs with zero 1942 APInt Imm(32, 0); 1943 for (int i = 3; i >= 0; --i) { 1944 int Idx = SHFIndices[i]; 1945 1946 if (Idx == -1) 1947 Idx = 0; 1948 1949 Imm <<= 2; 1950 Imm |= Idx & 0x3; 1951 } 1952 1953 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 1954 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 1955} 1956 1957// Lower VECTOR_SHUFFLE into ILVEV (if possible). 1958// 1959// ILVEV interleaves the even elements from each vector. 1960// 1961// It is possible to lower into ILVEV when the mask takes the form: 1962// <0, n, 2, n+2, 4, n+4, ...> 1963// where n is the number of elements in the vector. 1964// 1965// When undef's appear in the mask they are treated as if they were whatever 1966// value is necessary in order to fit the above form. 1967static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 1968 SmallVector<int, 16> Indices, 1969 SelectionDAG &DAG) { 1970 assert ((Indices.size() % 2) == 0); 1971 int WsIdx = 0; 1972 int WtIdx = ResTy.getVectorNumElements(); 1973 1974 for (unsigned i = 0; i < Indices.size(); i += 2) { 1975 if (Indices[i] != -1 && Indices[i] != WsIdx) 1976 return SDValue(); 1977 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 1978 return SDValue(); 1979 WsIdx += 2; 1980 WtIdx += 2; 1981 } 1982 1983 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 1984 Op->getOperand(1)); 1985} 1986 1987// Lower VECTOR_SHUFFLE into ILVOD (if possible). 1988// 1989// ILVOD interleaves the odd elements from each vector. 1990// 1991// It is possible to lower into ILVOD when the mask takes the form: 1992// <1, n+1, 3, n+3, 5, n+5, ...> 1993// where n is the number of elements in the vector. 1994// 1995// When undef's appear in the mask they are treated as if they were whatever 1996// value is necessary in order to fit the above form. 1997static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 1998 SmallVector<int, 16> Indices, 1999 SelectionDAG &DAG) { 2000 assert ((Indices.size() % 2) == 0); 2001 int WsIdx = 1; 2002 int WtIdx = ResTy.getVectorNumElements() + 1; 2003 2004 for (unsigned i = 0; i < Indices.size(); i += 2) { 2005 if (Indices[i] != -1 && Indices[i] != WsIdx) 2006 return SDValue(); 2007 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2008 return SDValue(); 2009 WsIdx += 2; 2010 WtIdx += 2; 2011 } 2012 2013 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 2014 Op->getOperand(1)); 2015} 2016 2017// Lower VECTOR_SHUFFLE into ILVL (if possible). 2018// 2019// ILVL interleaves consecutive elements from the left half of each vector. 2020// 2021// It is possible to lower into ILVL when the mask takes the form: 2022// <0, n, 1, n+1, 2, n+2, ...> 2023// where n is the number of elements in the vector. 2024// 2025// When undef's appear in the mask they are treated as if they were whatever 2026// value is necessary in order to fit the above form. 2027static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 2028 SmallVector<int, 16> Indices, 2029 SelectionDAG &DAG) { 2030 assert ((Indices.size() % 2) == 0); 2031 int WsIdx = 0; 2032 int WtIdx = ResTy.getVectorNumElements(); 2033 2034 for (unsigned i = 0; i < Indices.size(); i += 2) { 2035 if (Indices[i] != -1 && Indices[i] != WsIdx) 2036 return SDValue(); 2037 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2038 return SDValue(); 2039 WsIdx ++; 2040 WtIdx ++; 2041 } 2042 2043 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 2044 Op->getOperand(1)); 2045} 2046 2047// Lower VECTOR_SHUFFLE into ILVR (if possible). 2048// 2049// ILVR interleaves consecutive elements from the right half of each vector. 2050// 2051// It is possible to lower into ILVR when the mask takes the form: 2052// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 2053// where n is the number of elements in the vector and x is half n. 2054// 2055// When undef's appear in the mask they are treated as if they were whatever 2056// value is necessary in order to fit the above form. 2057static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 2058 SmallVector<int, 16> Indices, 2059 SelectionDAG &DAG) { 2060 assert ((Indices.size() % 2) == 0); 2061 unsigned NumElts = ResTy.getVectorNumElements(); 2062 int WsIdx = NumElts / 2; 2063 int WtIdx = NumElts + NumElts / 2; 2064 2065 for (unsigned i = 0; i < Indices.size(); i += 2) { 2066 if (Indices[i] != -1 && Indices[i] != WsIdx) 2067 return SDValue(); 2068 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2069 return SDValue(); 2070 WsIdx ++; 2071 WtIdx ++; 2072 } 2073 2074 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 2075 Op->getOperand(1)); 2076} 2077 2078// Lower VECTOR_SHUFFLE into PCKEV (if possible). 2079// 2080// PCKEV copies the even elements of each vector into the result vector. 2081// 2082// It is possible to lower into PCKEV when the mask takes the form: 2083// <0, 2, 4, ..., n, n+2, n+4, ...> 2084// where n is the number of elements in the vector. 2085// 2086// When undef's appear in the mask they are treated as if they were whatever 2087// value is necessary in order to fit the above form. 2088static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2089 SmallVector<int, 16> Indices, 2090 SelectionDAG &DAG) { 2091 assert ((Indices.size() % 2) == 0); 2092 int Idx = 0; 2093 2094 for (unsigned i = 0; i < Indices.size(); ++i) { 2095 if (Indices[i] != -1 && Indices[i] != Idx) 2096 return SDValue(); 2097 Idx += 2; 2098 } 2099 2100 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2101 Op->getOperand(1)); 2102} 2103 2104// Lower VECTOR_SHUFFLE into PCKOD (if possible). 2105// 2106// PCKOD copies the odd elements of each vector into the result vector. 2107// 2108// It is possible to lower into PCKOD when the mask takes the form: 2109// <1, 3, 5, ..., n+1, n+3, n+5, ...> 2110// where n is the number of elements in the vector. 2111// 2112// When undef's appear in the mask they are treated as if they were whatever 2113// value is necessary in order to fit the above form. 2114static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2115 SmallVector<int, 16> Indices, 2116 SelectionDAG &DAG) { 2117 assert ((Indices.size() % 2) == 0); 2118 int Idx = 1; 2119 2120 for (unsigned i = 0; i < Indices.size(); ++i) { 2121 if (Indices[i] != -1 && Indices[i] != Idx) 2122 return SDValue(); 2123 Idx += 2; 2124 } 2125 2126 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2127 Op->getOperand(1)); 2128} 2129 2130// Lower VECTOR_SHUFFLE into VSHF. 2131// 2132// This mostly consists of converting the shuffle indices in Indices into a 2133// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2134// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2135// if the type is v8i16 and all the indices are less than 8 then the second 2136// operand is unused and can be replaced with anything. We choose to replace it 2137// with the used operand since this reduces the number of instructions overall. 2138static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2139 SmallVector<int, 16> Indices, 2140 SelectionDAG &DAG) { 2141 SmallVector<SDValue, 16> Ops; 2142 SDValue Op0; 2143 SDValue Op1; 2144 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2145 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2146 bool Using1stVec = false; 2147 bool Using2ndVec = false; 2148 SDLoc DL(Op); 2149 int ResTyNumElts = ResTy.getVectorNumElements(); 2150 2151 for (int i = 0; i < ResTyNumElts; ++i) { 2152 // Idx == -1 means UNDEF 2153 int Idx = Indices[i]; 2154 2155 if (0 <= Idx && Idx < ResTyNumElts) 2156 Using1stVec = true; 2157 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2158 Using2ndVec = true; 2159 } 2160 2161 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2162 ++I) 2163 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2164 2165 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0], 2166 Ops.size()); 2167 2168 if (Using1stVec && Using2ndVec) { 2169 Op0 = Op->getOperand(0); 2170 Op1 = Op->getOperand(1); 2171 } else if (Using1stVec) 2172 Op0 = Op1 = Op->getOperand(0); 2173 else if (Using2ndVec) 2174 Op0 = Op1 = Op->getOperand(1); 2175 else 2176 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2177 2178 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1); 2179} 2180 2181// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2182// indices in the shuffle. 2183SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2184 SelectionDAG &DAG) const { 2185 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2186 EVT ResTy = Op->getValueType(0); 2187 2188 if (!ResTy.is128BitVector()) 2189 return SDValue(); 2190 2191 int ResTyNumElts = ResTy.getVectorNumElements(); 2192 SmallVector<int, 16> Indices; 2193 2194 for (int i = 0; i < ResTyNumElts; ++i) 2195 Indices.push_back(Node->getMaskElt(i)); 2196 2197 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2198 if (Result.getNode()) 2199 return Result; 2200 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2201 if (Result.getNode()) 2202 return Result; 2203 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2204 if (Result.getNode()) 2205 return Result; 2206 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2207 if (Result.getNode()) 2208 return Result; 2209 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2210 if (Result.getNode()) 2211 return Result; 2212 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2213 if (Result.getNode()) 2214 return Result; 2215 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2216 if (Result.getNode()) 2217 return Result; 2218 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2219} 2220 2221MachineBasicBlock * MipsSETargetLowering:: 2222emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2223 // $bb: 2224 // bposge32_pseudo $vr0 2225 // => 2226 // $bb: 2227 // bposge32 $tbb 2228 // $fbb: 2229 // li $vr2, 0 2230 // b $sink 2231 // $tbb: 2232 // li $vr1, 1 2233 // $sink: 2234 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2235 2236 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2237 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2238 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2239 DebugLoc DL = MI->getDebugLoc(); 2240 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2241 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2242 MachineFunction *F = BB->getParent(); 2243 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2244 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2245 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2246 F->insert(It, FBB); 2247 F->insert(It, TBB); 2248 F->insert(It, Sink); 2249 2250 // Transfer the remainder of BB and its successor edges to Sink. 2251 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2252 BB->end()); 2253 Sink->transferSuccessorsAndUpdatePHIs(BB); 2254 2255 // Add successors. 2256 BB->addSuccessor(FBB); 2257 BB->addSuccessor(TBB); 2258 FBB->addSuccessor(Sink); 2259 TBB->addSuccessor(Sink); 2260 2261 // Insert the real bposge32 instruction to $BB. 2262 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2263 2264 // Fill $FBB. 2265 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2266 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2267 .addReg(Mips::ZERO).addImm(0); 2268 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2269 2270 // Fill $TBB. 2271 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2272 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2273 .addReg(Mips::ZERO).addImm(1); 2274 2275 // Insert phi function to $Sink. 2276 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2277 MI->getOperand(0).getReg()) 2278 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2279 2280 MI->eraseFromParent(); // The pseudo instruction is gone now. 2281 return Sink; 2282} 2283 2284MachineBasicBlock * MipsSETargetLowering:: 2285emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2286 unsigned BranchOp) const{ 2287 // $bb: 2288 // vany_nonzero $rd, $ws 2289 // => 2290 // $bb: 2291 // bnz.b $ws, $tbb 2292 // b $fbb 2293 // $fbb: 2294 // li $rd1, 0 2295 // b $sink 2296 // $tbb: 2297 // li $rd2, 1 2298 // $sink: 2299 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2300 2301 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2302 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2303 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2304 DebugLoc DL = MI->getDebugLoc(); 2305 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2306 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2307 MachineFunction *F = BB->getParent(); 2308 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2309 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2310 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2311 F->insert(It, FBB); 2312 F->insert(It, TBB); 2313 F->insert(It, Sink); 2314 2315 // Transfer the remainder of BB and its successor edges to Sink. 2316 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2317 BB->end()); 2318 Sink->transferSuccessorsAndUpdatePHIs(BB); 2319 2320 // Add successors. 2321 BB->addSuccessor(FBB); 2322 BB->addSuccessor(TBB); 2323 FBB->addSuccessor(Sink); 2324 TBB->addSuccessor(Sink); 2325 2326 // Insert the real bnz.b instruction to $BB. 2327 BuildMI(BB, DL, TII->get(BranchOp)) 2328 .addReg(MI->getOperand(1).getReg()) 2329 .addMBB(TBB); 2330 2331 // Fill $FBB. 2332 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2333 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2334 .addReg(Mips::ZERO).addImm(0); 2335 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2336 2337 // Fill $TBB. 2338 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2339 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2340 .addReg(Mips::ZERO).addImm(1); 2341 2342 // Insert phi function to $Sink. 2343 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2344 MI->getOperand(0).getReg()) 2345 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2346 2347 MI->eraseFromParent(); // The pseudo instruction is gone now. 2348 return Sink; 2349} 2350 2351// Emit the COPY_FW pseudo instruction. 2352// 2353// copy_fw_pseudo $fd, $ws, n 2354// => 2355// copy_u_w $rt, $ws, $n 2356// mtc1 $rt, $fd 2357// 2358// When n is zero, the equivalent operation can be performed with (potentially) 2359// zero instructions due to register overlaps. This optimization is never valid 2360// for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2361MachineBasicBlock * MipsSETargetLowering:: 2362emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2363 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2364 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2365 DebugLoc DL = MI->getDebugLoc(); 2366 unsigned Fd = MI->getOperand(0).getReg(); 2367 unsigned Ws = MI->getOperand(1).getReg(); 2368 unsigned Lane = MI->getOperand(2).getImm(); 2369 2370 if (Lane == 0) 2371 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2372 else { 2373 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2374 2375 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); 2376 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2377 } 2378 2379 MI->eraseFromParent(); // The pseudo instruction is gone now. 2380 return BB; 2381} 2382 2383// Emit the COPY_FD pseudo instruction. 2384// 2385// copy_fd_pseudo $fd, $ws, n 2386// => 2387// splati.d $wt, $ws, $n 2388// copy $fd, $wt:sub_64 2389// 2390// When n is zero, the equivalent operation can be performed with (potentially) 2391// zero instructions due to register overlaps. This optimization is always 2392// valid because FR=1 mode which is the only supported mode in MSA. 2393MachineBasicBlock * MipsSETargetLowering:: 2394emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2395 assert(Subtarget->isFP64bit()); 2396 2397 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2398 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2399 unsigned Fd = MI->getOperand(0).getReg(); 2400 unsigned Ws = MI->getOperand(1).getReg(); 2401 unsigned Lane = MI->getOperand(2).getImm() * 2; 2402 DebugLoc DL = MI->getDebugLoc(); 2403 2404 if (Lane == 0) 2405 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2406 else { 2407 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2408 2409 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2410 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2411 } 2412 2413 MI->eraseFromParent(); // The pseudo instruction is gone now. 2414 return BB; 2415} 2416 2417// Emit the INSERT_FW pseudo instruction. 2418// 2419// insert_fw_pseudo $wd, $wd_in, $n, $fs 2420// => 2421// subreg_to_reg $wt:sub_lo, $fs 2422// insve_w $wd[$n], $wd_in, $wt[0] 2423MachineBasicBlock * 2424MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, 2425 MachineBasicBlock *BB) const { 2426 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2427 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2428 DebugLoc DL = MI->getDebugLoc(); 2429 unsigned Wd = MI->getOperand(0).getReg(); 2430 unsigned Wd_in = MI->getOperand(1).getReg(); 2431 unsigned Lane = MI->getOperand(2).getImm(); 2432 unsigned Fs = MI->getOperand(3).getReg(); 2433 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2434 2435 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2436 .addImm(0) 2437 .addReg(Fs) 2438 .addImm(Mips::sub_lo); 2439 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2440 .addReg(Wd_in) 2441 .addImm(Lane) 2442 .addReg(Wt); 2443 2444 MI->eraseFromParent(); // The pseudo instruction is gone now. 2445 return BB; 2446} 2447 2448// Emit the INSERT_FD pseudo instruction. 2449// 2450// insert_fd_pseudo $wd, $fs, n 2451// => 2452// subreg_to_reg $wt:sub_64, $fs 2453// insve_d $wd[$n], $wd_in, $wt[0] 2454MachineBasicBlock * 2455MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, 2456 MachineBasicBlock *BB) const { 2457 assert(Subtarget->isFP64bit()); 2458 2459 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2460 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2461 DebugLoc DL = MI->getDebugLoc(); 2462 unsigned Wd = MI->getOperand(0).getReg(); 2463 unsigned Wd_in = MI->getOperand(1).getReg(); 2464 unsigned Lane = MI->getOperand(2).getImm(); 2465 unsigned Fs = MI->getOperand(3).getReg(); 2466 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2467 2468 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2469 .addImm(0) 2470 .addReg(Fs) 2471 .addImm(Mips::sub_64); 2472 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2473 .addReg(Wd_in) 2474 .addImm(Lane) 2475 .addReg(Wt); 2476 2477 MI->eraseFromParent(); // The pseudo instruction is gone now. 2478 return BB; 2479} 2480 2481// Emit the FILL_FW pseudo instruction. 2482// 2483// fill_fw_pseudo $wd, $fs 2484// => 2485// implicit_def $wt1 2486// insert_subreg $wt2:subreg_lo, $wt1, $fs 2487// splati.w $wd, $wt2[0] 2488MachineBasicBlock * 2489MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, 2490 MachineBasicBlock *BB) const { 2491 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2492 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2493 DebugLoc DL = MI->getDebugLoc(); 2494 unsigned Wd = MI->getOperand(0).getReg(); 2495 unsigned Fs = MI->getOperand(1).getReg(); 2496 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2497 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2498 2499 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2500 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2501 .addReg(Wt1) 2502 .addReg(Fs) 2503 .addImm(Mips::sub_lo); 2504 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); 2505 2506 MI->eraseFromParent(); // The pseudo instruction is gone now. 2507 return BB; 2508} 2509 2510// Emit the FILL_FD pseudo instruction. 2511// 2512// fill_fd_pseudo $wd, $fs 2513// => 2514// implicit_def $wt1 2515// insert_subreg $wt2:subreg_64, $wt1, $fs 2516// splati.d $wd, $wt2[0] 2517MachineBasicBlock * 2518MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, 2519 MachineBasicBlock *BB) const { 2520 assert(Subtarget->isFP64bit()); 2521 2522 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2523 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2524 DebugLoc DL = MI->getDebugLoc(); 2525 unsigned Wd = MI->getOperand(0).getReg(); 2526 unsigned Fs = MI->getOperand(1).getReg(); 2527 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2528 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2529 2530 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2531 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2532 .addReg(Wt1) 2533 .addReg(Fs) 2534 .addImm(Mips::sub_64); 2535 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); 2536 2537 MI->eraseFromParent(); // The pseudo instruction is gone now. 2538 return BB; 2539} 2540 2541// Emit the FEXP2_W_1 pseudo instructions. 2542// 2543// fexp2_w_1_pseudo $wd, $wt 2544// => 2545// ldi.w $ws, 1 2546// fexp2.w $wd, $ws, $wt 2547MachineBasicBlock * 2548MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, 2549 MachineBasicBlock *BB) const { 2550 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2551 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2552 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; 2553 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2554 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2555 DebugLoc DL = MI->getDebugLoc(); 2556 2557 // Splat 1.0 into a vector 2558 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); 2559 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); 2560 2561 // Emit 1.0 * fexp2(Wt) 2562 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) 2563 .addReg(Ws2) 2564 .addReg(MI->getOperand(1).getReg()); 2565 2566 MI->eraseFromParent(); // The pseudo instruction is gone now. 2567 return BB; 2568} 2569 2570// Emit the FEXP2_D_1 pseudo instructions. 2571// 2572// fexp2_d_1_pseudo $wd, $wt 2573// => 2574// ldi.d $ws, 1 2575// fexp2.d $wd, $ws, $wt 2576MachineBasicBlock * 2577MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, 2578 MachineBasicBlock *BB) const { 2579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2580 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2581 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; 2582 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2583 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2584 DebugLoc DL = MI->getDebugLoc(); 2585 2586 // Splat 1.0 into a vector 2587 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); 2588 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); 2589 2590 // Emit 1.0 * fexp2(Wt) 2591 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) 2592 .addReg(Ws2) 2593 .addReg(MI->getOperand(1).getReg()); 2594 2595 MI->eraseFromParent(); // The pseudo instruction is gone now. 2596 return BB; 2597} 2598