MipsSEISelLowering.cpp revision d593a77b4cf3b81cd657e351e47cad25ee037ce1 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Support/CommandLine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21using namespace llvm;
22
23static cl::opt<bool>
24EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
25                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
26
27MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
28  : MipsTargetLowering(TM) {
29  // Set up the register classes
30  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
31
32  if (HasMips64)
33    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
34
35  if (Subtarget->hasDSP()) {
36    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
37
38    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
39      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
40
41      // Expand all builtin opcodes.
42      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
43        setOperationAction(Opc, VecTys[i], Expand);
44
45      setOperationAction(ISD::LOAD, VecTys[i], Legal);
46      setOperationAction(ISD::STORE, VecTys[i], Legal);
47      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
48    }
49  }
50
51  if (!TM.Options.UseSoftFloat) {
52    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
53
54    // When dealing with single precision only, use libcalls
55    if (!Subtarget->isSingleFloat()) {
56      if (HasMips64)
57        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
58      else
59        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
60    }
61  }
62
63  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
64  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
65  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
66  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
67
68  if (HasMips64)
69    setOperationAction(ISD::MUL,              MVT::i64, Custom);
70
71  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
72  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
73  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
74  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
75  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
76  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
77  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
78  setOperationAction(ISD::STORE,              MVT::i32, Custom);
79
80  setTargetDAGCombine(ISD::ADDE);
81  setTargetDAGCombine(ISD::SUBE);
82
83  computeRegisterProperties();
84}
85
86const MipsTargetLowering *
87llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
88  return new MipsSETargetLowering(TM);
89}
90
91
92bool
93MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
94  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
95
96  switch (SVT) {
97  case MVT::i64:
98  case MVT::i32:
99    if (Fast)
100      *Fast = true;
101    return true;
102  default:
103    return false;
104  }
105}
106
107SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
108                                             SelectionDAG &DAG) const {
109  switch(Op.getOpcode()) {
110  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
111  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
112  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
113  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
114  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
115  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
116  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
117  }
118
119  return MipsTargetLowering::LowerOperation(Op, DAG);
120}
121
122// selectMADD -
123// Transforms a subgraph in CurDAG if the following pattern is found:
124//  (addc multLo, Lo0), (adde multHi, Hi0),
125// where,
126//  multHi/Lo: product of multiplication
127//  Lo0: initial value of Lo register
128//  Hi0: initial value of Hi register
129// Return true if pattern matching was successful.
130static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
131  // ADDENode's second operand must be a flag output of an ADDC node in order
132  // for the matching to be successful.
133  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
134
135  if (ADDCNode->getOpcode() != ISD::ADDC)
136    return false;
137
138  SDValue MultHi = ADDENode->getOperand(0);
139  SDValue MultLo = ADDCNode->getOperand(0);
140  SDNode *MultNode = MultHi.getNode();
141  unsigned MultOpc = MultHi.getOpcode();
142
143  // MultHi and MultLo must be generated by the same node,
144  if (MultLo.getNode() != MultNode)
145    return false;
146
147  // and it must be a multiplication.
148  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
149    return false;
150
151  // MultLo amd MultHi must be the first and second output of MultNode
152  // respectively.
153  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
154    return false;
155
156  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
157  // of the values of MultNode, in which case MultNode will be removed in later
158  // phases.
159  // If there exist users other than ADDENode or ADDCNode, this function returns
160  // here, which will result in MultNode being mapped to a single MULT
161  // instruction node rather than a pair of MULT and MADD instructions being
162  // produced.
163  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
164    return false;
165
166  SDValue Chain = CurDAG->getEntryNode();
167  DebugLoc DL = ADDENode->getDebugLoc();
168
169  // Initialize accumulator.
170  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
171                                  ADDCNode->getOperand(1),
172                                  ADDENode->getOperand(1));
173
174  // create MipsMAdd(u) node
175  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
176
177  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
178                                 MultNode->getOperand(0),// Factor 0
179                                 MultNode->getOperand(1),// Factor 1
180                                 ACCIn);
181
182  // replace uses of adde and addc here
183  if (!SDValue(ADDCNode, 0).use_empty()) {
184    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
185    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
186                                    LoIdx);
187    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
188  }
189  if (!SDValue(ADDENode, 0).use_empty()) {
190    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
191    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
192                                    HiIdx);
193    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
194  }
195
196  return true;
197}
198
199// selectMSUB -
200// Transforms a subgraph in CurDAG if the following pattern is found:
201//  (addc Lo0, multLo), (sube Hi0, multHi),
202// where,
203//  multHi/Lo: product of multiplication
204//  Lo0: initial value of Lo register
205//  Hi0: initial value of Hi register
206// Return true if pattern matching was successful.
207static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
208  // SUBENode's second operand must be a flag output of an SUBC node in order
209  // for the matching to be successful.
210  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
211
212  if (SUBCNode->getOpcode() != ISD::SUBC)
213    return false;
214
215  SDValue MultHi = SUBENode->getOperand(1);
216  SDValue MultLo = SUBCNode->getOperand(1);
217  SDNode *MultNode = MultHi.getNode();
218  unsigned MultOpc = MultHi.getOpcode();
219
220  // MultHi and MultLo must be generated by the same node,
221  if (MultLo.getNode() != MultNode)
222    return false;
223
224  // and it must be a multiplication.
225  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
226    return false;
227
228  // MultLo amd MultHi must be the first and second output of MultNode
229  // respectively.
230  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
231    return false;
232
233  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
234  // of the values of MultNode, in which case MultNode will be removed in later
235  // phases.
236  // If there exist users other than SUBENode or SUBCNode, this function returns
237  // here, which will result in MultNode being mapped to a single MULT
238  // instruction node rather than a pair of MULT and MSUB instructions being
239  // produced.
240  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
241    return false;
242
243  SDValue Chain = CurDAG->getEntryNode();
244  DebugLoc DL = SUBENode->getDebugLoc();
245
246  // Initialize accumulator.
247  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
248                                  SUBCNode->getOperand(0),
249                                  SUBENode->getOperand(0));
250
251  // create MipsSub(u) node
252  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
253
254  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
255                                 MultNode->getOperand(0),// Factor 0
256                                 MultNode->getOperand(1),// Factor 1
257                                 ACCIn);
258
259  // replace uses of sube and subc here
260  if (!SDValue(SUBCNode, 0).use_empty()) {
261    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
262    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
263                                    LoIdx);
264    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
265  }
266  if (!SDValue(SUBENode, 0).use_empty()) {
267    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
268    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
269                                    HiIdx);
270    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
271  }
272
273  return true;
274}
275
276static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
277                                  TargetLowering::DAGCombinerInfo &DCI,
278                                  const MipsSubtarget *Subtarget) {
279  if (DCI.isBeforeLegalize())
280    return SDValue();
281
282  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
283      selectMADD(N, &DAG))
284    return SDValue(N, 0);
285
286  return SDValue();
287}
288
289static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
290                                  TargetLowering::DAGCombinerInfo &DCI,
291                                  const MipsSubtarget *Subtarget) {
292  if (DCI.isBeforeLegalize())
293    return SDValue();
294
295  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
296      selectMSUB(N, &DAG))
297    return SDValue(N, 0);
298
299  return SDValue();
300}
301
302SDValue
303MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
304  SelectionDAG &DAG = DCI.DAG;
305
306  switch (N->getOpcode()) {
307  case ISD::ADDE:
308    return performADDECombine(N, DAG, DCI, Subtarget);
309  case ISD::SUBE:
310    return performSUBECombine(N, DAG, DCI, Subtarget);
311  default:
312    return MipsTargetLowering::PerformDAGCombine(N, DCI);
313  }
314}
315
316MachineBasicBlock *
317MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
318                                                  MachineBasicBlock *BB) const {
319  switch (MI->getOpcode()) {
320  default:
321    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
322  case Mips::BPOSGE32_PSEUDO:
323    return emitBPOSGE32(MI, BB);
324  }
325}
326
327bool MipsSETargetLowering::
328isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
329                                  unsigned NextStackOffset,
330                                  const MipsFunctionInfo& FI) const {
331  if (!EnableMipsTailCalls)
332    return false;
333
334  // Return false if either the callee or caller has a byval argument.
335  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
336    return false;
337
338  // Return true if the callee's argument area is no larger than the
339  // caller's.
340  return NextStackOffset <= FI.getIncomingArgSize();
341}
342
343void MipsSETargetLowering::
344getOpndList(SmallVectorImpl<SDValue> &Ops,
345            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
346            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
347            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
348  // T9 should contain the address of the callee function if
349  // -reloction-model=pic or it is an indirect call.
350  if (IsPICCall || !GlobalOrExternal) {
351    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
352    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
353  } else
354    Ops.push_back(Callee);
355
356  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
357                                  InternalLinkage, CLI, Callee, Chain);
358}
359
360SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
361                                          bool HasLo, bool HasHi,
362                                          SelectionDAG &DAG) const {
363  EVT Ty = Op.getOperand(0).getValueType();
364  DebugLoc DL = Op.getDebugLoc();
365  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
366                             Op.getOperand(0), Op.getOperand(1));
367  SDValue Lo, Hi;
368
369  if (HasLo)
370    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
371                     DAG.getConstant(Mips::sub_lo, MVT::i32));
372  if (HasHi)
373    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
374                     DAG.getConstant(Mips::sub_hi, MVT::i32));
375
376  if (!HasLo || !HasHi)
377    return HasLo ? Lo : Hi;
378
379  SDValue Vals[] = { Lo, Hi };
380  return DAG.getMergeValues(Vals, 2, DL);
381}
382
383MachineBasicBlock * MipsSETargetLowering::
384emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
385  // $bb:
386  //  bposge32_pseudo $vr0
387  //  =>
388  // $bb:
389  //  bposge32 $tbb
390  // $fbb:
391  //  li $vr2, 0
392  //  b $sink
393  // $tbb:
394  //  li $vr1, 1
395  // $sink:
396  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
397
398  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
399  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
400  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
401  DebugLoc DL = MI->getDebugLoc();
402  const BasicBlock *LLVM_BB = BB->getBasicBlock();
403  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
404  MachineFunction *F = BB->getParent();
405  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
406  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
407  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
408  F->insert(It, FBB);
409  F->insert(It, TBB);
410  F->insert(It, Sink);
411
412  // Transfer the remainder of BB and its successor edges to Sink.
413  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
414               BB->end());
415  Sink->transferSuccessorsAndUpdatePHIs(BB);
416
417  // Add successors.
418  BB->addSuccessor(FBB);
419  BB->addSuccessor(TBB);
420  FBB->addSuccessor(Sink);
421  TBB->addSuccessor(Sink);
422
423  // Insert the real bposge32 instruction to $BB.
424  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
425
426  // Fill $FBB.
427  unsigned VR2 = RegInfo.createVirtualRegister(RC);
428  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
429    .addReg(Mips::ZERO).addImm(0);
430  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
431
432  // Fill $TBB.
433  unsigned VR1 = RegInfo.createVirtualRegister(RC);
434  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
435    .addReg(Mips::ZERO).addImm(1);
436
437  // Insert phi function to $Sink.
438  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
439          MI->getOperand(0).getReg())
440    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
441
442  MI->eraseFromParent();   // The pseudo instruction is gone now.
443  return Sink;
444}
445