MipsSEISelLowering.cpp revision da521cc1cc733ee1c27b00e4c0e365c8b702e2e0 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93  }
94
95  if (!Subtarget->mipsSEUsesSoftFloat()) {
96    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
97
98    // When dealing with single precision only, use libcalls
99    if (!Subtarget->isSingleFloat()) {
100      if (Subtarget->isFP64bit())
101        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
102      else
103        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
104    }
105  }
106
107  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
108  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
109  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
110  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
111
112  if (HasMips64) {
113    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
114    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
115    setOperationAction(ISD::MUL,              MVT::i64, Custom);
116  }
117
118  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
119  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
120
121  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
122  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
123  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
124  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
125  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
126  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
127  setOperationAction(ISD::STORE,              MVT::i32, Custom);
128
129  setTargetDAGCombine(ISD::ADDE);
130  setTargetDAGCombine(ISD::SUBE);
131  setTargetDAGCombine(ISD::MUL);
132
133  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
136
137  if (NoDPLoadStore) {
138    setOperationAction(ISD::LOAD, MVT::f64, Custom);
139    setOperationAction(ISD::STORE, MVT::f64, Custom);
140  }
141
142  computeRegisterProperties();
143}
144
145const MipsTargetLowering *
146llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
147  return new MipsSETargetLowering(TM);
148}
149
150// Enable MSA support for the given integer type and Register class.
151void MipsSETargetLowering::
152addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
153  addRegisterClass(Ty, RC);
154
155  // Expand all builtin opcodes.
156  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
157    setOperationAction(Opc, Ty, Expand);
158
159  setOperationAction(ISD::BITCAST, Ty, Legal);
160  setOperationAction(ISD::LOAD, Ty, Legal);
161  setOperationAction(ISD::STORE, Ty, Legal);
162  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
163
164  setOperationAction(ISD::ADD, Ty, Legal);
165  setOperationAction(ISD::CTLZ, Ty, Legal);
166  setOperationAction(ISD::MUL, Ty, Legal);
167  setOperationAction(ISD::SDIV, Ty, Legal);
168  setOperationAction(ISD::SHL, Ty, Legal);
169  setOperationAction(ISD::SRA, Ty, Legal);
170  setOperationAction(ISD::SRL, Ty, Legal);
171  setOperationAction(ISD::SUB, Ty, Legal);
172  setOperationAction(ISD::UDIV, Ty, Legal);
173}
174
175// Enable MSA support for the given floating-point type and Register class.
176void MipsSETargetLowering::
177addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
178  addRegisterClass(Ty, RC);
179
180  // Expand all builtin opcodes.
181  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
182    setOperationAction(Opc, Ty, Expand);
183
184  setOperationAction(ISD::LOAD, Ty, Legal);
185  setOperationAction(ISD::STORE, Ty, Legal);
186  setOperationAction(ISD::BITCAST, Ty, Legal);
187
188  if (Ty != MVT::v8f16) {
189    setOperationAction(ISD::FADD,  Ty, Legal);
190    setOperationAction(ISD::FDIV,  Ty, Legal);
191    setOperationAction(ISD::FLOG2, Ty, Legal);
192    setOperationAction(ISD::FMUL,  Ty, Legal);
193    setOperationAction(ISD::FRINT, Ty, Legal);
194    setOperationAction(ISD::FSQRT, Ty, Legal);
195    setOperationAction(ISD::FSUB,  Ty, Legal);
196  }
197}
198
199bool
200MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
201  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
202
203  switch (SVT) {
204  case MVT::i64:
205  case MVT::i32:
206    if (Fast)
207      *Fast = true;
208    return true;
209  default:
210    return false;
211  }
212}
213
214SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
215                                             SelectionDAG &DAG) const {
216  switch(Op.getOpcode()) {
217  case ISD::LOAD:  return lowerLOAD(Op, DAG);
218  case ISD::STORE: return lowerSTORE(Op, DAG);
219  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
220  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
221  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
222  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
223  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
224  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
225  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
226                                          DAG);
227  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
228  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
229  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
230  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
231  }
232
233  return MipsTargetLowering::LowerOperation(Op, DAG);
234}
235
236// selectMADD -
237// Transforms a subgraph in CurDAG if the following pattern is found:
238//  (addc multLo, Lo0), (adde multHi, Hi0),
239// where,
240//  multHi/Lo: product of multiplication
241//  Lo0: initial value of Lo register
242//  Hi0: initial value of Hi register
243// Return true if pattern matching was successful.
244static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
245  // ADDENode's second operand must be a flag output of an ADDC node in order
246  // for the matching to be successful.
247  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
248
249  if (ADDCNode->getOpcode() != ISD::ADDC)
250    return false;
251
252  SDValue MultHi = ADDENode->getOperand(0);
253  SDValue MultLo = ADDCNode->getOperand(0);
254  SDNode *MultNode = MultHi.getNode();
255  unsigned MultOpc = MultHi.getOpcode();
256
257  // MultHi and MultLo must be generated by the same node,
258  if (MultLo.getNode() != MultNode)
259    return false;
260
261  // and it must be a multiplication.
262  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
263    return false;
264
265  // MultLo amd MultHi must be the first and second output of MultNode
266  // respectively.
267  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
268    return false;
269
270  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
271  // of the values of MultNode, in which case MultNode will be removed in later
272  // phases.
273  // If there exist users other than ADDENode or ADDCNode, this function returns
274  // here, which will result in MultNode being mapped to a single MULT
275  // instruction node rather than a pair of MULT and MADD instructions being
276  // produced.
277  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
278    return false;
279
280  SDLoc DL(ADDENode);
281
282  // Initialize accumulator.
283  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
284                                  ADDCNode->getOperand(1),
285                                  ADDENode->getOperand(1));
286
287  // create MipsMAdd(u) node
288  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
289
290  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
291                                 MultNode->getOperand(0),// Factor 0
292                                 MultNode->getOperand(1),// Factor 1
293                                 ACCIn);
294
295  // replace uses of adde and addc here
296  if (!SDValue(ADDCNode, 0).use_empty()) {
297    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
298    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
299                                    LoIdx);
300    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
301  }
302  if (!SDValue(ADDENode, 0).use_empty()) {
303    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
304    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
305                                    HiIdx);
306    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
307  }
308
309  return true;
310}
311
312// selectMSUB -
313// Transforms a subgraph in CurDAG if the following pattern is found:
314//  (addc Lo0, multLo), (sube Hi0, multHi),
315// where,
316//  multHi/Lo: product of multiplication
317//  Lo0: initial value of Lo register
318//  Hi0: initial value of Hi register
319// Return true if pattern matching was successful.
320static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
321  // SUBENode's second operand must be a flag output of an SUBC node in order
322  // for the matching to be successful.
323  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
324
325  if (SUBCNode->getOpcode() != ISD::SUBC)
326    return false;
327
328  SDValue MultHi = SUBENode->getOperand(1);
329  SDValue MultLo = SUBCNode->getOperand(1);
330  SDNode *MultNode = MultHi.getNode();
331  unsigned MultOpc = MultHi.getOpcode();
332
333  // MultHi and MultLo must be generated by the same node,
334  if (MultLo.getNode() != MultNode)
335    return false;
336
337  // and it must be a multiplication.
338  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
339    return false;
340
341  // MultLo amd MultHi must be the first and second output of MultNode
342  // respectively.
343  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
344    return false;
345
346  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
347  // of the values of MultNode, in which case MultNode will be removed in later
348  // phases.
349  // If there exist users other than SUBENode or SUBCNode, this function returns
350  // here, which will result in MultNode being mapped to a single MULT
351  // instruction node rather than a pair of MULT and MSUB instructions being
352  // produced.
353  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
354    return false;
355
356  SDLoc DL(SUBENode);
357
358  // Initialize accumulator.
359  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
360                                  SUBCNode->getOperand(0),
361                                  SUBENode->getOperand(0));
362
363  // create MipsSub(u) node
364  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
365
366  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
367                                 MultNode->getOperand(0),// Factor 0
368                                 MultNode->getOperand(1),// Factor 1
369                                 ACCIn);
370
371  // replace uses of sube and subc here
372  if (!SDValue(SUBCNode, 0).use_empty()) {
373    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
374    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
375                                    LoIdx);
376    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
377  }
378  if (!SDValue(SUBENode, 0).use_empty()) {
379    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
380    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
381                                    HiIdx);
382    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
383  }
384
385  return true;
386}
387
388static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
389                                  TargetLowering::DAGCombinerInfo &DCI,
390                                  const MipsSubtarget *Subtarget) {
391  if (DCI.isBeforeLegalize())
392    return SDValue();
393
394  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
395      selectMADD(N, &DAG))
396    return SDValue(N, 0);
397
398  return SDValue();
399}
400
401static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
402                                  TargetLowering::DAGCombinerInfo &DCI,
403                                  const MipsSubtarget *Subtarget) {
404  if (DCI.isBeforeLegalize())
405    return SDValue();
406
407  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
408      selectMSUB(N, &DAG))
409    return SDValue(N, 0);
410
411  return SDValue();
412}
413
414static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
415                            EVT ShiftTy, SelectionDAG &DAG) {
416  // Clear the upper (64 - VT.sizeInBits) bits.
417  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
418
419  // Return 0.
420  if (C == 0)
421    return DAG.getConstant(0, VT);
422
423  // Return x.
424  if (C == 1)
425    return X;
426
427  // If c is power of 2, return (shl x, log2(c)).
428  if (isPowerOf2_64(C))
429    return DAG.getNode(ISD::SHL, DL, VT, X,
430                       DAG.getConstant(Log2_64(C), ShiftTy));
431
432  unsigned Log2Ceil = Log2_64_Ceil(C);
433  uint64_t Floor = 1LL << Log2_64(C);
434  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
435
436  // If |c - floor_c| <= |c - ceil_c|,
437  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
438  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
439  if (C - Floor <= Ceil - C) {
440    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
441    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
442    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
443  }
444
445  // If |c - floor_c| > |c - ceil_c|,
446  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
447  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
448  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
449  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
450}
451
452static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
453                                 const TargetLowering::DAGCombinerInfo &DCI,
454                                 const MipsSETargetLowering *TL) {
455  EVT VT = N->getValueType(0);
456
457  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
458    if (!VT.isVector())
459      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
460                          VT, TL->getScalarShiftAmountTy(VT), DAG);
461
462  return SDValue(N, 0);
463}
464
465static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
466                                      SelectionDAG &DAG,
467                                      const MipsSubtarget *Subtarget) {
468  // See if this is a vector splat immediate node.
469  APInt SplatValue, SplatUndef;
470  unsigned SplatBitSize;
471  bool HasAnyUndefs;
472  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
473  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
474
475  if (!BV ||
476      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
477                           EltSize, !Subtarget->isLittle()) ||
478      (SplatBitSize != EltSize) ||
479      (SplatValue.getZExtValue() >= EltSize))
480    return SDValue();
481
482  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
483                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
484}
485
486static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
487                                 TargetLowering::DAGCombinerInfo &DCI,
488                                 const MipsSubtarget *Subtarget) {
489  EVT Ty = N->getValueType(0);
490
491  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
492    return SDValue();
493
494  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
495}
496
497static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
498                                 TargetLowering::DAGCombinerInfo &DCI,
499                                 const MipsSubtarget *Subtarget) {
500  EVT Ty = N->getValueType(0);
501
502  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
503    return SDValue();
504
505  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
506}
507
508
509static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
510                                 TargetLowering::DAGCombinerInfo &DCI,
511                                 const MipsSubtarget *Subtarget) {
512  EVT Ty = N->getValueType(0);
513
514  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
515    return SDValue();
516
517  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
518}
519
520static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
521  bool IsV216 = (Ty == MVT::v2i16);
522
523  switch (CC) {
524  case ISD::SETEQ:
525  case ISD::SETNE:  return true;
526  case ISD::SETLT:
527  case ISD::SETLE:
528  case ISD::SETGT:
529  case ISD::SETGE:  return IsV216;
530  case ISD::SETULT:
531  case ISD::SETULE:
532  case ISD::SETUGT:
533  case ISD::SETUGE: return !IsV216;
534  default:          return false;
535  }
536}
537
538static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
539  EVT Ty = N->getValueType(0);
540
541  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
542    return SDValue();
543
544  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
545    return SDValue();
546
547  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
548                     N->getOperand(1), N->getOperand(2));
549}
550
551static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
552  EVT Ty = N->getValueType(0);
553
554  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
555    return SDValue();
556
557  SDValue SetCC = N->getOperand(0);
558
559  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
560    return SDValue();
561
562  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
563                     SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
564                     N->getOperand(2), SetCC.getOperand(2));
565}
566
567SDValue
568MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
569  SelectionDAG &DAG = DCI.DAG;
570  SDValue Val;
571
572  switch (N->getOpcode()) {
573  case ISD::ADDE:
574    return performADDECombine(N, DAG, DCI, Subtarget);
575  case ISD::SUBE:
576    return performSUBECombine(N, DAG, DCI, Subtarget);
577  case ISD::MUL:
578    return performMULCombine(N, DAG, DCI, this);
579  case ISD::SHL:
580    return performSHLCombine(N, DAG, DCI, Subtarget);
581  case ISD::SRA:
582    return performSRACombine(N, DAG, DCI, Subtarget);
583  case ISD::SRL:
584    return performSRLCombine(N, DAG, DCI, Subtarget);
585  case ISD::VSELECT:
586    return performVSELECTCombine(N, DAG);
587  case ISD::SETCC: {
588    Val = performSETCCCombine(N, DAG);
589    break;
590  }
591  }
592
593  if (Val.getNode())
594    return Val;
595
596  return MipsTargetLowering::PerformDAGCombine(N, DCI);
597}
598
599MachineBasicBlock *
600MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
601                                                  MachineBasicBlock *BB) const {
602  switch (MI->getOpcode()) {
603  default:
604    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
605  case Mips::BPOSGE32_PSEUDO:
606    return emitBPOSGE32(MI, BB);
607  case Mips::SNZ_B_PSEUDO:
608    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
609  case Mips::SNZ_H_PSEUDO:
610    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
611  case Mips::SNZ_W_PSEUDO:
612    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
613  case Mips::SNZ_D_PSEUDO:
614    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
615  case Mips::SNZ_V_PSEUDO:
616    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
617  case Mips::SZ_B_PSEUDO:
618    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
619  case Mips::SZ_H_PSEUDO:
620    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
621  case Mips::SZ_W_PSEUDO:
622    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
623  case Mips::SZ_D_PSEUDO:
624    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
625  case Mips::SZ_V_PSEUDO:
626    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
627  }
628}
629
630bool MipsSETargetLowering::
631isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
632                                  unsigned NextStackOffset,
633                                  const MipsFunctionInfo& FI) const {
634  if (!EnableMipsTailCalls)
635    return false;
636
637  // Return false if either the callee or caller has a byval argument.
638  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
639    return false;
640
641  // Return true if the callee's argument area is no larger than the
642  // caller's.
643  return NextStackOffset <= FI.getIncomingArgSize();
644}
645
646void MipsSETargetLowering::
647getOpndList(SmallVectorImpl<SDValue> &Ops,
648            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
649            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
650            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
651  // T9 should contain the address of the callee function if
652  // -reloction-model=pic or it is an indirect call.
653  if (IsPICCall || !GlobalOrExternal) {
654    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
655    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
656  } else
657    Ops.push_back(Callee);
658
659  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
660                                  InternalLinkage, CLI, Callee, Chain);
661}
662
663SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
664  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
665
666  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
667    return MipsTargetLowering::lowerLOAD(Op, DAG);
668
669  // Replace a double precision load with two i32 loads and a buildpair64.
670  SDLoc DL(Op);
671  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
672  EVT PtrVT = Ptr.getValueType();
673
674  // i32 load from lower address.
675  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
676                           MachinePointerInfo(), Nd.isVolatile(),
677                           Nd.isNonTemporal(), Nd.isInvariant(),
678                           Nd.getAlignment());
679
680  // i32 load from higher address.
681  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
682  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
683                           MachinePointerInfo(), Nd.isVolatile(),
684                           Nd.isNonTemporal(), Nd.isInvariant(),
685                           std::min(Nd.getAlignment(), 4U));
686
687  if (!Subtarget->isLittle())
688    std::swap(Lo, Hi);
689
690  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
691  SDValue Ops[2] = {BP, Hi.getValue(1)};
692  return DAG.getMergeValues(Ops, 2, DL);
693}
694
695SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
696  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
697
698  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
699    return MipsTargetLowering::lowerSTORE(Op, DAG);
700
701  // Replace a double precision store with two extractelement64s and i32 stores.
702  SDLoc DL(Op);
703  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
704  EVT PtrVT = Ptr.getValueType();
705  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
706                           Val, DAG.getConstant(0, MVT::i32));
707  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
708                           Val, DAG.getConstant(1, MVT::i32));
709
710  if (!Subtarget->isLittle())
711    std::swap(Lo, Hi);
712
713  // i32 store to lower address.
714  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
715                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
716                       Nd.getTBAAInfo());
717
718  // i32 store to higher address.
719  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
720  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
721                      Nd.isVolatile(), Nd.isNonTemporal(),
722                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
723}
724
725SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
726                                          bool HasLo, bool HasHi,
727                                          SelectionDAG &DAG) const {
728  EVT Ty = Op.getOperand(0).getValueType();
729  SDLoc DL(Op);
730  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
731                             Op.getOperand(0), Op.getOperand(1));
732  SDValue Lo, Hi;
733
734  if (HasLo)
735    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
736                     DAG.getConstant(Mips::sub_lo, MVT::i32));
737  if (HasHi)
738    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
739                     DAG.getConstant(Mips::sub_hi, MVT::i32));
740
741  if (!HasLo || !HasHi)
742    return HasLo ? Lo : Hi;
743
744  SDValue Vals[] = { Lo, Hi };
745  return DAG.getMergeValues(Vals, 2, DL);
746}
747
748
749static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
750  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
751                             DAG.getConstant(0, MVT::i32));
752  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
753                             DAG.getConstant(1, MVT::i32));
754  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
755}
756
757static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
758  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
759                           DAG.getConstant(Mips::sub_lo, MVT::i32));
760  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
761                           DAG.getConstant(Mips::sub_hi, MVT::i32));
762  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
763}
764
765// This function expands mips intrinsic nodes which have 64-bit input operands
766// or output values.
767//
768// out64 = intrinsic-node in64
769// =>
770// lo = copy (extract-element (in64, 0))
771// hi = copy (extract-element (in64, 1))
772// mips-specific-node
773// v0 = copy lo
774// v1 = copy hi
775// out64 = merge-values (v0, v1)
776//
777static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
778  SDLoc DL(Op);
779  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
780  SmallVector<SDValue, 3> Ops;
781  unsigned OpNo = 0;
782
783  // See if Op has a chain input.
784  if (HasChainIn)
785    Ops.push_back(Op->getOperand(OpNo++));
786
787  // The next operand is the intrinsic opcode.
788  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
789
790  // See if the next operand has type i64.
791  SDValue Opnd = Op->getOperand(++OpNo), In64;
792
793  if (Opnd.getValueType() == MVT::i64)
794    In64 = initAccumulator(Opnd, DL, DAG);
795  else
796    Ops.push_back(Opnd);
797
798  // Push the remaining operands.
799  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
800    Ops.push_back(Op->getOperand(OpNo));
801
802  // Add In64 to the end of the list.
803  if (In64.getNode())
804    Ops.push_back(In64);
805
806  // Scan output.
807  SmallVector<EVT, 2> ResTys;
808
809  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
810       I != E; ++I)
811    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
812
813  // Create node.
814  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
815  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
816
817  if (!HasChainIn)
818    return Out;
819
820  assert(Val->getValueType(1) == MVT::Other);
821  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
822  return DAG.getMergeValues(Vals, 2, DL);
823}
824
825static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
826  SDLoc DL(Op);
827  SDValue LHS = Op->getOperand(1);
828  SDValue RHS = Op->getOperand(2);
829  EVT ResTy = Op->getValueType(0);
830
831  SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
832
833  return Result;
834}
835
836static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
837  SDLoc DL(Op);
838  SDValue Value = Op->getOperand(1);
839  EVT ResTy = Op->getValueType(0);
840
841  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
842
843  return Result;
844}
845
846static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
847  SDLoc DL(Op);
848  SDValue Value = Op->getOperand(1);
849  EVT ResTy = Op->getValueType(0);
850
851  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
852
853  return Result;
854}
855
856SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
857                                                      SelectionDAG &DAG) const {
858  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
859  default:
860    return SDValue();
861  case Intrinsic::mips_shilo:
862    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
863  case Intrinsic::mips_dpau_h_qbl:
864    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
865  case Intrinsic::mips_dpau_h_qbr:
866    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
867  case Intrinsic::mips_dpsu_h_qbl:
868    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
869  case Intrinsic::mips_dpsu_h_qbr:
870    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
871  case Intrinsic::mips_dpa_w_ph:
872    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
873  case Intrinsic::mips_dps_w_ph:
874    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
875  case Intrinsic::mips_dpax_w_ph:
876    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
877  case Intrinsic::mips_dpsx_w_ph:
878    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
879  case Intrinsic::mips_mulsa_w_ph:
880    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
881  case Intrinsic::mips_mult:
882    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
883  case Intrinsic::mips_multu:
884    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
885  case Intrinsic::mips_madd:
886    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
887  case Intrinsic::mips_maddu:
888    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
889  case Intrinsic::mips_msub:
890    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
891  case Intrinsic::mips_msubu:
892    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
893  case Intrinsic::mips_addv_b:
894  case Intrinsic::mips_addv_h:
895  case Intrinsic::mips_addv_w:
896  case Intrinsic::mips_addv_d:
897    return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
898  case Intrinsic::mips_bnz_b:
899  case Intrinsic::mips_bnz_h:
900  case Intrinsic::mips_bnz_w:
901  case Intrinsic::mips_bnz_d:
902    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
903  case Intrinsic::mips_bnz_v:
904    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
905  case Intrinsic::mips_bz_b:
906  case Intrinsic::mips_bz_h:
907  case Intrinsic::mips_bz_w:
908  case Intrinsic::mips_bz_d:
909    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
910  case Intrinsic::mips_bz_v:
911    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
912  case Intrinsic::mips_div_s_b:
913  case Intrinsic::mips_div_s_h:
914  case Intrinsic::mips_div_s_w:
915  case Intrinsic::mips_div_s_d:
916    return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
917  case Intrinsic::mips_div_u_b:
918  case Intrinsic::mips_div_u_h:
919  case Intrinsic::mips_div_u_w:
920  case Intrinsic::mips_div_u_d:
921    return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
922  case Intrinsic::mips_fadd_w:
923  case Intrinsic::mips_fadd_d:
924    return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
925  case Intrinsic::mips_fdiv_w:
926  case Intrinsic::mips_fdiv_d:
927    return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
928  case Intrinsic::mips_fill_b:
929  case Intrinsic::mips_fill_h:
930  case Intrinsic::mips_fill_w:
931    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
932  case Intrinsic::mips_flog2_w:
933  case Intrinsic::mips_flog2_d:
934    return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
935  case Intrinsic::mips_fmul_w:
936  case Intrinsic::mips_fmul_d:
937    return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
938  case Intrinsic::mips_frint_w:
939  case Intrinsic::mips_frint_d:
940    return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
941  case Intrinsic::mips_fsqrt_w:
942  case Intrinsic::mips_fsqrt_d:
943    return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
944  case Intrinsic::mips_fsub_w:
945  case Intrinsic::mips_fsub_d:
946    return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
947  case Intrinsic::mips_ldi_b:
948  case Intrinsic::mips_ldi_h:
949  case Intrinsic::mips_ldi_w:
950  case Intrinsic::mips_ldi_d:
951    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
952  case Intrinsic::mips_mulv_b:
953  case Intrinsic::mips_mulv_h:
954  case Intrinsic::mips_mulv_w:
955  case Intrinsic::mips_mulv_d:
956    return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
957  case Intrinsic::mips_nlzc_b:
958  case Intrinsic::mips_nlzc_h:
959  case Intrinsic::mips_nlzc_w:
960  case Intrinsic::mips_nlzc_d:
961    return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
962  case Intrinsic::mips_sll_b:
963  case Intrinsic::mips_sll_h:
964  case Intrinsic::mips_sll_w:
965  case Intrinsic::mips_sll_d:
966    return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
967  case Intrinsic::mips_sra_b:
968  case Intrinsic::mips_sra_h:
969  case Intrinsic::mips_sra_w:
970  case Intrinsic::mips_sra_d:
971    return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
972  case Intrinsic::mips_srl_b:
973  case Intrinsic::mips_srl_h:
974  case Intrinsic::mips_srl_w:
975  case Intrinsic::mips_srl_d:
976    return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
977  case Intrinsic::mips_subv_b:
978  case Intrinsic::mips_subv_h:
979  case Intrinsic::mips_subv_w:
980  case Intrinsic::mips_subv_d:
981    return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
982  }
983}
984
985static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
986  SDLoc DL(Op);
987  SDValue ChainIn = Op->getOperand(0);
988  SDValue Address = Op->getOperand(2);
989  SDValue Offset  = Op->getOperand(3);
990  EVT ResTy = Op->getValueType(0);
991  EVT PtrTy = Address->getValueType(0);
992
993  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
994
995  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
996                     false, false, 16);
997}
998
999SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1000                                                     SelectionDAG &DAG) const {
1001  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1002  switch (Intr) {
1003  default:
1004    return SDValue();
1005  case Intrinsic::mips_extp:
1006    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1007  case Intrinsic::mips_extpdp:
1008    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1009  case Intrinsic::mips_extr_w:
1010    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1011  case Intrinsic::mips_extr_r_w:
1012    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1013  case Intrinsic::mips_extr_rs_w:
1014    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1015  case Intrinsic::mips_extr_s_h:
1016    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1017  case Intrinsic::mips_mthlip:
1018    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1019  case Intrinsic::mips_mulsaq_s_w_ph:
1020    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1021  case Intrinsic::mips_maq_s_w_phl:
1022    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1023  case Intrinsic::mips_maq_s_w_phr:
1024    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1025  case Intrinsic::mips_maq_sa_w_phl:
1026    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1027  case Intrinsic::mips_maq_sa_w_phr:
1028    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1029  case Intrinsic::mips_dpaq_s_w_ph:
1030    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1031  case Intrinsic::mips_dpsq_s_w_ph:
1032    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1033  case Intrinsic::mips_dpaq_sa_l_w:
1034    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1035  case Intrinsic::mips_dpsq_sa_l_w:
1036    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1037  case Intrinsic::mips_dpaqx_s_w_ph:
1038    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1039  case Intrinsic::mips_dpaqx_sa_w_ph:
1040    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1041  case Intrinsic::mips_dpsqx_s_w_ph:
1042    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1043  case Intrinsic::mips_dpsqx_sa_w_ph:
1044    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1045  case Intrinsic::mips_ld_b:
1046  case Intrinsic::mips_ld_h:
1047  case Intrinsic::mips_ld_w:
1048  case Intrinsic::mips_ld_d:
1049  case Intrinsic::mips_ldx_b:
1050  case Intrinsic::mips_ldx_h:
1051  case Intrinsic::mips_ldx_w:
1052  case Intrinsic::mips_ldx_d:
1053   return lowerMSALoadIntr(Op, DAG, Intr);
1054  }
1055}
1056
1057static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1058  SDLoc DL(Op);
1059  SDValue ChainIn = Op->getOperand(0);
1060  SDValue Value   = Op->getOperand(2);
1061  SDValue Address = Op->getOperand(3);
1062  SDValue Offset  = Op->getOperand(4);
1063  EVT PtrTy = Address->getValueType(0);
1064
1065  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1066
1067  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1068                      false, 16);
1069}
1070
1071SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1072                                                  SelectionDAG &DAG) const {
1073  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1074  switch (Intr) {
1075  default:
1076    return SDValue();
1077  case Intrinsic::mips_st_b:
1078  case Intrinsic::mips_st_h:
1079  case Intrinsic::mips_st_w:
1080  case Intrinsic::mips_st_d:
1081  case Intrinsic::mips_stx_b:
1082  case Intrinsic::mips_stx_h:
1083  case Intrinsic::mips_stx_w:
1084  case Intrinsic::mips_stx_d:
1085    return lowerMSAStoreIntr(Op, DAG, Intr);
1086  }
1087}
1088
1089/// \brief Check if the given BuildVectorSDNode is a splat.
1090/// This method currently relies on DAG nodes being reused when equivalent,
1091/// so it's possible for this to return false even when isConstantSplat returns
1092/// true.
1093static bool isSplatVector(const BuildVectorSDNode *N) {
1094  EVT VT = N->getValueType(0);
1095  assert(VT.isVector() && "Expected a vector type");
1096
1097  unsigned int nOps = N->getNumOperands();
1098  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1099
1100  SDValue Operand0 = N->getOperand(0);
1101
1102  for (unsigned int i = 1; i < nOps; ++i) {
1103    if (N->getOperand(i) != Operand0)
1104      return false;
1105  }
1106
1107  return true;
1108}
1109
1110// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1111// backend.
1112//
1113// Lowers according to the following rules:
1114// - Vectors of 128-bits may be legal subject to the other rules. Other sizes
1115//   are not legal.
1116// - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
1117// - Constant splats with an element size of 32-bits or less are legal and are
1118//   lowered to MipsISD::VSPLAT.
1119// - Constant splats with an element size of 64-bits but whose value would fit
1120//   within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
1121// - All other ISD::BUILD_VECTORS are not legal
1122SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1123                                                SelectionDAG &DAG) const {
1124  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1125  EVT ResTy = Op->getValueType(0);
1126  SDLoc DL(Op);
1127  APInt SplatValue, SplatUndef;
1128  unsigned SplatBitSize;
1129  bool HasAnyUndefs;
1130
1131  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1132    return SDValue();
1133
1134  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1135                            HasAnyUndefs, 8,
1136                            !Subtarget->isLittle())) {
1137    SDValue Result;
1138    EVT TmpVecTy;
1139    EVT ConstTy = MVT::i32;
1140    unsigned SplatOp = MipsISD::VSPLAT;
1141
1142    switch (SplatBitSize) {
1143    default:
1144      return SDValue();
1145    case 64:
1146      TmpVecTy = MVT::v2i64;
1147
1148      // i64 is an illegal type on Mips32, but if it the constant fits into a
1149      // signed 10-bit value then we can still handle it using VSPLATD and an
1150      // i32 constant
1151      if (HasMips64)
1152        ConstTy = MVT::i64;
1153      else if (isInt<10>(SplatValue.getSExtValue())) {
1154        SplatValue = SplatValue.trunc(32);
1155        SplatOp = MipsISD::VSPLATD;
1156      } else
1157        return SDValue();
1158      break;
1159    case 32:
1160      TmpVecTy = MVT::v4i32;
1161      break;
1162    case 16:
1163      TmpVecTy = MVT::v8i16;
1164      SplatValue = SplatValue.sext(32);
1165      break;
1166    case 8:
1167      TmpVecTy = MVT::v16i8;
1168      SplatValue = SplatValue.sext(32);
1169      break;
1170    }
1171
1172    Result = DAG.getNode(SplatOp, DL, TmpVecTy,
1173                         DAG.getConstant(SplatValue, ConstTy));
1174    if (ResTy != Result.getValueType())
1175      Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1176
1177    return Result;
1178  }
1179  else if (isSplatVector(Node))
1180    return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
1181
1182  return SDValue();
1183}
1184
1185MachineBasicBlock * MipsSETargetLowering::
1186emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1187  // $bb:
1188  //  bposge32_pseudo $vr0
1189  //  =>
1190  // $bb:
1191  //  bposge32 $tbb
1192  // $fbb:
1193  //  li $vr2, 0
1194  //  b $sink
1195  // $tbb:
1196  //  li $vr1, 1
1197  // $sink:
1198  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1199
1200  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1201  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1202  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1203  DebugLoc DL = MI->getDebugLoc();
1204  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1205  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1206  MachineFunction *F = BB->getParent();
1207  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1208  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1209  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1210  F->insert(It, FBB);
1211  F->insert(It, TBB);
1212  F->insert(It, Sink);
1213
1214  // Transfer the remainder of BB and its successor edges to Sink.
1215  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1216               BB->end());
1217  Sink->transferSuccessorsAndUpdatePHIs(BB);
1218
1219  // Add successors.
1220  BB->addSuccessor(FBB);
1221  BB->addSuccessor(TBB);
1222  FBB->addSuccessor(Sink);
1223  TBB->addSuccessor(Sink);
1224
1225  // Insert the real bposge32 instruction to $BB.
1226  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1227
1228  // Fill $FBB.
1229  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1230  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1231    .addReg(Mips::ZERO).addImm(0);
1232  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1233
1234  // Fill $TBB.
1235  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1236  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1237    .addReg(Mips::ZERO).addImm(1);
1238
1239  // Insert phi function to $Sink.
1240  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1241          MI->getOperand(0).getReg())
1242    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1243
1244  MI->eraseFromParent();   // The pseudo instruction is gone now.
1245  return Sink;
1246}
1247
1248MachineBasicBlock * MipsSETargetLowering::
1249emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1250                     unsigned BranchOp) const{
1251  // $bb:
1252  //  vany_nonzero $rd, $ws
1253  //  =>
1254  // $bb:
1255  //  bnz.b $ws, $tbb
1256  //  b $fbb
1257  // $fbb:
1258  //  li $rd1, 0
1259  //  b $sink
1260  // $tbb:
1261  //  li $rd2, 1
1262  // $sink:
1263  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1264
1265  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1266  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1267  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1268  DebugLoc DL = MI->getDebugLoc();
1269  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1270  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1271  MachineFunction *F = BB->getParent();
1272  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1273  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1274  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1275  F->insert(It, FBB);
1276  F->insert(It, TBB);
1277  F->insert(It, Sink);
1278
1279  // Transfer the remainder of BB and its successor edges to Sink.
1280  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1281               BB->end());
1282  Sink->transferSuccessorsAndUpdatePHIs(BB);
1283
1284  // Add successors.
1285  BB->addSuccessor(FBB);
1286  BB->addSuccessor(TBB);
1287  FBB->addSuccessor(Sink);
1288  TBB->addSuccessor(Sink);
1289
1290  // Insert the real bnz.b instruction to $BB.
1291  BuildMI(BB, DL, TII->get(BranchOp))
1292    .addReg(MI->getOperand(1).getReg())
1293    .addMBB(TBB);
1294
1295  // Fill $FBB.
1296  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1297  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1298    .addReg(Mips::ZERO).addImm(0);
1299  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1300
1301  // Fill $TBB.
1302  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1303  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1304    .addReg(Mips::ZERO).addImm(1);
1305
1306  // Insert phi function to $Sink.
1307  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1308          MI->getOperand(0).getReg())
1309    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1310
1311  MI->eraseFromParent();   // The pseudo instruction is gone now.
1312  return Sink;
1313}
1314