MipsSEISelLowering.cpp revision e0187e51a17f2081d6a72a57e0fbba8ce38d9410 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93
94    setTargetDAGCombine(ISD::AND);
95    setTargetDAGCombine(ISD::SRA);
96    setTargetDAGCombine(ISD::XOR);
97  }
98
99  if (!Subtarget->mipsSEUsesSoftFloat()) {
100    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
101
102    // When dealing with single precision only, use libcalls
103    if (!Subtarget->isSingleFloat()) {
104      if (Subtarget->isFP64bit())
105        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
106      else
107        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
108    }
109  }
110
111  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
112  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
113  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
114  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
115
116  if (HasMips64) {
117    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
118    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
119    setOperationAction(ISD::MUL,              MVT::i64, Custom);
120  }
121
122  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
123  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
124
125  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
126  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
127  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
128  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
129  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
130  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
131  setOperationAction(ISD::STORE,              MVT::i32, Custom);
132
133  setTargetDAGCombine(ISD::ADDE);
134  setTargetDAGCombine(ISD::SUBE);
135  setTargetDAGCombine(ISD::MUL);
136
137  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
138  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
139  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
140
141  if (NoDPLoadStore) {
142    setOperationAction(ISD::LOAD, MVT::f64, Custom);
143    setOperationAction(ISD::STORE, MVT::f64, Custom);
144  }
145
146  computeRegisterProperties();
147}
148
149const MipsTargetLowering *
150llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
151  return new MipsSETargetLowering(TM);
152}
153
154// Enable MSA support for the given integer type and Register class.
155void MipsSETargetLowering::
156addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
157  addRegisterClass(Ty, RC);
158
159  // Expand all builtin opcodes.
160  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
161    setOperationAction(Opc, Ty, Expand);
162
163  setOperationAction(ISD::BITCAST, Ty, Legal);
164  setOperationAction(ISD::LOAD, Ty, Legal);
165  setOperationAction(ISD::STORE, Ty, Legal);
166  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
167  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
168  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
169
170  setOperationAction(ISD::ADD, Ty, Legal);
171  setOperationAction(ISD::AND, Ty, Legal);
172  setOperationAction(ISD::CTLZ, Ty, Legal);
173  setOperationAction(ISD::CTPOP, Ty, Legal);
174  setOperationAction(ISD::MUL, Ty, Legal);
175  setOperationAction(ISD::OR, Ty, Legal);
176  setOperationAction(ISD::SDIV, Ty, Legal);
177  setOperationAction(ISD::SHL, Ty, Legal);
178  setOperationAction(ISD::SRA, Ty, Legal);
179  setOperationAction(ISD::SRL, Ty, Legal);
180  setOperationAction(ISD::SUB, Ty, Legal);
181  setOperationAction(ISD::UDIV, Ty, Legal);
182  setOperationAction(ISD::XOR, Ty, Legal);
183}
184
185// Enable MSA support for the given floating-point type and Register class.
186void MipsSETargetLowering::
187addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
188  addRegisterClass(Ty, RC);
189
190  // Expand all builtin opcodes.
191  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
192    setOperationAction(Opc, Ty, Expand);
193
194  setOperationAction(ISD::LOAD, Ty, Legal);
195  setOperationAction(ISD::STORE, Ty, Legal);
196  setOperationAction(ISD::BITCAST, Ty, Legal);
197  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
198
199  if (Ty != MVT::v8f16) {
200    setOperationAction(ISD::FADD,  Ty, Legal);
201    setOperationAction(ISD::FDIV,  Ty, Legal);
202    setOperationAction(ISD::FLOG2, Ty, Legal);
203    setOperationAction(ISD::FMUL,  Ty, Legal);
204    setOperationAction(ISD::FRINT, Ty, Legal);
205    setOperationAction(ISD::FSQRT, Ty, Legal);
206    setOperationAction(ISD::FSUB,  Ty, Legal);
207  }
208}
209
210bool
211MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
212  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
213
214  switch (SVT) {
215  case MVT::i64:
216  case MVT::i32:
217    if (Fast)
218      *Fast = true;
219    return true;
220  default:
221    return false;
222  }
223}
224
225SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
226                                             SelectionDAG &DAG) const {
227  switch(Op.getOpcode()) {
228  case ISD::LOAD:  return lowerLOAD(Op, DAG);
229  case ISD::STORE: return lowerSTORE(Op, DAG);
230  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
231  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
232  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
233  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
234  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
235  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
236  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
237                                          DAG);
238  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
239  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
240  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
241  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
242  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
243  }
244
245  return MipsTargetLowering::LowerOperation(Op, DAG);
246}
247
248// selectMADD -
249// Transforms a subgraph in CurDAG if the following pattern is found:
250//  (addc multLo, Lo0), (adde multHi, Hi0),
251// where,
252//  multHi/Lo: product of multiplication
253//  Lo0: initial value of Lo register
254//  Hi0: initial value of Hi register
255// Return true if pattern matching was successful.
256static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
257  // ADDENode's second operand must be a flag output of an ADDC node in order
258  // for the matching to be successful.
259  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
260
261  if (ADDCNode->getOpcode() != ISD::ADDC)
262    return false;
263
264  SDValue MultHi = ADDENode->getOperand(0);
265  SDValue MultLo = ADDCNode->getOperand(0);
266  SDNode *MultNode = MultHi.getNode();
267  unsigned MultOpc = MultHi.getOpcode();
268
269  // MultHi and MultLo must be generated by the same node,
270  if (MultLo.getNode() != MultNode)
271    return false;
272
273  // and it must be a multiplication.
274  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
275    return false;
276
277  // MultLo amd MultHi must be the first and second output of MultNode
278  // respectively.
279  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
280    return false;
281
282  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
283  // of the values of MultNode, in which case MultNode will be removed in later
284  // phases.
285  // If there exist users other than ADDENode or ADDCNode, this function returns
286  // here, which will result in MultNode being mapped to a single MULT
287  // instruction node rather than a pair of MULT and MADD instructions being
288  // produced.
289  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
290    return false;
291
292  SDLoc DL(ADDENode);
293
294  // Initialize accumulator.
295  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
296                                  ADDCNode->getOperand(1),
297                                  ADDENode->getOperand(1));
298
299  // create MipsMAdd(u) node
300  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
301
302  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
303                                 MultNode->getOperand(0),// Factor 0
304                                 MultNode->getOperand(1),// Factor 1
305                                 ACCIn);
306
307  // replace uses of adde and addc here
308  if (!SDValue(ADDCNode, 0).use_empty()) {
309    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
310    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
311                                    LoIdx);
312    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
313  }
314  if (!SDValue(ADDENode, 0).use_empty()) {
315    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
316    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
317                                    HiIdx);
318    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
319  }
320
321  return true;
322}
323
324// selectMSUB -
325// Transforms a subgraph in CurDAG if the following pattern is found:
326//  (addc Lo0, multLo), (sube Hi0, multHi),
327// where,
328//  multHi/Lo: product of multiplication
329//  Lo0: initial value of Lo register
330//  Hi0: initial value of Hi register
331// Return true if pattern matching was successful.
332static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
333  // SUBENode's second operand must be a flag output of an SUBC node in order
334  // for the matching to be successful.
335  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
336
337  if (SUBCNode->getOpcode() != ISD::SUBC)
338    return false;
339
340  SDValue MultHi = SUBENode->getOperand(1);
341  SDValue MultLo = SUBCNode->getOperand(1);
342  SDNode *MultNode = MultHi.getNode();
343  unsigned MultOpc = MultHi.getOpcode();
344
345  // MultHi and MultLo must be generated by the same node,
346  if (MultLo.getNode() != MultNode)
347    return false;
348
349  // and it must be a multiplication.
350  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
351    return false;
352
353  // MultLo amd MultHi must be the first and second output of MultNode
354  // respectively.
355  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
356    return false;
357
358  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
359  // of the values of MultNode, in which case MultNode will be removed in later
360  // phases.
361  // If there exist users other than SUBENode or SUBCNode, this function returns
362  // here, which will result in MultNode being mapped to a single MULT
363  // instruction node rather than a pair of MULT and MSUB instructions being
364  // produced.
365  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
366    return false;
367
368  SDLoc DL(SUBENode);
369
370  // Initialize accumulator.
371  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
372                                  SUBCNode->getOperand(0),
373                                  SUBENode->getOperand(0));
374
375  // create MipsSub(u) node
376  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
377
378  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
379                                 MultNode->getOperand(0),// Factor 0
380                                 MultNode->getOperand(1),// Factor 1
381                                 ACCIn);
382
383  // replace uses of sube and subc here
384  if (!SDValue(SUBCNode, 0).use_empty()) {
385    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
386    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
387                                    LoIdx);
388    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
389  }
390  if (!SDValue(SUBENode, 0).use_empty()) {
391    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
392    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
393                                    HiIdx);
394    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
395  }
396
397  return true;
398}
399
400static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
401                                  TargetLowering::DAGCombinerInfo &DCI,
402                                  const MipsSubtarget *Subtarget) {
403  if (DCI.isBeforeLegalize())
404    return SDValue();
405
406  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
407      selectMADD(N, &DAG))
408    return SDValue(N, 0);
409
410  return SDValue();
411}
412
413// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
414//
415// Performs the following transformations:
416// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
417//   sign/zero-extension is completely overwritten by the new one performed by
418//   the ISD::AND.
419// - Removes redundant zero extensions performed by an ISD::AND.
420static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
421                                 TargetLowering::DAGCombinerInfo &DCI,
422                                 const MipsSubtarget *Subtarget) {
423  if (!Subtarget->hasMSA())
424    return SDValue();
425
426  SDValue Op0 = N->getOperand(0);
427  SDValue Op1 = N->getOperand(1);
428  unsigned Op0Opcode = Op0->getOpcode();
429
430  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
431  // where $d + 1 == 2^n and n == 32
432  // or    $d + 1 == 2^n and n <= 32 and ZExt
433  // -> (MipsVExtractZExt $a, $b, $c)
434  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
435      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
436    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
437
438    if (!Mask)
439      return SDValue();
440
441    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
442
443    if (Log2IfPositive <= 0)
444      return SDValue(); // Mask+1 is not a power of 2
445
446    SDValue Op0Op2 = Op0->getOperand(2);
447    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
448    unsigned ExtendTySize = ExtendTy.getSizeInBits();
449    unsigned Log2 = Log2IfPositive;
450
451    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
452        Log2 == ExtendTySize) {
453      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
454      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
455                      Op0->getVTList(), Ops, Op0->getNumOperands());
456      return Op0;
457    }
458  }
459
460  return SDValue();
461}
462
463static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
464                                  TargetLowering::DAGCombinerInfo &DCI,
465                                  const MipsSubtarget *Subtarget) {
466  if (DCI.isBeforeLegalize())
467    return SDValue();
468
469  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
470      selectMSUB(N, &DAG))
471    return SDValue(N, 0);
472
473  return SDValue();
474}
475
476static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
477                            EVT ShiftTy, SelectionDAG &DAG) {
478  // Clear the upper (64 - VT.sizeInBits) bits.
479  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
480
481  // Return 0.
482  if (C == 0)
483    return DAG.getConstant(0, VT);
484
485  // Return x.
486  if (C == 1)
487    return X;
488
489  // If c is power of 2, return (shl x, log2(c)).
490  if (isPowerOf2_64(C))
491    return DAG.getNode(ISD::SHL, DL, VT, X,
492                       DAG.getConstant(Log2_64(C), ShiftTy));
493
494  unsigned Log2Ceil = Log2_64_Ceil(C);
495  uint64_t Floor = 1LL << Log2_64(C);
496  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
497
498  // If |c - floor_c| <= |c - ceil_c|,
499  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
500  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
501  if (C - Floor <= Ceil - C) {
502    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
503    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
504    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
505  }
506
507  // If |c - floor_c| > |c - ceil_c|,
508  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
509  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
510  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
511  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
512}
513
514static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
515                                 const TargetLowering::DAGCombinerInfo &DCI,
516                                 const MipsSETargetLowering *TL) {
517  EVT VT = N->getValueType(0);
518
519  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
520    if (!VT.isVector())
521      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
522                          VT, TL->getScalarShiftAmountTy(VT), DAG);
523
524  return SDValue(N, 0);
525}
526
527static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
528                                      SelectionDAG &DAG,
529                                      const MipsSubtarget *Subtarget) {
530  // See if this is a vector splat immediate node.
531  APInt SplatValue, SplatUndef;
532  unsigned SplatBitSize;
533  bool HasAnyUndefs;
534  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
535  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
536
537  if (!BV ||
538      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
539                           EltSize, !Subtarget->isLittle()) ||
540      (SplatBitSize != EltSize) ||
541      (SplatValue.getZExtValue() >= EltSize))
542    return SDValue();
543
544  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
545                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
546}
547
548static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
549                                 TargetLowering::DAGCombinerInfo &DCI,
550                                 const MipsSubtarget *Subtarget) {
551  EVT Ty = N->getValueType(0);
552
553  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
554    return SDValue();
555
556  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
557}
558
559// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
560// constant splats into MipsISD::SHRA_DSP for DSPr2.
561//
562// Performs the following transformations:
563// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
564//   sign/zero-extension is completely overwritten by the new one performed by
565//   the ISD::SRA and ISD::SHL nodes.
566// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
567//   sequence.
568//
569// See performDSPShiftCombine for more information about the transformation
570// used for DSPr2.
571static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
572                                 TargetLowering::DAGCombinerInfo &DCI,
573                                 const MipsSubtarget *Subtarget) {
574  EVT Ty = N->getValueType(0);
575
576  if (Subtarget->hasMSA()) {
577    SDValue Op0 = N->getOperand(0);
578    SDValue Op1 = N->getOperand(1);
579
580    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
581    // where $d + sizeof($c) == 32
582    // or    $d + sizeof($c) <= 32 and SExt
583    // -> (MipsVExtractSExt $a, $b, $c)
584    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
585      SDValue Op0Op0 = Op0->getOperand(0);
586      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
587
588      if (!ShAmount)
589        return SDValue();
590
591      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
592      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
593
594      if (TotalBits == 32 ||
595          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
596           TotalBits <= 32)) {
597        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
598                          Op0Op0->getOperand(2) };
599        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
600                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
601        return Op0Op0;
602      }
603    }
604  }
605
606  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
607    return SDValue();
608
609  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
610}
611
612
613static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
614                                 TargetLowering::DAGCombinerInfo &DCI,
615                                 const MipsSubtarget *Subtarget) {
616  EVT Ty = N->getValueType(0);
617
618  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
619    return SDValue();
620
621  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
622}
623
624static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
625  bool IsV216 = (Ty == MVT::v2i16);
626
627  switch (CC) {
628  case ISD::SETEQ:
629  case ISD::SETNE:  return true;
630  case ISD::SETLT:
631  case ISD::SETLE:
632  case ISD::SETGT:
633  case ISD::SETGE:  return IsV216;
634  case ISD::SETULT:
635  case ISD::SETULE:
636  case ISD::SETUGT:
637  case ISD::SETUGE: return !IsV216;
638  default:          return false;
639  }
640}
641
642static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
643  EVT Ty = N->getValueType(0);
644
645  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
646    return SDValue();
647
648  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
649    return SDValue();
650
651  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
652                     N->getOperand(1), N->getOperand(2));
653}
654
655static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
656  EVT Ty = N->getValueType(0);
657
658  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
659    return SDValue();
660
661  SDValue SetCC = N->getOperand(0);
662
663  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
664    return SDValue();
665
666  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
667                     SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
668                     N->getOperand(2), SetCC.getOperand(2));
669}
670
671static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
672                                 const MipsSubtarget *Subtarget) {
673  EVT Ty = N->getValueType(0);
674
675  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
676    // Try the following combines:
677    //   (xor (or $a, $b), (build_vector allones))
678    //   (xor (or $a, $b), (bitcast (build_vector allones)))
679    SDValue Op0 = N->getOperand(0);
680    SDValue Op1 = N->getOperand(1);
681    SDValue NotOp;
682    ConstantSDNode *Const;
683
684    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
685      NotOp = Op1;
686    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
687      NotOp = Op0;
688    else if ((Op0->getOpcode() == MipsISD::VSPLAT ||
689              Op0->getOpcode() == MipsISD::VSPLATD) &&
690             (Const = dyn_cast<ConstantSDNode>(Op0->getOperand(0))) &&
691             Const->isAllOnesValue())
692      NotOp = Op1;
693    else if ((Op1->getOpcode() == MipsISD::VSPLAT ||
694              Op1->getOpcode() == MipsISD::VSPLATD) &&
695             (Const = dyn_cast<ConstantSDNode>(Op1->getOperand(0))) &&
696             Const->isAllOnesValue())
697      NotOp = Op0;
698    else
699      return SDValue();
700
701    if (NotOp->getOpcode() == ISD::OR)
702      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
703                         NotOp->getOperand(1));
704  }
705
706  return SDValue();
707}
708
709SDValue
710MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
711  SelectionDAG &DAG = DCI.DAG;
712  SDValue Val;
713
714  switch (N->getOpcode()) {
715  case ISD::ADDE:
716    return performADDECombine(N, DAG, DCI, Subtarget);
717  case ISD::AND:
718    Val = performANDCombine(N, DAG, DCI, Subtarget);
719    break;
720  case ISD::SUBE:
721    return performSUBECombine(N, DAG, DCI, Subtarget);
722  case ISD::MUL:
723    return performMULCombine(N, DAG, DCI, this);
724  case ISD::SHL:
725    return performSHLCombine(N, DAG, DCI, Subtarget);
726  case ISD::SRA:
727    return performSRACombine(N, DAG, DCI, Subtarget);
728  case ISD::SRL:
729    return performSRLCombine(N, DAG, DCI, Subtarget);
730  case ISD::VSELECT:
731    return performVSELECTCombine(N, DAG);
732  case ISD::XOR:
733    Val = performXORCombine(N, DAG, Subtarget);
734    break;
735  case ISD::SETCC:
736    Val = performSETCCCombine(N, DAG);
737    break;
738  }
739
740  if (Val.getNode())
741    return Val;
742
743  return MipsTargetLowering::PerformDAGCombine(N, DCI);
744}
745
746MachineBasicBlock *
747MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
748                                                  MachineBasicBlock *BB) const {
749  switch (MI->getOpcode()) {
750  default:
751    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
752  case Mips::BPOSGE32_PSEUDO:
753    return emitBPOSGE32(MI, BB);
754  case Mips::SNZ_B_PSEUDO:
755    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
756  case Mips::SNZ_H_PSEUDO:
757    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
758  case Mips::SNZ_W_PSEUDO:
759    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
760  case Mips::SNZ_D_PSEUDO:
761    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
762  case Mips::SNZ_V_PSEUDO:
763    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
764  case Mips::SZ_B_PSEUDO:
765    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
766  case Mips::SZ_H_PSEUDO:
767    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
768  case Mips::SZ_W_PSEUDO:
769    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
770  case Mips::SZ_D_PSEUDO:
771    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
772  case Mips::SZ_V_PSEUDO:
773    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
774  }
775}
776
777bool MipsSETargetLowering::
778isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
779                                  unsigned NextStackOffset,
780                                  const MipsFunctionInfo& FI) const {
781  if (!EnableMipsTailCalls)
782    return false;
783
784  // Return false if either the callee or caller has a byval argument.
785  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
786    return false;
787
788  // Return true if the callee's argument area is no larger than the
789  // caller's.
790  return NextStackOffset <= FI.getIncomingArgSize();
791}
792
793void MipsSETargetLowering::
794getOpndList(SmallVectorImpl<SDValue> &Ops,
795            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
796            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
797            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
798  // T9 should contain the address of the callee function if
799  // -reloction-model=pic or it is an indirect call.
800  if (IsPICCall || !GlobalOrExternal) {
801    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
802    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
803  } else
804    Ops.push_back(Callee);
805
806  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
807                                  InternalLinkage, CLI, Callee, Chain);
808}
809
810SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
811  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
812
813  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
814    return MipsTargetLowering::lowerLOAD(Op, DAG);
815
816  // Replace a double precision load with two i32 loads and a buildpair64.
817  SDLoc DL(Op);
818  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
819  EVT PtrVT = Ptr.getValueType();
820
821  // i32 load from lower address.
822  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
823                           MachinePointerInfo(), Nd.isVolatile(),
824                           Nd.isNonTemporal(), Nd.isInvariant(),
825                           Nd.getAlignment());
826
827  // i32 load from higher address.
828  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
829  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
830                           MachinePointerInfo(), Nd.isVolatile(),
831                           Nd.isNonTemporal(), Nd.isInvariant(),
832                           std::min(Nd.getAlignment(), 4U));
833
834  if (!Subtarget->isLittle())
835    std::swap(Lo, Hi);
836
837  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
838  SDValue Ops[2] = {BP, Hi.getValue(1)};
839  return DAG.getMergeValues(Ops, 2, DL);
840}
841
842SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
843  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
844
845  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
846    return MipsTargetLowering::lowerSTORE(Op, DAG);
847
848  // Replace a double precision store with two extractelement64s and i32 stores.
849  SDLoc DL(Op);
850  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
851  EVT PtrVT = Ptr.getValueType();
852  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
853                           Val, DAG.getConstant(0, MVT::i32));
854  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
855                           Val, DAG.getConstant(1, MVT::i32));
856
857  if (!Subtarget->isLittle())
858    std::swap(Lo, Hi);
859
860  // i32 store to lower address.
861  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
862                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
863                       Nd.getTBAAInfo());
864
865  // i32 store to higher address.
866  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
867  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
868                      Nd.isVolatile(), Nd.isNonTemporal(),
869                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
870}
871
872SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
873                                          bool HasLo, bool HasHi,
874                                          SelectionDAG &DAG) const {
875  EVT Ty = Op.getOperand(0).getValueType();
876  SDLoc DL(Op);
877  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
878                             Op.getOperand(0), Op.getOperand(1));
879  SDValue Lo, Hi;
880
881  if (HasLo)
882    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
883                     DAG.getConstant(Mips::sub_lo, MVT::i32));
884  if (HasHi)
885    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
886                     DAG.getConstant(Mips::sub_hi, MVT::i32));
887
888  if (!HasLo || !HasHi)
889    return HasLo ? Lo : Hi;
890
891  SDValue Vals[] = { Lo, Hi };
892  return DAG.getMergeValues(Vals, 2, DL);
893}
894
895
896static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
897  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
898                             DAG.getConstant(0, MVT::i32));
899  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
900                             DAG.getConstant(1, MVT::i32));
901  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
902}
903
904static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
905  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
906                           DAG.getConstant(Mips::sub_lo, MVT::i32));
907  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
908                           DAG.getConstant(Mips::sub_hi, MVT::i32));
909  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
910}
911
912// This function expands mips intrinsic nodes which have 64-bit input operands
913// or output values.
914//
915// out64 = intrinsic-node in64
916// =>
917// lo = copy (extract-element (in64, 0))
918// hi = copy (extract-element (in64, 1))
919// mips-specific-node
920// v0 = copy lo
921// v1 = copy hi
922// out64 = merge-values (v0, v1)
923//
924static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
925  SDLoc DL(Op);
926  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
927  SmallVector<SDValue, 3> Ops;
928  unsigned OpNo = 0;
929
930  // See if Op has a chain input.
931  if (HasChainIn)
932    Ops.push_back(Op->getOperand(OpNo++));
933
934  // The next operand is the intrinsic opcode.
935  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
936
937  // See if the next operand has type i64.
938  SDValue Opnd = Op->getOperand(++OpNo), In64;
939
940  if (Opnd.getValueType() == MVT::i64)
941    In64 = initAccumulator(Opnd, DL, DAG);
942  else
943    Ops.push_back(Opnd);
944
945  // Push the remaining operands.
946  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
947    Ops.push_back(Op->getOperand(OpNo));
948
949  // Add In64 to the end of the list.
950  if (In64.getNode())
951    Ops.push_back(In64);
952
953  // Scan output.
954  SmallVector<EVT, 2> ResTys;
955
956  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
957       I != E; ++I)
958    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
959
960  // Create node.
961  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
962  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
963
964  if (!HasChainIn)
965    return Out;
966
967  assert(Val->getValueType(1) == MVT::Other);
968  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
969  return DAG.getMergeValues(Vals, 2, DL);
970}
971
972static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
973  SDLoc DL(Op);
974  SDValue LHS = Op->getOperand(1);
975  SDValue RHS = Op->getOperand(2);
976  EVT ResTy = Op->getValueType(0);
977
978  SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
979
980  return Result;
981}
982
983static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
984                                     unsigned Opc, SDValue RHS) {
985  SDValue LHS = Op->getOperand(1);
986  EVT ResTy = Op->getValueType(0);
987
988  return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
989}
990
991static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
992  SDLoc DL(Op);
993  SDValue Value = Op->getOperand(1);
994  EVT ResTy = Op->getValueType(0);
995
996  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
997
998  return Result;
999}
1000
1001// Lower an MSA copy intrinsic into the specified SelectionDAG node
1002static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1003  SDLoc DL(Op);
1004  SDValue Vec = Op->getOperand(1);
1005  SDValue Idx = Op->getOperand(2);
1006  EVT ResTy = Op->getValueType(0);
1007  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1008
1009  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1010                               DAG.getValueType(EltTy));
1011
1012  return Result;
1013}
1014
1015// Lower an MSA insert intrinsic into the specified SelectionDAG node
1016static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1017  SDLoc DL(Op);
1018  SDValue Op0 = Op->getOperand(1);
1019  SDValue Op1 = Op->getOperand(2);
1020  SDValue Op2 = Op->getOperand(3);
1021  EVT ResTy = Op->getValueType(0);
1022
1023  SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
1024
1025  return Result;
1026}
1027
1028static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1029  EVT ResTy = Op->getValueType(0);
1030
1031  unsigned SplatOp = MipsISD::VSPLAT;
1032  if (ResTy == MVT::v2i64)
1033    SplatOp = MipsISD::VSPLATD;
1034
1035  return DAG.getNode(SplatOp, SDLoc(Op), ResTy, Op->getOperand(ImmOp));
1036}
1037
1038static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1039  SDLoc DL(Op);
1040  SDValue Value = Op->getOperand(1);
1041  EVT ResTy = Op->getValueType(0);
1042
1043  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1044
1045  return Result;
1046}
1047
1048SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1049                                                      SelectionDAG &DAG) const {
1050  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1051  default:
1052    return SDValue();
1053  case Intrinsic::mips_shilo:
1054    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1055  case Intrinsic::mips_dpau_h_qbl:
1056    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1057  case Intrinsic::mips_dpau_h_qbr:
1058    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1059  case Intrinsic::mips_dpsu_h_qbl:
1060    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1061  case Intrinsic::mips_dpsu_h_qbr:
1062    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1063  case Intrinsic::mips_dpa_w_ph:
1064    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1065  case Intrinsic::mips_dps_w_ph:
1066    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1067  case Intrinsic::mips_dpax_w_ph:
1068    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1069  case Intrinsic::mips_dpsx_w_ph:
1070    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1071  case Intrinsic::mips_mulsa_w_ph:
1072    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1073  case Intrinsic::mips_mult:
1074    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1075  case Intrinsic::mips_multu:
1076    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1077  case Intrinsic::mips_madd:
1078    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1079  case Intrinsic::mips_maddu:
1080    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1081  case Intrinsic::mips_msub:
1082    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1083  case Intrinsic::mips_msubu:
1084    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1085  case Intrinsic::mips_addv_b:
1086  case Intrinsic::mips_addv_h:
1087  case Intrinsic::mips_addv_w:
1088  case Intrinsic::mips_addv_d:
1089    return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
1090  case Intrinsic::mips_addvi_b:
1091  case Intrinsic::mips_addvi_h:
1092  case Intrinsic::mips_addvi_w:
1093  case Intrinsic::mips_addvi_d:
1094    return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
1095                                 lowerMSASplatImm(Op, 2, DAG));
1096  case Intrinsic::mips_and_v:
1097    return lowerMSABinaryIntr(Op, DAG, ISD::AND);
1098  case Intrinsic::mips_bnz_b:
1099  case Intrinsic::mips_bnz_h:
1100  case Intrinsic::mips_bnz_w:
1101  case Intrinsic::mips_bnz_d:
1102    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
1103  case Intrinsic::mips_bnz_v:
1104    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
1105  case Intrinsic::mips_bz_b:
1106  case Intrinsic::mips_bz_h:
1107  case Intrinsic::mips_bz_w:
1108  case Intrinsic::mips_bz_d:
1109    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
1110  case Intrinsic::mips_bz_v:
1111    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
1112  case Intrinsic::mips_copy_s_b:
1113  case Intrinsic::mips_copy_s_h:
1114  case Intrinsic::mips_copy_s_w:
1115    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1116  case Intrinsic::mips_copy_u_b:
1117  case Intrinsic::mips_copy_u_h:
1118  case Intrinsic::mips_copy_u_w:
1119    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1120  case Intrinsic::mips_div_s_b:
1121  case Intrinsic::mips_div_s_h:
1122  case Intrinsic::mips_div_s_w:
1123  case Intrinsic::mips_div_s_d:
1124    return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
1125  case Intrinsic::mips_div_u_b:
1126  case Intrinsic::mips_div_u_h:
1127  case Intrinsic::mips_div_u_w:
1128  case Intrinsic::mips_div_u_d:
1129    return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
1130  case Intrinsic::mips_fadd_w:
1131  case Intrinsic::mips_fadd_d:
1132    return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
1133  case Intrinsic::mips_fdiv_w:
1134  case Intrinsic::mips_fdiv_d:
1135    return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
1136  case Intrinsic::mips_fill_b:
1137  case Intrinsic::mips_fill_h:
1138  case Intrinsic::mips_fill_w:
1139    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1140  case Intrinsic::mips_flog2_w:
1141  case Intrinsic::mips_flog2_d:
1142    return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
1143  case Intrinsic::mips_fmul_w:
1144  case Intrinsic::mips_fmul_d:
1145    return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
1146  case Intrinsic::mips_frint_w:
1147  case Intrinsic::mips_frint_d:
1148    return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
1149  case Intrinsic::mips_fsqrt_w:
1150  case Intrinsic::mips_fsqrt_d:
1151    return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
1152  case Intrinsic::mips_fsub_w:
1153  case Intrinsic::mips_fsub_d:
1154    return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
1155  case Intrinsic::mips_insert_b:
1156  case Intrinsic::mips_insert_h:
1157  case Intrinsic::mips_insert_w:
1158    return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
1159  case Intrinsic::mips_ldi_b:
1160  case Intrinsic::mips_ldi_h:
1161  case Intrinsic::mips_ldi_w:
1162  case Intrinsic::mips_ldi_d:
1163    return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
1164  case Intrinsic::mips_mulv_b:
1165  case Intrinsic::mips_mulv_h:
1166  case Intrinsic::mips_mulv_w:
1167  case Intrinsic::mips_mulv_d:
1168    return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
1169  case Intrinsic::mips_nlzc_b:
1170  case Intrinsic::mips_nlzc_h:
1171  case Intrinsic::mips_nlzc_w:
1172  case Intrinsic::mips_nlzc_d:
1173    return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
1174  case Intrinsic::mips_nor_v: {
1175    SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
1176    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1177  }
1178  case Intrinsic::mips_or_v:
1179    return lowerMSABinaryIntr(Op, DAG, ISD::OR);
1180  case Intrinsic::mips_pcnt_b:
1181  case Intrinsic::mips_pcnt_h:
1182  case Intrinsic::mips_pcnt_w:
1183  case Intrinsic::mips_pcnt_d:
1184    return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
1185  case Intrinsic::mips_sll_b:
1186  case Intrinsic::mips_sll_h:
1187  case Intrinsic::mips_sll_w:
1188  case Intrinsic::mips_sll_d:
1189    return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
1190  case Intrinsic::mips_sra_b:
1191  case Intrinsic::mips_sra_h:
1192  case Intrinsic::mips_sra_w:
1193  case Intrinsic::mips_sra_d:
1194    return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
1195  case Intrinsic::mips_srl_b:
1196  case Intrinsic::mips_srl_h:
1197  case Intrinsic::mips_srl_w:
1198  case Intrinsic::mips_srl_d:
1199    return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
1200  case Intrinsic::mips_subv_b:
1201  case Intrinsic::mips_subv_h:
1202  case Intrinsic::mips_subv_w:
1203  case Intrinsic::mips_subv_d:
1204    return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
1205  case Intrinsic::mips_subvi_b:
1206  case Intrinsic::mips_subvi_h:
1207  case Intrinsic::mips_subvi_w:
1208  case Intrinsic::mips_subvi_d:
1209    return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
1210                                 lowerMSASplatImm(Op, 2, DAG));
1211  case Intrinsic::mips_xor_v:
1212    return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
1213  }
1214}
1215
1216static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1217  SDLoc DL(Op);
1218  SDValue ChainIn = Op->getOperand(0);
1219  SDValue Address = Op->getOperand(2);
1220  SDValue Offset  = Op->getOperand(3);
1221  EVT ResTy = Op->getValueType(0);
1222  EVT PtrTy = Address->getValueType(0);
1223
1224  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1225
1226  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1227                     false, false, 16);
1228}
1229
1230SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1231                                                     SelectionDAG &DAG) const {
1232  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1233  switch (Intr) {
1234  default:
1235    return SDValue();
1236  case Intrinsic::mips_extp:
1237    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1238  case Intrinsic::mips_extpdp:
1239    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1240  case Intrinsic::mips_extr_w:
1241    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1242  case Intrinsic::mips_extr_r_w:
1243    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1244  case Intrinsic::mips_extr_rs_w:
1245    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1246  case Intrinsic::mips_extr_s_h:
1247    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1248  case Intrinsic::mips_mthlip:
1249    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1250  case Intrinsic::mips_mulsaq_s_w_ph:
1251    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1252  case Intrinsic::mips_maq_s_w_phl:
1253    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1254  case Intrinsic::mips_maq_s_w_phr:
1255    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1256  case Intrinsic::mips_maq_sa_w_phl:
1257    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1258  case Intrinsic::mips_maq_sa_w_phr:
1259    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1260  case Intrinsic::mips_dpaq_s_w_ph:
1261    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1262  case Intrinsic::mips_dpsq_s_w_ph:
1263    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1264  case Intrinsic::mips_dpaq_sa_l_w:
1265    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1266  case Intrinsic::mips_dpsq_sa_l_w:
1267    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1268  case Intrinsic::mips_dpaqx_s_w_ph:
1269    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1270  case Intrinsic::mips_dpaqx_sa_w_ph:
1271    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1272  case Intrinsic::mips_dpsqx_s_w_ph:
1273    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1274  case Intrinsic::mips_dpsqx_sa_w_ph:
1275    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1276  case Intrinsic::mips_ld_b:
1277  case Intrinsic::mips_ld_h:
1278  case Intrinsic::mips_ld_w:
1279  case Intrinsic::mips_ld_d:
1280  case Intrinsic::mips_ldx_b:
1281  case Intrinsic::mips_ldx_h:
1282  case Intrinsic::mips_ldx_w:
1283  case Intrinsic::mips_ldx_d:
1284   return lowerMSALoadIntr(Op, DAG, Intr);
1285  }
1286}
1287
1288static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1289  SDLoc DL(Op);
1290  SDValue ChainIn = Op->getOperand(0);
1291  SDValue Value   = Op->getOperand(2);
1292  SDValue Address = Op->getOperand(3);
1293  SDValue Offset  = Op->getOperand(4);
1294  EVT PtrTy = Address->getValueType(0);
1295
1296  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1297
1298  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1299                      false, 16);
1300}
1301
1302SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1303                                                  SelectionDAG &DAG) const {
1304  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1305  switch (Intr) {
1306  default:
1307    return SDValue();
1308  case Intrinsic::mips_st_b:
1309  case Intrinsic::mips_st_h:
1310  case Intrinsic::mips_st_w:
1311  case Intrinsic::mips_st_d:
1312  case Intrinsic::mips_stx_b:
1313  case Intrinsic::mips_stx_h:
1314  case Intrinsic::mips_stx_w:
1315  case Intrinsic::mips_stx_d:
1316    return lowerMSAStoreIntr(Op, DAG, Intr);
1317  }
1318}
1319
1320/// \brief Check if the given BuildVectorSDNode is a splat.
1321/// This method currently relies on DAG nodes being reused when equivalent,
1322/// so it's possible for this to return false even when isConstantSplat returns
1323/// true.
1324static bool isSplatVector(const BuildVectorSDNode *N) {
1325  unsigned int nOps = N->getNumOperands();
1326  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1327
1328  SDValue Operand0 = N->getOperand(0);
1329
1330  for (unsigned int i = 1; i < nOps; ++i) {
1331    if (N->getOperand(i) != Operand0)
1332      return false;
1333  }
1334
1335  return true;
1336}
1337
1338// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1339//
1340// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1341// choose to sign-extend but we could have equally chosen zero-extend. The
1342// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1343// result into this node later (possibly changing it to a zero-extend in the
1344// process).
1345SDValue MipsSETargetLowering::
1346lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1347  SDLoc DL(Op);
1348  EVT ResTy = Op->getValueType(0);
1349  SDValue Op0 = Op->getOperand(0);
1350  SDValue Op1 = Op->getOperand(1);
1351  EVT EltTy = Op0->getValueType(0).getVectorElementType();
1352  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1353                     DAG.getValueType(EltTy));
1354}
1355
1356// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1357// backend.
1358//
1359// Lowers according to the following rules:
1360// - Vectors of 128-bits may be legal subject to the other rules. Other sizes
1361//   are not legal.
1362// - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
1363// - Constant splats with an element size of 32-bits or less are legal and are
1364//   lowered to MipsISD::VSPLAT.
1365// - Constant splats with an element size of 64-bits but whose value would fit
1366//   within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
1367// - All other ISD::BUILD_VECTORS are not legal
1368SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1369                                                SelectionDAG &DAG) const {
1370  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1371  EVT ResTy = Op->getValueType(0);
1372  SDLoc DL(Op);
1373  APInt SplatValue, SplatUndef;
1374  unsigned SplatBitSize;
1375  bool HasAnyUndefs;
1376
1377  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1378    return SDValue();
1379
1380  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1381                            HasAnyUndefs, 8,
1382                            !Subtarget->isLittle())) {
1383    SDValue Result;
1384    EVT TmpVecTy;
1385    EVT ConstTy = MVT::i32;
1386    unsigned SplatOp = MipsISD::VSPLAT;
1387
1388    switch (SplatBitSize) {
1389    default:
1390      return SDValue();
1391    case 64:
1392      TmpVecTy = MVT::v2i64;
1393
1394      // i64 is an illegal type on Mips32, but if it the constant fits into a
1395      // signed 10-bit value then we can still handle it using VSPLATD and an
1396      // i32 constant
1397      if (HasMips64)
1398        ConstTy = MVT::i64;
1399      else if (isInt<10>(SplatValue.getSExtValue())) {
1400        SplatValue = SplatValue.trunc(32);
1401        SplatOp = MipsISD::VSPLATD;
1402      } else
1403        return SDValue();
1404      break;
1405    case 32:
1406      TmpVecTy = MVT::v4i32;
1407      break;
1408    case 16:
1409      TmpVecTy = MVT::v8i16;
1410      SplatValue = SplatValue.sext(32);
1411      break;
1412    case 8:
1413      TmpVecTy = MVT::v16i8;
1414      SplatValue = SplatValue.sext(32);
1415      break;
1416    }
1417
1418    Result = DAG.getNode(SplatOp, DL, TmpVecTy,
1419                         DAG.getConstant(SplatValue, ConstTy));
1420    if (ResTy != Result.getValueType())
1421      Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1422
1423    return Result;
1424  }
1425  else if (isSplatVector(Node))
1426    return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
1427
1428  return SDValue();
1429}
1430
1431MachineBasicBlock * MipsSETargetLowering::
1432emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1433  // $bb:
1434  //  bposge32_pseudo $vr0
1435  //  =>
1436  // $bb:
1437  //  bposge32 $tbb
1438  // $fbb:
1439  //  li $vr2, 0
1440  //  b $sink
1441  // $tbb:
1442  //  li $vr1, 1
1443  // $sink:
1444  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1445
1446  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1447  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1448  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1449  DebugLoc DL = MI->getDebugLoc();
1450  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1451  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1452  MachineFunction *F = BB->getParent();
1453  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1454  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1455  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1456  F->insert(It, FBB);
1457  F->insert(It, TBB);
1458  F->insert(It, Sink);
1459
1460  // Transfer the remainder of BB and its successor edges to Sink.
1461  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1462               BB->end());
1463  Sink->transferSuccessorsAndUpdatePHIs(BB);
1464
1465  // Add successors.
1466  BB->addSuccessor(FBB);
1467  BB->addSuccessor(TBB);
1468  FBB->addSuccessor(Sink);
1469  TBB->addSuccessor(Sink);
1470
1471  // Insert the real bposge32 instruction to $BB.
1472  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1473
1474  // Fill $FBB.
1475  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1476  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1477    .addReg(Mips::ZERO).addImm(0);
1478  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1479
1480  // Fill $TBB.
1481  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1482  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1483    .addReg(Mips::ZERO).addImm(1);
1484
1485  // Insert phi function to $Sink.
1486  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1487          MI->getOperand(0).getReg())
1488    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1489
1490  MI->eraseFromParent();   // The pseudo instruction is gone now.
1491  return Sink;
1492}
1493
1494MachineBasicBlock * MipsSETargetLowering::
1495emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1496                     unsigned BranchOp) const{
1497  // $bb:
1498  //  vany_nonzero $rd, $ws
1499  //  =>
1500  // $bb:
1501  //  bnz.b $ws, $tbb
1502  //  b $fbb
1503  // $fbb:
1504  //  li $rd1, 0
1505  //  b $sink
1506  // $tbb:
1507  //  li $rd2, 1
1508  // $sink:
1509  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1510
1511  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1512  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1513  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1514  DebugLoc DL = MI->getDebugLoc();
1515  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1516  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1517  MachineFunction *F = BB->getParent();
1518  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1519  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1520  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1521  F->insert(It, FBB);
1522  F->insert(It, TBB);
1523  F->insert(It, Sink);
1524
1525  // Transfer the remainder of BB and its successor edges to Sink.
1526  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1527               BB->end());
1528  Sink->transferSuccessorsAndUpdatePHIs(BB);
1529
1530  // Add successors.
1531  BB->addSuccessor(FBB);
1532  BB->addSuccessor(TBB);
1533  FBB->addSuccessor(Sink);
1534  TBB->addSuccessor(Sink);
1535
1536  // Insert the real bnz.b instruction to $BB.
1537  BuildMI(BB, DL, TII->get(BranchOp))
1538    .addReg(MI->getOperand(1).getReg())
1539    .addMBB(TBB);
1540
1541  // Fill $FBB.
1542  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1543  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1544    .addReg(Mips::ZERO).addImm(0);
1545  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1546
1547  // Fill $TBB.
1548  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1549  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1550    .addReg(Mips::ZERO).addImm(1);
1551
1552  // Insert phi function to $Sink.
1553  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1554          MI->getOperand(0).getReg())
1555    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1556
1557  MI->eraseFromParent();   // The pseudo instruction is gone now.
1558  return Sink;
1559}
1560