MipsSEISelLowering.cpp revision f515964d36834ec918fe831029bc72ccdcec34d3 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93
94    setTargetDAGCombine(ISD::AND);
95    setTargetDAGCombine(ISD::SRA);
96    setTargetDAGCombine(ISD::VSELECT);
97    setTargetDAGCombine(ISD::XOR);
98  }
99
100  if (!Subtarget->mipsSEUsesSoftFloat()) {
101    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
102
103    // When dealing with single precision only, use libcalls
104    if (!Subtarget->isSingleFloat()) {
105      if (Subtarget->isFP64bit())
106        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
107      else
108        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
109    }
110  }
111
112  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
113  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
114  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
115  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
116
117  if (HasMips64) {
118    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
119    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
120    setOperationAction(ISD::MUL,              MVT::i64, Custom);
121  }
122
123  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
124  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
125
126  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
127  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
128  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
129  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
130  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
131  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
132  setOperationAction(ISD::STORE,              MVT::i32, Custom);
133
134  setTargetDAGCombine(ISD::ADDE);
135  setTargetDAGCombine(ISD::SUBE);
136  setTargetDAGCombine(ISD::MUL);
137
138  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
139  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
140  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141
142  if (NoDPLoadStore) {
143    setOperationAction(ISD::LOAD, MVT::f64, Custom);
144    setOperationAction(ISD::STORE, MVT::f64, Custom);
145  }
146
147  computeRegisterProperties();
148}
149
150const MipsTargetLowering *
151llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
152  return new MipsSETargetLowering(TM);
153}
154
155// Enable MSA support for the given integer type and Register class.
156void MipsSETargetLowering::
157addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
158  addRegisterClass(Ty, RC);
159
160  // Expand all builtin opcodes.
161  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
162    setOperationAction(Opc, Ty, Expand);
163
164  setOperationAction(ISD::BITCAST, Ty, Legal);
165  setOperationAction(ISD::LOAD, Ty, Legal);
166  setOperationAction(ISD::STORE, Ty, Legal);
167  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
168  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
169  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
170
171  setOperationAction(ISD::ADD, Ty, Legal);
172  setOperationAction(ISD::AND, Ty, Legal);
173  setOperationAction(ISD::CTLZ, Ty, Legal);
174  setOperationAction(ISD::CTPOP, Ty, Legal);
175  setOperationAction(ISD::MUL, Ty, Legal);
176  setOperationAction(ISD::OR, Ty, Legal);
177  setOperationAction(ISD::SDIV, Ty, Legal);
178  setOperationAction(ISD::SHL, Ty, Legal);
179  setOperationAction(ISD::SRA, Ty, Legal);
180  setOperationAction(ISD::SRL, Ty, Legal);
181  setOperationAction(ISD::SUB, Ty, Legal);
182  setOperationAction(ISD::UDIV, Ty, Legal);
183  setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
184  setOperationAction(ISD::VSELECT, Ty, Legal);
185  setOperationAction(ISD::XOR, Ty, Legal);
186
187  setOperationAction(ISD::SETCC, Ty, Legal);
188  setCondCodeAction(ISD::SETNE, Ty, Expand);
189  setCondCodeAction(ISD::SETGE, Ty, Expand);
190  setCondCodeAction(ISD::SETGT, Ty, Expand);
191  setCondCodeAction(ISD::SETUGE, Ty, Expand);
192  setCondCodeAction(ISD::SETUGT, Ty, Expand);
193}
194
195// Enable MSA support for the given floating-point type and Register class.
196void MipsSETargetLowering::
197addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
198  addRegisterClass(Ty, RC);
199
200  // Expand all builtin opcodes.
201  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
202    setOperationAction(Opc, Ty, Expand);
203
204  setOperationAction(ISD::LOAD, Ty, Legal);
205  setOperationAction(ISD::STORE, Ty, Legal);
206  setOperationAction(ISD::BITCAST, Ty, Legal);
207  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
208
209  if (Ty != MVT::v8f16) {
210    setOperationAction(ISD::FABS,  Ty, Legal);
211    setOperationAction(ISD::FADD,  Ty, Legal);
212    setOperationAction(ISD::FDIV,  Ty, Legal);
213    setOperationAction(ISD::FLOG2, Ty, Legal);
214    setOperationAction(ISD::FMUL,  Ty, Legal);
215    setOperationAction(ISD::FRINT, Ty, Legal);
216    setOperationAction(ISD::FSQRT, Ty, Legal);
217    setOperationAction(ISD::FSUB,  Ty, Legal);
218    setOperationAction(ISD::VSELECT, Ty, Legal);
219
220    setOperationAction(ISD::SETCC, Ty, Legal);
221    setCondCodeAction(ISD::SETOGE, Ty, Expand);
222    setCondCodeAction(ISD::SETOGT, Ty, Expand);
223    setCondCodeAction(ISD::SETUGE, Ty, Expand);
224    setCondCodeAction(ISD::SETUGT, Ty, Expand);
225    setCondCodeAction(ISD::SETGE,  Ty, Expand);
226    setCondCodeAction(ISD::SETGT,  Ty, Expand);
227  }
228}
229
230bool
231MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
232  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
233
234  switch (SVT) {
235  case MVT::i64:
236  case MVT::i32:
237    if (Fast)
238      *Fast = true;
239    return true;
240  default:
241    return false;
242  }
243}
244
245SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
246                                             SelectionDAG &DAG) const {
247  switch(Op.getOpcode()) {
248  case ISD::LOAD:  return lowerLOAD(Op, DAG);
249  case ISD::STORE: return lowerSTORE(Op, DAG);
250  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
251  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
252  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
253  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
254  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
255  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
256  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
257                                          DAG);
258  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
259  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
260  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
261  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
262  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
263  case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);
264  }
265
266  return MipsTargetLowering::LowerOperation(Op, DAG);
267}
268
269// selectMADD -
270// Transforms a subgraph in CurDAG if the following pattern is found:
271//  (addc multLo, Lo0), (adde multHi, Hi0),
272// where,
273//  multHi/Lo: product of multiplication
274//  Lo0: initial value of Lo register
275//  Hi0: initial value of Hi register
276// Return true if pattern matching was successful.
277static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
278  // ADDENode's second operand must be a flag output of an ADDC node in order
279  // for the matching to be successful.
280  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
281
282  if (ADDCNode->getOpcode() != ISD::ADDC)
283    return false;
284
285  SDValue MultHi = ADDENode->getOperand(0);
286  SDValue MultLo = ADDCNode->getOperand(0);
287  SDNode *MultNode = MultHi.getNode();
288  unsigned MultOpc = MultHi.getOpcode();
289
290  // MultHi and MultLo must be generated by the same node,
291  if (MultLo.getNode() != MultNode)
292    return false;
293
294  // and it must be a multiplication.
295  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
296    return false;
297
298  // MultLo amd MultHi must be the first and second output of MultNode
299  // respectively.
300  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
301    return false;
302
303  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
304  // of the values of MultNode, in which case MultNode will be removed in later
305  // phases.
306  // If there exist users other than ADDENode or ADDCNode, this function returns
307  // here, which will result in MultNode being mapped to a single MULT
308  // instruction node rather than a pair of MULT and MADD instructions being
309  // produced.
310  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
311    return false;
312
313  SDLoc DL(ADDENode);
314
315  // Initialize accumulator.
316  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
317                                  ADDCNode->getOperand(1),
318                                  ADDENode->getOperand(1));
319
320  // create MipsMAdd(u) node
321  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
322
323  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
324                                 MultNode->getOperand(0),// Factor 0
325                                 MultNode->getOperand(1),// Factor 1
326                                 ACCIn);
327
328  // replace uses of adde and addc here
329  if (!SDValue(ADDCNode, 0).use_empty()) {
330    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
331    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
332                                    LoIdx);
333    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
334  }
335  if (!SDValue(ADDENode, 0).use_empty()) {
336    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
337    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
338                                    HiIdx);
339    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
340  }
341
342  return true;
343}
344
345// selectMSUB -
346// Transforms a subgraph in CurDAG if the following pattern is found:
347//  (addc Lo0, multLo), (sube Hi0, multHi),
348// where,
349//  multHi/Lo: product of multiplication
350//  Lo0: initial value of Lo register
351//  Hi0: initial value of Hi register
352// Return true if pattern matching was successful.
353static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
354  // SUBENode's second operand must be a flag output of an SUBC node in order
355  // for the matching to be successful.
356  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
357
358  if (SUBCNode->getOpcode() != ISD::SUBC)
359    return false;
360
361  SDValue MultHi = SUBENode->getOperand(1);
362  SDValue MultLo = SUBCNode->getOperand(1);
363  SDNode *MultNode = MultHi.getNode();
364  unsigned MultOpc = MultHi.getOpcode();
365
366  // MultHi and MultLo must be generated by the same node,
367  if (MultLo.getNode() != MultNode)
368    return false;
369
370  // and it must be a multiplication.
371  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
372    return false;
373
374  // MultLo amd MultHi must be the first and second output of MultNode
375  // respectively.
376  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
377    return false;
378
379  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
380  // of the values of MultNode, in which case MultNode will be removed in later
381  // phases.
382  // If there exist users other than SUBENode or SUBCNode, this function returns
383  // here, which will result in MultNode being mapped to a single MULT
384  // instruction node rather than a pair of MULT and MSUB instructions being
385  // produced.
386  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
387    return false;
388
389  SDLoc DL(SUBENode);
390
391  // Initialize accumulator.
392  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
393                                  SUBCNode->getOperand(0),
394                                  SUBENode->getOperand(0));
395
396  // create MipsSub(u) node
397  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
398
399  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
400                                 MultNode->getOperand(0),// Factor 0
401                                 MultNode->getOperand(1),// Factor 1
402                                 ACCIn);
403
404  // replace uses of sube and subc here
405  if (!SDValue(SUBCNode, 0).use_empty()) {
406    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
407    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
408                                    LoIdx);
409    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
410  }
411  if (!SDValue(SUBENode, 0).use_empty()) {
412    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
413    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
414                                    HiIdx);
415    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
416  }
417
418  return true;
419}
420
421static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
422                                  TargetLowering::DAGCombinerInfo &DCI,
423                                  const MipsSubtarget *Subtarget) {
424  if (DCI.isBeforeLegalize())
425    return SDValue();
426
427  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
428      selectMADD(N, &DAG))
429    return SDValue(N, 0);
430
431  return SDValue();
432}
433
434// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
435//
436// Performs the following transformations:
437// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
438//   sign/zero-extension is completely overwritten by the new one performed by
439//   the ISD::AND.
440// - Removes redundant zero extensions performed by an ISD::AND.
441static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
442                                 TargetLowering::DAGCombinerInfo &DCI,
443                                 const MipsSubtarget *Subtarget) {
444  if (!Subtarget->hasMSA())
445    return SDValue();
446
447  SDValue Op0 = N->getOperand(0);
448  SDValue Op1 = N->getOperand(1);
449  unsigned Op0Opcode = Op0->getOpcode();
450
451  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
452  // where $d + 1 == 2^n and n == 32
453  // or    $d + 1 == 2^n and n <= 32 and ZExt
454  // -> (MipsVExtractZExt $a, $b, $c)
455  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
456      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
457    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
458
459    if (!Mask)
460      return SDValue();
461
462    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
463
464    if (Log2IfPositive <= 0)
465      return SDValue(); // Mask+1 is not a power of 2
466
467    SDValue Op0Op2 = Op0->getOperand(2);
468    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
469    unsigned ExtendTySize = ExtendTy.getSizeInBits();
470    unsigned Log2 = Log2IfPositive;
471
472    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
473        Log2 == ExtendTySize) {
474      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
475      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
476                      Op0->getVTList(), Ops, Op0->getNumOperands());
477      return Op0;
478    }
479  }
480
481  return SDValue();
482}
483
484static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
485                                  TargetLowering::DAGCombinerInfo &DCI,
486                                  const MipsSubtarget *Subtarget) {
487  if (DCI.isBeforeLegalize())
488    return SDValue();
489
490  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
491      selectMSUB(N, &DAG))
492    return SDValue(N, 0);
493
494  return SDValue();
495}
496
497static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
498                            EVT ShiftTy, SelectionDAG &DAG) {
499  // Clear the upper (64 - VT.sizeInBits) bits.
500  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
501
502  // Return 0.
503  if (C == 0)
504    return DAG.getConstant(0, VT);
505
506  // Return x.
507  if (C == 1)
508    return X;
509
510  // If c is power of 2, return (shl x, log2(c)).
511  if (isPowerOf2_64(C))
512    return DAG.getNode(ISD::SHL, DL, VT, X,
513                       DAG.getConstant(Log2_64(C), ShiftTy));
514
515  unsigned Log2Ceil = Log2_64_Ceil(C);
516  uint64_t Floor = 1LL << Log2_64(C);
517  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
518
519  // If |c - floor_c| <= |c - ceil_c|,
520  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
521  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
522  if (C - Floor <= Ceil - C) {
523    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
524    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
525    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
526  }
527
528  // If |c - floor_c| > |c - ceil_c|,
529  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
530  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
531  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
532  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
533}
534
535static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
536                                 const TargetLowering::DAGCombinerInfo &DCI,
537                                 const MipsSETargetLowering *TL) {
538  EVT VT = N->getValueType(0);
539
540  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
541    if (!VT.isVector())
542      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
543                          VT, TL->getScalarShiftAmountTy(VT), DAG);
544
545  return SDValue(N, 0);
546}
547
548static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
549                                      SelectionDAG &DAG,
550                                      const MipsSubtarget *Subtarget) {
551  // See if this is a vector splat immediate node.
552  APInt SplatValue, SplatUndef;
553  unsigned SplatBitSize;
554  bool HasAnyUndefs;
555  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
556  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
557
558  if (!BV ||
559      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
560                           EltSize, !Subtarget->isLittle()) ||
561      (SplatBitSize != EltSize) ||
562      (SplatValue.getZExtValue() >= EltSize))
563    return SDValue();
564
565  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
566                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
567}
568
569static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
570                                 TargetLowering::DAGCombinerInfo &DCI,
571                                 const MipsSubtarget *Subtarget) {
572  EVT Ty = N->getValueType(0);
573
574  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
575    return SDValue();
576
577  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
578}
579
580// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
581// constant splats into MipsISD::SHRA_DSP for DSPr2.
582//
583// Performs the following transformations:
584// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
585//   sign/zero-extension is completely overwritten by the new one performed by
586//   the ISD::SRA and ISD::SHL nodes.
587// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
588//   sequence.
589//
590// See performDSPShiftCombine for more information about the transformation
591// used for DSPr2.
592static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
593                                 TargetLowering::DAGCombinerInfo &DCI,
594                                 const MipsSubtarget *Subtarget) {
595  EVT Ty = N->getValueType(0);
596
597  if (Subtarget->hasMSA()) {
598    SDValue Op0 = N->getOperand(0);
599    SDValue Op1 = N->getOperand(1);
600
601    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
602    // where $d + sizeof($c) == 32
603    // or    $d + sizeof($c) <= 32 and SExt
604    // -> (MipsVExtractSExt $a, $b, $c)
605    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
606      SDValue Op0Op0 = Op0->getOperand(0);
607      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
608
609      if (!ShAmount)
610        return SDValue();
611
612      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
613      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
614
615      if (TotalBits == 32 ||
616          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
617           TotalBits <= 32)) {
618        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
619                          Op0Op0->getOperand(2) };
620        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
621                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
622        return Op0Op0;
623      }
624    }
625  }
626
627  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
628    return SDValue();
629
630  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
631}
632
633
634static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
635                                 TargetLowering::DAGCombinerInfo &DCI,
636                                 const MipsSubtarget *Subtarget) {
637  EVT Ty = N->getValueType(0);
638
639  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
640    return SDValue();
641
642  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
643}
644
645static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
646  bool IsV216 = (Ty == MVT::v2i16);
647
648  switch (CC) {
649  case ISD::SETEQ:
650  case ISD::SETNE:  return true;
651  case ISD::SETLT:
652  case ISD::SETLE:
653  case ISD::SETGT:
654  case ISD::SETGE:  return IsV216;
655  case ISD::SETULT:
656  case ISD::SETULE:
657  case ISD::SETUGT:
658  case ISD::SETUGE: return !IsV216;
659  default:          return false;
660  }
661}
662
663static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
664  EVT Ty = N->getValueType(0);
665
666  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
667    return SDValue();
668
669  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
670    return SDValue();
671
672  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
673                     N->getOperand(1), N->getOperand(2));
674}
675
676static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
677  EVT Ty = N->getValueType(0);
678
679  if (Ty.is128BitVector() && Ty.isInteger()) {
680    // Try the following combines:
681    //   (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
682    //   (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
683    //   (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
684    //   (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
685    //   (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
686    //   (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
687    //   (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
688    //   (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
689    // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
690    // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
691    // legalizer.
692    SDValue Op0 = N->getOperand(0);
693
694    if (Op0->getOpcode() != ISD::SETCC)
695      return SDValue();
696
697    ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
698    bool Signed;
699
700    if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)
701      Signed = true;
702    else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
703      Signed = false;
704    else
705      return SDValue();
706
707    SDValue Op1 = N->getOperand(1);
708    SDValue Op2 = N->getOperand(2);
709    SDValue Op0Op0 = Op0->getOperand(0);
710    SDValue Op0Op1 = Op0->getOperand(1);
711
712    if (Op1 == Op0Op0 && Op2 == Op0Op1)
713      return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
714                         Ty, Op1, Op2);
715    else if (Op1 == Op0Op1 && Op2 == Op0Op0)
716      return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
717                         Ty, Op1, Op2);
718  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
719    SDValue SetCC = N->getOperand(0);
720
721    if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
722      return SDValue();
723
724    return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
725                       SetCC.getOperand(0), SetCC.getOperand(1),
726                       N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
727  }
728
729  return SDValue();
730}
731
732static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
733                                 const MipsSubtarget *Subtarget) {
734  EVT Ty = N->getValueType(0);
735
736  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
737    // Try the following combines:
738    //   (xor (or $a, $b), (build_vector allones))
739    //   (xor (or $a, $b), (bitcast (build_vector allones)))
740    SDValue Op0 = N->getOperand(0);
741    SDValue Op1 = N->getOperand(1);
742    SDValue NotOp;
743
744    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
745      NotOp = Op1;
746    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
747      NotOp = Op0;
748    else
749      return SDValue();
750
751    if (NotOp->getOpcode() == ISD::OR)
752      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
753                         NotOp->getOperand(1));
754  }
755
756  return SDValue();
757}
758
759SDValue
760MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
761  SelectionDAG &DAG = DCI.DAG;
762  SDValue Val;
763
764  switch (N->getOpcode()) {
765  case ISD::ADDE:
766    return performADDECombine(N, DAG, DCI, Subtarget);
767  case ISD::AND:
768    Val = performANDCombine(N, DAG, DCI, Subtarget);
769    break;
770  case ISD::SUBE:
771    return performSUBECombine(N, DAG, DCI, Subtarget);
772  case ISD::MUL:
773    return performMULCombine(N, DAG, DCI, this);
774  case ISD::SHL:
775    return performSHLCombine(N, DAG, DCI, Subtarget);
776  case ISD::SRA:
777    return performSRACombine(N, DAG, DCI, Subtarget);
778  case ISD::SRL:
779    return performSRLCombine(N, DAG, DCI, Subtarget);
780  case ISD::VSELECT:
781    return performVSELECTCombine(N, DAG);
782  case ISD::XOR:
783    Val = performXORCombine(N, DAG, Subtarget);
784    break;
785  case ISD::SETCC:
786    Val = performSETCCCombine(N, DAG);
787    break;
788  }
789
790  if (Val.getNode())
791    return Val;
792
793  return MipsTargetLowering::PerformDAGCombine(N, DCI);
794}
795
796MachineBasicBlock *
797MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
798                                                  MachineBasicBlock *BB) const {
799  switch (MI->getOpcode()) {
800  default:
801    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
802  case Mips::BPOSGE32_PSEUDO:
803    return emitBPOSGE32(MI, BB);
804  case Mips::SNZ_B_PSEUDO:
805    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
806  case Mips::SNZ_H_PSEUDO:
807    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
808  case Mips::SNZ_W_PSEUDO:
809    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
810  case Mips::SNZ_D_PSEUDO:
811    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
812  case Mips::SNZ_V_PSEUDO:
813    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
814  case Mips::SZ_B_PSEUDO:
815    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
816  case Mips::SZ_H_PSEUDO:
817    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
818  case Mips::SZ_W_PSEUDO:
819    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
820  case Mips::SZ_D_PSEUDO:
821    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
822  case Mips::SZ_V_PSEUDO:
823    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
824  }
825}
826
827bool MipsSETargetLowering::
828isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
829                                  unsigned NextStackOffset,
830                                  const MipsFunctionInfo& FI) const {
831  if (!EnableMipsTailCalls)
832    return false;
833
834  // Return false if either the callee or caller has a byval argument.
835  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
836    return false;
837
838  // Return true if the callee's argument area is no larger than the
839  // caller's.
840  return NextStackOffset <= FI.getIncomingArgSize();
841}
842
843void MipsSETargetLowering::
844getOpndList(SmallVectorImpl<SDValue> &Ops,
845            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
846            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
847            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
848  // T9 should contain the address of the callee function if
849  // -reloction-model=pic or it is an indirect call.
850  if (IsPICCall || !GlobalOrExternal) {
851    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
852    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
853  } else
854    Ops.push_back(Callee);
855
856  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
857                                  InternalLinkage, CLI, Callee, Chain);
858}
859
860SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
861  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
862
863  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
864    return MipsTargetLowering::lowerLOAD(Op, DAG);
865
866  // Replace a double precision load with two i32 loads and a buildpair64.
867  SDLoc DL(Op);
868  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
869  EVT PtrVT = Ptr.getValueType();
870
871  // i32 load from lower address.
872  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
873                           MachinePointerInfo(), Nd.isVolatile(),
874                           Nd.isNonTemporal(), Nd.isInvariant(),
875                           Nd.getAlignment());
876
877  // i32 load from higher address.
878  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
879  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
880                           MachinePointerInfo(), Nd.isVolatile(),
881                           Nd.isNonTemporal(), Nd.isInvariant(),
882                           std::min(Nd.getAlignment(), 4U));
883
884  if (!Subtarget->isLittle())
885    std::swap(Lo, Hi);
886
887  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
888  SDValue Ops[2] = {BP, Hi.getValue(1)};
889  return DAG.getMergeValues(Ops, 2, DL);
890}
891
892SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
893  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
894
895  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
896    return MipsTargetLowering::lowerSTORE(Op, DAG);
897
898  // Replace a double precision store with two extractelement64s and i32 stores.
899  SDLoc DL(Op);
900  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
901  EVT PtrVT = Ptr.getValueType();
902  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
903                           Val, DAG.getConstant(0, MVT::i32));
904  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
905                           Val, DAG.getConstant(1, MVT::i32));
906
907  if (!Subtarget->isLittle())
908    std::swap(Lo, Hi);
909
910  // i32 store to lower address.
911  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
912                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
913                       Nd.getTBAAInfo());
914
915  // i32 store to higher address.
916  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
917  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
918                      Nd.isVolatile(), Nd.isNonTemporal(),
919                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
920}
921
922SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
923                                          bool HasLo, bool HasHi,
924                                          SelectionDAG &DAG) const {
925  EVT Ty = Op.getOperand(0).getValueType();
926  SDLoc DL(Op);
927  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
928                             Op.getOperand(0), Op.getOperand(1));
929  SDValue Lo, Hi;
930
931  if (HasLo)
932    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
933                     DAG.getConstant(Mips::sub_lo, MVT::i32));
934  if (HasHi)
935    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
936                     DAG.getConstant(Mips::sub_hi, MVT::i32));
937
938  if (!HasLo || !HasHi)
939    return HasLo ? Lo : Hi;
940
941  SDValue Vals[] = { Lo, Hi };
942  return DAG.getMergeValues(Vals, 2, DL);
943}
944
945
946static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
947  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
948                             DAG.getConstant(0, MVT::i32));
949  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
950                             DAG.getConstant(1, MVT::i32));
951  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
952}
953
954static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
955  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
956                           DAG.getConstant(Mips::sub_lo, MVT::i32));
957  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
958                           DAG.getConstant(Mips::sub_hi, MVT::i32));
959  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
960}
961
962// This function expands mips intrinsic nodes which have 64-bit input operands
963// or output values.
964//
965// out64 = intrinsic-node in64
966// =>
967// lo = copy (extract-element (in64, 0))
968// hi = copy (extract-element (in64, 1))
969// mips-specific-node
970// v0 = copy lo
971// v1 = copy hi
972// out64 = merge-values (v0, v1)
973//
974static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
975  SDLoc DL(Op);
976  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
977  SmallVector<SDValue, 3> Ops;
978  unsigned OpNo = 0;
979
980  // See if Op has a chain input.
981  if (HasChainIn)
982    Ops.push_back(Op->getOperand(OpNo++));
983
984  // The next operand is the intrinsic opcode.
985  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
986
987  // See if the next operand has type i64.
988  SDValue Opnd = Op->getOperand(++OpNo), In64;
989
990  if (Opnd.getValueType() == MVT::i64)
991    In64 = initAccumulator(Opnd, DL, DAG);
992  else
993    Ops.push_back(Opnd);
994
995  // Push the remaining operands.
996  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
997    Ops.push_back(Op->getOperand(OpNo));
998
999  // Add In64 to the end of the list.
1000  if (In64.getNode())
1001    Ops.push_back(In64);
1002
1003  // Scan output.
1004  SmallVector<EVT, 2> ResTys;
1005
1006  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1007       I != E; ++I)
1008    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1009
1010  // Create node.
1011  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1012  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1013
1014  if (!HasChainIn)
1015    return Out;
1016
1017  assert(Val->getValueType(1) == MVT::Other);
1018  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1019  return DAG.getMergeValues(Vals, 2, DL);
1020}
1021
1022static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1023  SDLoc DL(Op);
1024  SDValue LHS = Op->getOperand(1);
1025  SDValue RHS = Op->getOperand(2);
1026  EVT ResTy = Op->getValueType(0);
1027
1028  SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
1029
1030  return Result;
1031}
1032
1033static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
1034                                     unsigned Opc, SDValue RHS) {
1035  SDValue LHS = Op->getOperand(1);
1036  EVT ResTy = Op->getValueType(0);
1037
1038  return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
1039}
1040
1041static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1042  SDLoc DL(Op);
1043  SDValue Value = Op->getOperand(1);
1044  EVT ResTy = Op->getValueType(0);
1045
1046  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1047
1048  return Result;
1049}
1050
1051// Lower an MSA copy intrinsic into the specified SelectionDAG node
1052static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1053  SDLoc DL(Op);
1054  SDValue Vec = Op->getOperand(1);
1055  SDValue Idx = Op->getOperand(2);
1056  EVT ResTy = Op->getValueType(0);
1057  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1058
1059  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1060                               DAG.getValueType(EltTy));
1061
1062  return Result;
1063}
1064
1065// Lower an MSA insert intrinsic into the specified SelectionDAG node
1066static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1067  SDLoc DL(Op);
1068  SDValue Op0 = Op->getOperand(1);
1069  SDValue Op1 = Op->getOperand(2);
1070  SDValue Op2 = Op->getOperand(3);
1071  EVT ResTy = Op->getValueType(0);
1072
1073  SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
1074
1075  return Result;
1076}
1077
1078static SDValue lowerMSASplatImm(SDValue Op, SDValue ImmOp, SelectionDAG &DAG) {
1079  EVT ResTy = Op->getValueType(0);
1080  EVT ViaVecTy = ResTy;
1081  SmallVector<SDValue, 16> Ops;
1082  SDValue ImmHiOp;
1083  SDLoc DL(Op);
1084
1085  if (ViaVecTy == MVT::v2i64) {
1086    ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1087                          DAG.getConstant(31, MVT::i32));
1088    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1089      Ops.push_back(ImmHiOp);
1090      Ops.push_back(ImmOp);
1091    }
1092    ViaVecTy = MVT::v4i32;
1093  } else {
1094    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1095      Ops.push_back(ImmOp);
1096  }
1097
1098  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1099                               Ops.size());
1100
1101  if (ResTy != ViaVecTy)
1102    Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1103
1104  return Result;
1105}
1106
1107static SDValue
1108lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1109  return lowerMSASplatImm(Op, Op->getOperand(ImmOp), DAG);
1110}
1111
1112static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1113  SDLoc DL(Op);
1114  SDValue Value = Op->getOperand(1);
1115  EVT ResTy = Op->getValueType(0);
1116
1117  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
1118
1119  return Result;
1120}
1121
1122SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1123                                                      SelectionDAG &DAG) const {
1124  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1125  default:
1126    return SDValue();
1127  case Intrinsic::mips_shilo:
1128    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1129  case Intrinsic::mips_dpau_h_qbl:
1130    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1131  case Intrinsic::mips_dpau_h_qbr:
1132    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1133  case Intrinsic::mips_dpsu_h_qbl:
1134    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1135  case Intrinsic::mips_dpsu_h_qbr:
1136    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1137  case Intrinsic::mips_dpa_w_ph:
1138    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1139  case Intrinsic::mips_dps_w_ph:
1140    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1141  case Intrinsic::mips_dpax_w_ph:
1142    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1143  case Intrinsic::mips_dpsx_w_ph:
1144    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1145  case Intrinsic::mips_mulsa_w_ph:
1146    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1147  case Intrinsic::mips_mult:
1148    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1149  case Intrinsic::mips_multu:
1150    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1151  case Intrinsic::mips_madd:
1152    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1153  case Intrinsic::mips_maddu:
1154    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1155  case Intrinsic::mips_msub:
1156    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1157  case Intrinsic::mips_msubu:
1158    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1159  case Intrinsic::mips_addv_b:
1160  case Intrinsic::mips_addv_h:
1161  case Intrinsic::mips_addv_w:
1162  case Intrinsic::mips_addv_d:
1163    return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
1164  case Intrinsic::mips_addvi_b:
1165  case Intrinsic::mips_addvi_h:
1166  case Intrinsic::mips_addvi_w:
1167  case Intrinsic::mips_addvi_d:
1168    return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
1169                                 lowerMSASplatImm(Op, 2, DAG));
1170  case Intrinsic::mips_and_v:
1171    return lowerMSABinaryIntr(Op, DAG, ISD::AND);
1172  case Intrinsic::mips_andi_b:
1173    return lowerMSABinaryImmIntr(Op, DAG, ISD::AND,
1174                                 lowerMSASplatImm(Op, 2, DAG));
1175  case Intrinsic::mips_bnz_b:
1176  case Intrinsic::mips_bnz_h:
1177  case Intrinsic::mips_bnz_w:
1178  case Intrinsic::mips_bnz_d:
1179    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
1180  case Intrinsic::mips_bnz_v:
1181    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
1182  case Intrinsic::mips_bsel_v:
1183    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1184                       Op->getOperand(1), Op->getOperand(2),
1185                       Op->getOperand(3));
1186  case Intrinsic::mips_bseli_b:
1187    return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
1188                       Op->getOperand(1), Op->getOperand(2),
1189                       lowerMSASplatImm(Op, 3, DAG));
1190  case Intrinsic::mips_bz_b:
1191  case Intrinsic::mips_bz_h:
1192  case Intrinsic::mips_bz_w:
1193  case Intrinsic::mips_bz_d:
1194    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
1195  case Intrinsic::mips_bz_v:
1196    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
1197  case Intrinsic::mips_ceq_b:
1198  case Intrinsic::mips_ceq_h:
1199  case Intrinsic::mips_ceq_w:
1200  case Intrinsic::mips_ceq_d:
1201    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1202                        Op->getOperand(2), ISD::SETEQ);
1203  case Intrinsic::mips_ceqi_b:
1204  case Intrinsic::mips_ceqi_h:
1205  case Intrinsic::mips_ceqi_w:
1206  case Intrinsic::mips_ceqi_d:
1207    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1208                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1209  case Intrinsic::mips_cle_s_b:
1210  case Intrinsic::mips_cle_s_h:
1211  case Intrinsic::mips_cle_s_w:
1212  case Intrinsic::mips_cle_s_d:
1213    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1214                        Op->getOperand(2), ISD::SETLE);
1215  case Intrinsic::mips_clei_s_b:
1216  case Intrinsic::mips_clei_s_h:
1217  case Intrinsic::mips_clei_s_w:
1218  case Intrinsic::mips_clei_s_d:
1219    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1220                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1221  case Intrinsic::mips_cle_u_b:
1222  case Intrinsic::mips_cle_u_h:
1223  case Intrinsic::mips_cle_u_w:
1224  case Intrinsic::mips_cle_u_d:
1225    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1226                        Op->getOperand(2), ISD::SETULE);
1227  case Intrinsic::mips_clei_u_b:
1228  case Intrinsic::mips_clei_u_h:
1229  case Intrinsic::mips_clei_u_w:
1230  case Intrinsic::mips_clei_u_d:
1231    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1232                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1233  case Intrinsic::mips_clt_s_b:
1234  case Intrinsic::mips_clt_s_h:
1235  case Intrinsic::mips_clt_s_w:
1236  case Intrinsic::mips_clt_s_d:
1237    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1238                        Op->getOperand(2), ISD::SETLT);
1239  case Intrinsic::mips_clti_s_b:
1240  case Intrinsic::mips_clti_s_h:
1241  case Intrinsic::mips_clti_s_w:
1242  case Intrinsic::mips_clti_s_d:
1243    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1244                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1245  case Intrinsic::mips_clt_u_b:
1246  case Intrinsic::mips_clt_u_h:
1247  case Intrinsic::mips_clt_u_w:
1248  case Intrinsic::mips_clt_u_d:
1249    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1250                        Op->getOperand(2), ISD::SETULT);
1251  case Intrinsic::mips_clti_u_b:
1252  case Intrinsic::mips_clti_u_h:
1253  case Intrinsic::mips_clti_u_w:
1254  case Intrinsic::mips_clti_u_d:
1255    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1256                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1257  case Intrinsic::mips_copy_s_b:
1258  case Intrinsic::mips_copy_s_h:
1259  case Intrinsic::mips_copy_s_w:
1260    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1261  case Intrinsic::mips_copy_u_b:
1262  case Intrinsic::mips_copy_u_h:
1263  case Intrinsic::mips_copy_u_w:
1264    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1265  case Intrinsic::mips_div_s_b:
1266  case Intrinsic::mips_div_s_h:
1267  case Intrinsic::mips_div_s_w:
1268  case Intrinsic::mips_div_s_d:
1269    return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
1270  case Intrinsic::mips_div_u_b:
1271  case Intrinsic::mips_div_u_h:
1272  case Intrinsic::mips_div_u_w:
1273  case Intrinsic::mips_div_u_d:
1274    return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
1275  case Intrinsic::mips_fadd_w:
1276  case Intrinsic::mips_fadd_d:
1277    return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
1278  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1279  case Intrinsic::mips_fceq_w:
1280  case Intrinsic::mips_fceq_d:
1281    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1282                        Op->getOperand(2), ISD::SETOEQ);
1283  case Intrinsic::mips_fcle_w:
1284  case Intrinsic::mips_fcle_d:
1285    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1286                        Op->getOperand(2), ISD::SETOLE);
1287  case Intrinsic::mips_fclt_w:
1288  case Intrinsic::mips_fclt_d:
1289    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1290                        Op->getOperand(2), ISD::SETOLT);
1291  case Intrinsic::mips_fcne_w:
1292  case Intrinsic::mips_fcne_d:
1293    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1294                        Op->getOperand(2), ISD::SETONE);
1295  case Intrinsic::mips_fcor_w:
1296  case Intrinsic::mips_fcor_d:
1297    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1298                        Op->getOperand(2), ISD::SETO);
1299  case Intrinsic::mips_fcueq_w:
1300  case Intrinsic::mips_fcueq_d:
1301    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1302                        Op->getOperand(2), ISD::SETUEQ);
1303  case Intrinsic::mips_fcule_w:
1304  case Intrinsic::mips_fcule_d:
1305    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1306                        Op->getOperand(2), ISD::SETULE);
1307  case Intrinsic::mips_fcult_w:
1308  case Intrinsic::mips_fcult_d:
1309    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1310                        Op->getOperand(2), ISD::SETULT);
1311  case Intrinsic::mips_fcun_w:
1312  case Intrinsic::mips_fcun_d:
1313    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1314                        Op->getOperand(2), ISD::SETUO);
1315  case Intrinsic::mips_fcune_w:
1316  case Intrinsic::mips_fcune_d:
1317    return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
1318                        Op->getOperand(2), ISD::SETUNE);
1319  case Intrinsic::mips_fdiv_w:
1320  case Intrinsic::mips_fdiv_d:
1321    return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
1322  case Intrinsic::mips_fill_b:
1323  case Intrinsic::mips_fill_h:
1324  case Intrinsic::mips_fill_w: {
1325    SmallVector<SDValue, 16> Ops;
1326    EVT ResTy = Op->getValueType(0);
1327
1328    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1329      Ops.push_back(Op->getOperand(1));
1330
1331    return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), ResTy, &Ops[0],
1332                       Ops.size());
1333  }
1334  case Intrinsic::mips_flog2_w:
1335  case Intrinsic::mips_flog2_d:
1336    return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
1337  case Intrinsic::mips_fmul_w:
1338  case Intrinsic::mips_fmul_d:
1339    return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
1340  case Intrinsic::mips_frint_w:
1341  case Intrinsic::mips_frint_d:
1342    return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
1343  case Intrinsic::mips_fsqrt_w:
1344  case Intrinsic::mips_fsqrt_d:
1345    return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
1346  case Intrinsic::mips_fsub_w:
1347  case Intrinsic::mips_fsub_d:
1348    return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
1349  case Intrinsic::mips_ilvev_b:
1350  case Intrinsic::mips_ilvev_h:
1351  case Intrinsic::mips_ilvev_w:
1352  case Intrinsic::mips_ilvev_d:
1353    return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), Op->getValueType(0),
1354                       Op->getOperand(1), Op->getOperand(2));
1355  case Intrinsic::mips_ilvl_b:
1356  case Intrinsic::mips_ilvl_h:
1357  case Intrinsic::mips_ilvl_w:
1358  case Intrinsic::mips_ilvl_d:
1359    return DAG.getNode(MipsISD::ILVL, SDLoc(Op), Op->getValueType(0),
1360                       Op->getOperand(1), Op->getOperand(2));
1361  case Intrinsic::mips_ilvod_b:
1362  case Intrinsic::mips_ilvod_h:
1363  case Intrinsic::mips_ilvod_w:
1364  case Intrinsic::mips_ilvod_d:
1365    return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), Op->getValueType(0),
1366                       Op->getOperand(1), Op->getOperand(2));
1367  case Intrinsic::mips_ilvr_b:
1368  case Intrinsic::mips_ilvr_h:
1369  case Intrinsic::mips_ilvr_w:
1370  case Intrinsic::mips_ilvr_d:
1371    return DAG.getNode(MipsISD::ILVR, SDLoc(Op), Op->getValueType(0),
1372                       Op->getOperand(1), Op->getOperand(2));
1373  case Intrinsic::mips_insert_b:
1374  case Intrinsic::mips_insert_h:
1375  case Intrinsic::mips_insert_w:
1376    return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
1377  case Intrinsic::mips_ldi_b:
1378  case Intrinsic::mips_ldi_h:
1379  case Intrinsic::mips_ldi_w:
1380  case Intrinsic::mips_ldi_d:
1381    return lowerMSASplatImm(Op, 1, DAG);
1382  case Intrinsic::mips_max_s_b:
1383  case Intrinsic::mips_max_s_h:
1384  case Intrinsic::mips_max_s_w:
1385  case Intrinsic::mips_max_s_d:
1386    return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMAX);
1387  case Intrinsic::mips_max_u_b:
1388  case Intrinsic::mips_max_u_h:
1389  case Intrinsic::mips_max_u_w:
1390  case Intrinsic::mips_max_u_d:
1391    return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMAX);
1392  case Intrinsic::mips_maxi_s_b:
1393  case Intrinsic::mips_maxi_s_h:
1394  case Intrinsic::mips_maxi_s_w:
1395  case Intrinsic::mips_maxi_s_d:
1396    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMAX,
1397                                 lowerMSASplatImm(Op, 2, DAG));
1398  case Intrinsic::mips_maxi_u_b:
1399  case Intrinsic::mips_maxi_u_h:
1400  case Intrinsic::mips_maxi_u_w:
1401  case Intrinsic::mips_maxi_u_d:
1402    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMAX,
1403                                 lowerMSASplatImm(Op, 2, DAG));
1404  case Intrinsic::mips_min_s_b:
1405  case Intrinsic::mips_min_s_h:
1406  case Intrinsic::mips_min_s_w:
1407  case Intrinsic::mips_min_s_d:
1408    return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMIN);
1409  case Intrinsic::mips_min_u_b:
1410  case Intrinsic::mips_min_u_h:
1411  case Intrinsic::mips_min_u_w:
1412  case Intrinsic::mips_min_u_d:
1413    return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMIN);
1414  case Intrinsic::mips_mini_s_b:
1415  case Intrinsic::mips_mini_s_h:
1416  case Intrinsic::mips_mini_s_w:
1417  case Intrinsic::mips_mini_s_d:
1418    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMIN,
1419                                 lowerMSASplatImm(Op, 2, DAG));
1420  case Intrinsic::mips_mini_u_b:
1421  case Intrinsic::mips_mini_u_h:
1422  case Intrinsic::mips_mini_u_w:
1423  case Intrinsic::mips_mini_u_d:
1424    return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMIN,
1425                                 lowerMSASplatImm(Op, 2, DAG));
1426  case Intrinsic::mips_mulv_b:
1427  case Intrinsic::mips_mulv_h:
1428  case Intrinsic::mips_mulv_w:
1429  case Intrinsic::mips_mulv_d:
1430    return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
1431  case Intrinsic::mips_nlzc_b:
1432  case Intrinsic::mips_nlzc_h:
1433  case Intrinsic::mips_nlzc_w:
1434  case Intrinsic::mips_nlzc_d:
1435    return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
1436  case Intrinsic::mips_nor_v: {
1437    SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
1438    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1439  }
1440  case Intrinsic::mips_nori_b: {
1441    SDValue Res = lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
1442                                        lowerMSASplatImm(Op, 2, DAG));
1443    return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
1444  }
1445  case Intrinsic::mips_or_v:
1446    return lowerMSABinaryIntr(Op, DAG, ISD::OR);
1447  case Intrinsic::mips_ori_b:
1448    return lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
1449                                 lowerMSASplatImm(Op, 2, DAG));
1450  case Intrinsic::mips_pcnt_b:
1451  case Intrinsic::mips_pcnt_h:
1452  case Intrinsic::mips_pcnt_w:
1453  case Intrinsic::mips_pcnt_d:
1454    return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
1455  case Intrinsic::mips_shf_b:
1456  case Intrinsic::mips_shf_h:
1457  case Intrinsic::mips_shf_w:
1458    return DAG.getNode(MipsISD::SHF, SDLoc(Op), Op->getValueType(0),
1459                       Op->getOperand(2), Op->getOperand(1));
1460  case Intrinsic::mips_sll_b:
1461  case Intrinsic::mips_sll_h:
1462  case Intrinsic::mips_sll_w:
1463  case Intrinsic::mips_sll_d:
1464    return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
1465  case Intrinsic::mips_slli_b:
1466  case Intrinsic::mips_slli_h:
1467  case Intrinsic::mips_slli_w:
1468  case Intrinsic::mips_slli_d:
1469    return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
1470                                 lowerMSASplatImm(Op, 2, DAG));
1471  case Intrinsic::mips_sra_b:
1472  case Intrinsic::mips_sra_h:
1473  case Intrinsic::mips_sra_w:
1474  case Intrinsic::mips_sra_d:
1475    return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
1476  case Intrinsic::mips_srai_b:
1477  case Intrinsic::mips_srai_h:
1478  case Intrinsic::mips_srai_w:
1479  case Intrinsic::mips_srai_d:
1480    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
1481                                 lowerMSASplatImm(Op, 2, DAG));
1482  case Intrinsic::mips_srl_b:
1483  case Intrinsic::mips_srl_h:
1484  case Intrinsic::mips_srl_w:
1485  case Intrinsic::mips_srl_d:
1486    return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
1487  case Intrinsic::mips_srli_b:
1488  case Intrinsic::mips_srli_h:
1489  case Intrinsic::mips_srli_w:
1490  case Intrinsic::mips_srli_d:
1491    return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
1492                                 lowerMSASplatImm(Op, 2, DAG));
1493  case Intrinsic::mips_subv_b:
1494  case Intrinsic::mips_subv_h:
1495  case Intrinsic::mips_subv_w:
1496  case Intrinsic::mips_subv_d:
1497    return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
1498  case Intrinsic::mips_subvi_b:
1499  case Intrinsic::mips_subvi_h:
1500  case Intrinsic::mips_subvi_w:
1501  case Intrinsic::mips_subvi_d:
1502    return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
1503                                 lowerMSASplatImm(Op, 2, DAG));
1504  case Intrinsic::mips_vshf_b:
1505  case Intrinsic::mips_vshf_h:
1506  case Intrinsic::mips_vshf_w:
1507  case Intrinsic::mips_vshf_d:
1508    return DAG.getNode(MipsISD::VSHF, SDLoc(Op), Op->getValueType(0),
1509                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1510  case Intrinsic::mips_xor_v:
1511    return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
1512  case Intrinsic::mips_xori_b:
1513    return lowerMSABinaryImmIntr(Op, DAG, ISD::XOR,
1514                                 lowerMSASplatImm(Op, 2, DAG));
1515  }
1516}
1517
1518static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1519  SDLoc DL(Op);
1520  SDValue ChainIn = Op->getOperand(0);
1521  SDValue Address = Op->getOperand(2);
1522  SDValue Offset  = Op->getOperand(3);
1523  EVT ResTy = Op->getValueType(0);
1524  EVT PtrTy = Address->getValueType(0);
1525
1526  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1527
1528  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1529                     false, false, 16);
1530}
1531
1532SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1533                                                     SelectionDAG &DAG) const {
1534  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1535  switch (Intr) {
1536  default:
1537    return SDValue();
1538  case Intrinsic::mips_extp:
1539    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1540  case Intrinsic::mips_extpdp:
1541    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1542  case Intrinsic::mips_extr_w:
1543    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1544  case Intrinsic::mips_extr_r_w:
1545    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1546  case Intrinsic::mips_extr_rs_w:
1547    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1548  case Intrinsic::mips_extr_s_h:
1549    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1550  case Intrinsic::mips_mthlip:
1551    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1552  case Intrinsic::mips_mulsaq_s_w_ph:
1553    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1554  case Intrinsic::mips_maq_s_w_phl:
1555    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1556  case Intrinsic::mips_maq_s_w_phr:
1557    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1558  case Intrinsic::mips_maq_sa_w_phl:
1559    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1560  case Intrinsic::mips_maq_sa_w_phr:
1561    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1562  case Intrinsic::mips_dpaq_s_w_ph:
1563    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1564  case Intrinsic::mips_dpsq_s_w_ph:
1565    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1566  case Intrinsic::mips_dpaq_sa_l_w:
1567    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1568  case Intrinsic::mips_dpsq_sa_l_w:
1569    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1570  case Intrinsic::mips_dpaqx_s_w_ph:
1571    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1572  case Intrinsic::mips_dpaqx_sa_w_ph:
1573    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1574  case Intrinsic::mips_dpsqx_s_w_ph:
1575    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1576  case Intrinsic::mips_dpsqx_sa_w_ph:
1577    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1578  case Intrinsic::mips_ld_b:
1579  case Intrinsic::mips_ld_h:
1580  case Intrinsic::mips_ld_w:
1581  case Intrinsic::mips_ld_d:
1582  case Intrinsic::mips_ldx_b:
1583  case Intrinsic::mips_ldx_h:
1584  case Intrinsic::mips_ldx_w:
1585  case Intrinsic::mips_ldx_d:
1586   return lowerMSALoadIntr(Op, DAG, Intr);
1587  }
1588}
1589
1590static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1591  SDLoc DL(Op);
1592  SDValue ChainIn = Op->getOperand(0);
1593  SDValue Value   = Op->getOperand(2);
1594  SDValue Address = Op->getOperand(3);
1595  SDValue Offset  = Op->getOperand(4);
1596  EVT PtrTy = Address->getValueType(0);
1597
1598  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1599
1600  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1601                      false, 16);
1602}
1603
1604SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1605                                                  SelectionDAG &DAG) const {
1606  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1607  switch (Intr) {
1608  default:
1609    return SDValue();
1610  case Intrinsic::mips_st_b:
1611  case Intrinsic::mips_st_h:
1612  case Intrinsic::mips_st_w:
1613  case Intrinsic::mips_st_d:
1614  case Intrinsic::mips_stx_b:
1615  case Intrinsic::mips_stx_h:
1616  case Intrinsic::mips_stx_w:
1617  case Intrinsic::mips_stx_d:
1618    return lowerMSAStoreIntr(Op, DAG, Intr);
1619  }
1620}
1621
1622/// \brief Check if the given BuildVectorSDNode is a splat.
1623/// This method currently relies on DAG nodes being reused when equivalent,
1624/// so it's possible for this to return false even when isConstantSplat returns
1625/// true.
1626static bool isSplatVector(const BuildVectorSDNode *N) {
1627  unsigned int nOps = N->getNumOperands();
1628  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1629
1630  SDValue Operand0 = N->getOperand(0);
1631
1632  for (unsigned int i = 1; i < nOps; ++i) {
1633    if (N->getOperand(i) != Operand0)
1634      return false;
1635  }
1636
1637  return true;
1638}
1639
1640// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1641//
1642// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1643// choose to sign-extend but we could have equally chosen zero-extend. The
1644// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1645// result into this node later (possibly changing it to a zero-extend in the
1646// process).
1647SDValue MipsSETargetLowering::
1648lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1649  SDLoc DL(Op);
1650  EVT ResTy = Op->getValueType(0);
1651  SDValue Op0 = Op->getOperand(0);
1652  SDValue Op1 = Op->getOperand(1);
1653  EVT EltTy = Op0->getValueType(0).getVectorElementType();
1654  return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1655                     DAG.getValueType(EltTy));
1656}
1657
1658static bool isConstantOrUndef(const SDValue Op) {
1659  if (Op->getOpcode() == ISD::UNDEF)
1660    return true;
1661  if (dyn_cast<ConstantSDNode>(Op))
1662    return true;
1663  if (dyn_cast<ConstantFPSDNode>(Op))
1664    return true;
1665  return false;
1666}
1667
1668static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1669  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1670    if (isConstantOrUndef(Op->getOperand(i)))
1671      return true;
1672  return false;
1673}
1674
1675// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1676// backend.
1677//
1678// Lowers according to the following rules:
1679// - Constant splats are legal as-is as long as the SplatBitSize is a power of
1680//   2 less than or equal to 64 and the value fits into a signed 10-bit
1681//   immediate
1682// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1683//   is a power of 2 less than or equal to 64 and the value does not fit into a
1684//   signed 10-bit immediate
1685// - Non-constant splats are legal as-is.
1686// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1687// - All others are illegal and must be expanded.
1688SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1689                                                SelectionDAG &DAG) const {
1690  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1691  EVT ResTy = Op->getValueType(0);
1692  SDLoc DL(Op);
1693  APInt SplatValue, SplatUndef;
1694  unsigned SplatBitSize;
1695  bool HasAnyUndefs;
1696
1697  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1698    return SDValue();
1699
1700  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1701                            HasAnyUndefs, 8,
1702                            !Subtarget->isLittle()) && SplatBitSize <= 64) {
1703    // We can only cope with 8, 16, 32, or 64-bit elements
1704    if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1705        SplatBitSize != 64)
1706      return SDValue();
1707
1708    // If the value fits into a simm10 then we can use ldi.[bhwd]
1709    if (SplatValue.isSignedIntN(10))
1710      return Op;
1711
1712    EVT ViaVecTy;
1713
1714    switch (SplatBitSize) {
1715    default:
1716      return SDValue();
1717    case 8:
1718      ViaVecTy = MVT::v16i8;
1719      break;
1720    case 16:
1721      ViaVecTy = MVT::v8i16;
1722      break;
1723    case 32:
1724      ViaVecTy = MVT::v4i32;
1725      break;
1726    case 64:
1727      // There's no fill.d to fall back on for 64-bit values
1728      return SDValue();
1729    }
1730
1731    SmallVector<SDValue, 16> Ops;
1732    SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1733
1734    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1735      Ops.push_back(Constant);
1736
1737    SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1738                                 &Ops[0], Ops.size());
1739
1740    if (ViaVecTy != ResTy)
1741      Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1742
1743    return Result;
1744  } else if (isSplatVector(Node))
1745    return Op;
1746  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1747    // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1748    // The resulting code is the same length as the expansion, but it doesn't
1749    // use memory operations
1750    EVT ResTy = Node->getValueType(0);
1751
1752    assert(ResTy.isVector());
1753
1754    unsigned NumElts = ResTy.getVectorNumElements();
1755    SDValue Vector = DAG.getUNDEF(ResTy);
1756    for (unsigned i = 0; i < NumElts; ++i) {
1757      Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1758                           Node->getOperand(i),
1759                           DAG.getConstant(i, MVT::i32));
1760    }
1761    return Vector;
1762  }
1763
1764  return SDValue();
1765}
1766
1767// Lower VECTOR_SHUFFLE into SHF (if possible).
1768//
1769// SHF splits the vector into blocks of four elements, then shuffles these
1770// elements according to a <4 x i2> constant (encoded as an integer immediate).
1771//
1772// It is therefore possible to lower into SHF when the mask takes the form:
1773//   <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
1774// When undef's appear they are treated as if they were whatever value is
1775// necessary in order to fit the above form.
1776//
1777// For example:
1778//   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
1779//                      <8 x i32> <i32 3, i32 2, i32 1, i32 0,
1780//                                 i32 7, i32 6, i32 5, i32 4>
1781// is lowered to:
1782//   (SHF_H $w0, $w1, 27)
1783// where the 27 comes from:
1784//   3 + (2 << 2) + (1 << 4) + (0 << 6)
1785static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
1786                                       SmallVector<int, 16> Indices,
1787                                       SelectionDAG &DAG) {
1788  int SHFIndices[4] = { -1, -1, -1, -1 };
1789
1790  if (Indices.size() < 4)
1791    return SDValue();
1792
1793  for (unsigned i = 0; i < 4; ++i) {
1794    for (unsigned j = i; j < Indices.size(); j += 4) {
1795      int Idx = Indices[j];
1796
1797      // Convert from vector index to 4-element subvector index
1798      // If an index refers to an element outside of the subvector then give up
1799      if (Idx != -1) {
1800        Idx -= 4 * (j / 4);
1801        if (Idx < 0 || Idx >= 4)
1802          return SDValue();
1803      }
1804
1805      // If the mask has an undef, replace it with the current index.
1806      // Note that it might still be undef if the current index is also undef
1807      if (SHFIndices[i] == -1)
1808        SHFIndices[i] = Idx;
1809
1810      // Check that non-undef values are the same as in the mask. If they
1811      // aren't then give up
1812      if (!(Idx == -1 || Idx == SHFIndices[i]))
1813        return SDValue();
1814    }
1815  }
1816
1817  // Calculate the immediate. Replace any remaining undefs with zero
1818  APInt Imm(32, 0);
1819  for (int i = 3; i >= 0; --i) {
1820    int Idx = SHFIndices[i];
1821
1822    if (Idx == -1)
1823      Idx = 0;
1824
1825    Imm <<= 2;
1826    Imm |= Idx & 0x3;
1827  }
1828
1829  return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
1830                     DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
1831}
1832
1833// Lower VECTOR_SHUFFLE into ILVEV (if possible).
1834//
1835// ILVEV interleaves the even elements from each vector.
1836//
1837// It is possible to lower into ILVEV when the mask takes the form:
1838//   <0, n, 2, n+2, 4, n+4, ...>
1839// where n is the number of elements in the vector.
1840//
1841// When undef's appear in the mask they are treated as if they were whatever
1842// value is necessary in order to fit the above form.
1843static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
1844                                         SmallVector<int, 16> Indices,
1845                                         SelectionDAG &DAG) {
1846  assert ((Indices.size() % 2) == 0);
1847  int WsIdx = 0;
1848  int WtIdx = ResTy.getVectorNumElements();
1849
1850  for (unsigned i = 0; i < Indices.size(); i += 2) {
1851    if (Indices[i] != -1 && Indices[i] != WsIdx)
1852      return SDValue();
1853    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1854      return SDValue();
1855    WsIdx += 2;
1856    WtIdx += 2;
1857  }
1858
1859  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
1860                     Op->getOperand(1));
1861}
1862
1863// Lower VECTOR_SHUFFLE into ILVOD (if possible).
1864//
1865// ILVOD interleaves the odd elements from each vector.
1866//
1867// It is possible to lower into ILVOD when the mask takes the form:
1868//   <1, n+1, 3, n+3, 5, n+5, ...>
1869// where n is the number of elements in the vector.
1870//
1871// When undef's appear in the mask they are treated as if they were whatever
1872// value is necessary in order to fit the above form.
1873static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
1874                                         SmallVector<int, 16> Indices,
1875                                         SelectionDAG &DAG) {
1876  assert ((Indices.size() % 2) == 0);
1877  int WsIdx = 1;
1878  int WtIdx = ResTy.getVectorNumElements() + 1;
1879
1880  for (unsigned i = 0; i < Indices.size(); i += 2) {
1881    if (Indices[i] != -1 && Indices[i] != WsIdx)
1882      return SDValue();
1883    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1884      return SDValue();
1885    WsIdx += 2;
1886    WtIdx += 2;
1887  }
1888
1889  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
1890                     Op->getOperand(1));
1891}
1892
1893// Lower VECTOR_SHUFFLE into ILVL (if possible).
1894//
1895// ILVL interleaves consecutive elements from the left half of each vector.
1896//
1897// It is possible to lower into ILVL when the mask takes the form:
1898//   <0, n, 1, n+1, 2, n+2, ...>
1899// where n is the number of elements in the vector.
1900//
1901// When undef's appear in the mask they are treated as if they were whatever
1902// value is necessary in order to fit the above form.
1903static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
1904                                        SmallVector<int, 16> Indices,
1905                                        SelectionDAG &DAG) {
1906  assert ((Indices.size() % 2) == 0);
1907  int WsIdx = 0;
1908  int WtIdx = ResTy.getVectorNumElements();
1909
1910  for (unsigned i = 0; i < Indices.size(); i += 2) {
1911    if (Indices[i] != -1 && Indices[i] != WsIdx)
1912      return SDValue();
1913    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1914      return SDValue();
1915    WsIdx ++;
1916    WtIdx ++;
1917  }
1918
1919  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
1920                     Op->getOperand(1));
1921}
1922
1923// Lower VECTOR_SHUFFLE into ILVR (if possible).
1924//
1925// ILVR interleaves consecutive elements from the right half of each vector.
1926//
1927// It is possible to lower into ILVR when the mask takes the form:
1928//   <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
1929// where n is the number of elements in the vector and x is half n.
1930//
1931// When undef's appear in the mask they are treated as if they were whatever
1932// value is necessary in order to fit the above form.
1933static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
1934                                        SmallVector<int, 16> Indices,
1935                                        SelectionDAG &DAG) {
1936  assert ((Indices.size() % 2) == 0);
1937  unsigned NumElts = ResTy.getVectorNumElements();
1938  int WsIdx = NumElts / 2;
1939  int WtIdx = NumElts + NumElts / 2;
1940
1941  for (unsigned i = 0; i < Indices.size(); i += 2) {
1942    if (Indices[i] != -1 && Indices[i] != WsIdx)
1943      return SDValue();
1944    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1945      return SDValue();
1946    WsIdx ++;
1947    WtIdx ++;
1948  }
1949
1950  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
1951                     Op->getOperand(1));
1952}
1953
1954// Lower VECTOR_SHUFFLE into VSHF.
1955//
1956// This mostly consists of converting the shuffle indices in Indices into a
1957// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
1958// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
1959// if the type is v8i16 and all the indices are less than 8 then the second
1960// operand is unused and can be replaced with anything. We choose to replace it
1961// with the used operand since this reduces the number of instructions overall.
1962static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
1963                                        SmallVector<int, 16> Indices,
1964                                        SelectionDAG &DAG) {
1965  SmallVector<SDValue, 16> Ops;
1966  SDValue Op0;
1967  SDValue Op1;
1968  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
1969  EVT MaskEltTy = MaskVecTy.getVectorElementType();
1970  bool Using1stVec = false;
1971  bool Using2ndVec = false;
1972  SDLoc DL(Op);
1973  int ResTyNumElts = ResTy.getVectorNumElements();
1974
1975  for (int i = 0; i < ResTyNumElts; ++i) {
1976    // Idx == -1 means UNDEF
1977    int Idx = Indices[i];
1978
1979    if (0 <= Idx && Idx < ResTyNumElts)
1980      Using1stVec = true;
1981    if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
1982      Using2ndVec = true;
1983  }
1984
1985  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
1986       ++I)
1987    Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
1988
1989  SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
1990                                Ops.size());
1991
1992  if (Using1stVec && Using2ndVec) {
1993    Op0 = Op->getOperand(0);
1994    Op1 = Op->getOperand(1);
1995  } else if (Using1stVec)
1996    Op0 = Op1 = Op->getOperand(0);
1997  else if (Using2ndVec)
1998    Op0 = Op1 = Op->getOperand(1);
1999  else
2000    llvm_unreachable("shuffle vector mask references neither vector operand?");
2001
2002  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2003}
2004
2005// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2006// indices in the shuffle.
2007SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2008                                                  SelectionDAG &DAG) const {
2009  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2010  EVT ResTy = Op->getValueType(0);
2011
2012  if (!ResTy.is128BitVector())
2013    return SDValue();
2014
2015  int ResTyNumElts = ResTy.getVectorNumElements();
2016  SmallVector<int, 16> Indices;
2017
2018  for (int i = 0; i < ResTyNumElts; ++i)
2019    Indices.push_back(Node->getMaskElt(i));
2020
2021  SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2022  if (Result.getNode())
2023    return Result;
2024  Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2025  if (Result.getNode())
2026    return Result;
2027  Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2028  if (Result.getNode())
2029    return Result;
2030  Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2031  if (Result.getNode())
2032    return Result;
2033  Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2034  if (Result.getNode())
2035    return Result;
2036  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2037}
2038
2039MachineBasicBlock * MipsSETargetLowering::
2040emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2041  // $bb:
2042  //  bposge32_pseudo $vr0
2043  //  =>
2044  // $bb:
2045  //  bposge32 $tbb
2046  // $fbb:
2047  //  li $vr2, 0
2048  //  b $sink
2049  // $tbb:
2050  //  li $vr1, 1
2051  // $sink:
2052  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2053
2054  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2055  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2056  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2057  DebugLoc DL = MI->getDebugLoc();
2058  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2059  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2060  MachineFunction *F = BB->getParent();
2061  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2062  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2063  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2064  F->insert(It, FBB);
2065  F->insert(It, TBB);
2066  F->insert(It, Sink);
2067
2068  // Transfer the remainder of BB and its successor edges to Sink.
2069  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2070               BB->end());
2071  Sink->transferSuccessorsAndUpdatePHIs(BB);
2072
2073  // Add successors.
2074  BB->addSuccessor(FBB);
2075  BB->addSuccessor(TBB);
2076  FBB->addSuccessor(Sink);
2077  TBB->addSuccessor(Sink);
2078
2079  // Insert the real bposge32 instruction to $BB.
2080  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2081
2082  // Fill $FBB.
2083  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2084  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2085    .addReg(Mips::ZERO).addImm(0);
2086  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2087
2088  // Fill $TBB.
2089  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2090  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2091    .addReg(Mips::ZERO).addImm(1);
2092
2093  // Insert phi function to $Sink.
2094  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2095          MI->getOperand(0).getReg())
2096    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2097
2098  MI->eraseFromParent();   // The pseudo instruction is gone now.
2099  return Sink;
2100}
2101
2102MachineBasicBlock * MipsSETargetLowering::
2103emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2104                     unsigned BranchOp) const{
2105  // $bb:
2106  //  vany_nonzero $rd, $ws
2107  //  =>
2108  // $bb:
2109  //  bnz.b $ws, $tbb
2110  //  b $fbb
2111  // $fbb:
2112  //  li $rd1, 0
2113  //  b $sink
2114  // $tbb:
2115  //  li $rd2, 1
2116  // $sink:
2117  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
2118
2119  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2120  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2121  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2122  DebugLoc DL = MI->getDebugLoc();
2123  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2124  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2125  MachineFunction *F = BB->getParent();
2126  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2127  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2128  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2129  F->insert(It, FBB);
2130  F->insert(It, TBB);
2131  F->insert(It, Sink);
2132
2133  // Transfer the remainder of BB and its successor edges to Sink.
2134  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2135               BB->end());
2136  Sink->transferSuccessorsAndUpdatePHIs(BB);
2137
2138  // Add successors.
2139  BB->addSuccessor(FBB);
2140  BB->addSuccessor(TBB);
2141  FBB->addSuccessor(Sink);
2142  TBB->addSuccessor(Sink);
2143
2144  // Insert the real bnz.b instruction to $BB.
2145  BuildMI(BB, DL, TII->get(BranchOp))
2146    .addReg(MI->getOperand(1).getReg())
2147    .addMBB(TBB);
2148
2149  // Fill $FBB.
2150  unsigned RD1 = RegInfo.createVirtualRegister(RC);
2151  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2152    .addReg(Mips::ZERO).addImm(0);
2153  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2154
2155  // Fill $TBB.
2156  unsigned RD2 = RegInfo.createVirtualRegister(RC);
2157  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2158    .addReg(Mips::ZERO).addImm(1);
2159
2160  // Insert phi function to $Sink.
2161  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2162          MI->getOperand(0).getReg())
2163    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2164
2165  MI->eraseFromParent();   // The pseudo instruction is gone now.
2166  return Sink;
2167}
2168