MipsSEISelLowering.cpp revision fc82e4db13b46b2f14f5895d2a0b33524d55d06a 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Support/CommandLine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21using namespace llvm;
22
23static cl::opt<bool>
24EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
25                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
26
27MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
28  : MipsTargetLowering(TM) {
29  // Set up the register classes
30
31  clearRegisterClasses();
32
33  addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
34
35  if (HasMips64)
36    addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
37
38  if (Subtarget->hasDSP()) {
39    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
40
41    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
42      addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
43
44      // Expand all builtin opcodes.
45      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
46        setOperationAction(Opc, VecTys[i], Expand);
47
48      setOperationAction(ISD::LOAD, VecTys[i], Legal);
49      setOperationAction(ISD::STORE, VecTys[i], Legal);
50      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
51    }
52  }
53
54  if (!TM.Options.UseSoftFloat) {
55    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
56
57    // When dealing with single precision only, use libcalls
58    if (!Subtarget->isSingleFloat()) {
59      if (HasMips64)
60        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
61      else
62        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
63    }
64  }
65
66  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
67  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
68  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
69  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
70
71  if (HasMips64) {
72    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
73    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
74    setOperationAction(ISD::MUL,              MVT::i64, Custom);
75  }
76
77  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
78  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
79  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
80  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
81  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Custom);
82  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
83  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
84  setOperationAction(ISD::STORE,              MVT::i32, Custom);
85
86  setTargetDAGCombine(ISD::ADDE);
87  setTargetDAGCombine(ISD::SUBE);
88
89  computeRegisterProperties();
90}
91
92const MipsTargetLowering *
93llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
94  return new MipsSETargetLowering(TM);
95}
96
97
98bool
99MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
100  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
101
102  switch (SVT) {
103  case MVT::i64:
104  case MVT::i32:
105    if (Fast)
106      *Fast = true;
107    return true;
108  default:
109    return false;
110  }
111}
112
113SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
114                                             SelectionDAG &DAG) const {
115  switch(Op.getOpcode()) {
116  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
117  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
118  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
119  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
120  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
121  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
122  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
123  }
124
125  return MipsTargetLowering::LowerOperation(Op, DAG);
126}
127
128// selectMADD -
129// Transforms a subgraph in CurDAG if the following pattern is found:
130//  (addc multLo, Lo0), (adde multHi, Hi0),
131// where,
132//  multHi/Lo: product of multiplication
133//  Lo0: initial value of Lo register
134//  Hi0: initial value of Hi register
135// Return true if pattern matching was successful.
136static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
137  // ADDENode's second operand must be a flag output of an ADDC node in order
138  // for the matching to be successful.
139  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
140
141  if (ADDCNode->getOpcode() != ISD::ADDC)
142    return false;
143
144  SDValue MultHi = ADDENode->getOperand(0);
145  SDValue MultLo = ADDCNode->getOperand(0);
146  SDNode *MultNode = MultHi.getNode();
147  unsigned MultOpc = MultHi.getOpcode();
148
149  // MultHi and MultLo must be generated by the same node,
150  if (MultLo.getNode() != MultNode)
151    return false;
152
153  // and it must be a multiplication.
154  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
155    return false;
156
157  // MultLo amd MultHi must be the first and second output of MultNode
158  // respectively.
159  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
160    return false;
161
162  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
163  // of the values of MultNode, in which case MultNode will be removed in later
164  // phases.
165  // If there exist users other than ADDENode or ADDCNode, this function returns
166  // here, which will result in MultNode being mapped to a single MULT
167  // instruction node rather than a pair of MULT and MADD instructions being
168  // produced.
169  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
170    return false;
171
172  DebugLoc DL = ADDENode->getDebugLoc();
173
174  // Initialize accumulator.
175  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
176                                  ADDCNode->getOperand(1),
177                                  ADDENode->getOperand(1));
178
179  // create MipsMAdd(u) node
180  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
181
182  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
183                                 MultNode->getOperand(0),// Factor 0
184                                 MultNode->getOperand(1),// Factor 1
185                                 ACCIn);
186
187  // replace uses of adde and addc here
188  if (!SDValue(ADDCNode, 0).use_empty()) {
189    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
190    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
191                                    LoIdx);
192    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
193  }
194  if (!SDValue(ADDENode, 0).use_empty()) {
195    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
196    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
197                                    HiIdx);
198    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
199  }
200
201  return true;
202}
203
204// selectMSUB -
205// Transforms a subgraph in CurDAG if the following pattern is found:
206//  (addc Lo0, multLo), (sube Hi0, multHi),
207// where,
208//  multHi/Lo: product of multiplication
209//  Lo0: initial value of Lo register
210//  Hi0: initial value of Hi register
211// Return true if pattern matching was successful.
212static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
213  // SUBENode's second operand must be a flag output of an SUBC node in order
214  // for the matching to be successful.
215  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
216
217  if (SUBCNode->getOpcode() != ISD::SUBC)
218    return false;
219
220  SDValue MultHi = SUBENode->getOperand(1);
221  SDValue MultLo = SUBCNode->getOperand(1);
222  SDNode *MultNode = MultHi.getNode();
223  unsigned MultOpc = MultHi.getOpcode();
224
225  // MultHi and MultLo must be generated by the same node,
226  if (MultLo.getNode() != MultNode)
227    return false;
228
229  // and it must be a multiplication.
230  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
231    return false;
232
233  // MultLo amd MultHi must be the first and second output of MultNode
234  // respectively.
235  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
236    return false;
237
238  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
239  // of the values of MultNode, in which case MultNode will be removed in later
240  // phases.
241  // If there exist users other than SUBENode or SUBCNode, this function returns
242  // here, which will result in MultNode being mapped to a single MULT
243  // instruction node rather than a pair of MULT and MSUB instructions being
244  // produced.
245  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
246    return false;
247
248  DebugLoc DL = SUBENode->getDebugLoc();
249
250  // Initialize accumulator.
251  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
252                                  SUBCNode->getOperand(0),
253                                  SUBENode->getOperand(0));
254
255  // create MipsSub(u) node
256  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
257
258  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
259                                 MultNode->getOperand(0),// Factor 0
260                                 MultNode->getOperand(1),// Factor 1
261                                 ACCIn);
262
263  // replace uses of sube and subc here
264  if (!SDValue(SUBCNode, 0).use_empty()) {
265    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
266    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
267                                    LoIdx);
268    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
269  }
270  if (!SDValue(SUBENode, 0).use_empty()) {
271    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
272    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
273                                    HiIdx);
274    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
275  }
276
277  return true;
278}
279
280static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
281                                  TargetLowering::DAGCombinerInfo &DCI,
282                                  const MipsSubtarget *Subtarget) {
283  if (DCI.isBeforeLegalize())
284    return SDValue();
285
286  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
287      selectMADD(N, &DAG))
288    return SDValue(N, 0);
289
290  return SDValue();
291}
292
293static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
294                                  TargetLowering::DAGCombinerInfo &DCI,
295                                  const MipsSubtarget *Subtarget) {
296  if (DCI.isBeforeLegalize())
297    return SDValue();
298
299  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
300      selectMSUB(N, &DAG))
301    return SDValue(N, 0);
302
303  return SDValue();
304}
305
306SDValue
307MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
308  SelectionDAG &DAG = DCI.DAG;
309
310  switch (N->getOpcode()) {
311  case ISD::ADDE:
312    return performADDECombine(N, DAG, DCI, Subtarget);
313  case ISD::SUBE:
314    return performSUBECombine(N, DAG, DCI, Subtarget);
315  default:
316    return MipsTargetLowering::PerformDAGCombine(N, DCI);
317  }
318}
319
320MachineBasicBlock *
321MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
322                                                  MachineBasicBlock *BB) const {
323  switch (MI->getOpcode()) {
324  default:
325    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
326  case Mips::BPOSGE32_PSEUDO:
327    return emitBPOSGE32(MI, BB);
328  }
329}
330
331bool MipsSETargetLowering::
332isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
333                                  unsigned NextStackOffset,
334                                  const MipsFunctionInfo& FI) const {
335  if (!EnableMipsTailCalls)
336    return false;
337
338  // Return false if either the callee or caller has a byval argument.
339  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
340    return false;
341
342  // Return true if the callee's argument area is no larger than the
343  // caller's.
344  return NextStackOffset <= FI.getIncomingArgSize();
345}
346
347void MipsSETargetLowering::
348getOpndList(SmallVectorImpl<SDValue> &Ops,
349            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
350            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
351            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
352  // T9 should contain the address of the callee function if
353  // -reloction-model=pic or it is an indirect call.
354  if (IsPICCall || !GlobalOrExternal) {
355    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
356    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
357  } else
358    Ops.push_back(Callee);
359
360  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
361                                  InternalLinkage, CLI, Callee, Chain);
362}
363
364SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
365                                          bool HasLo, bool HasHi,
366                                          SelectionDAG &DAG) const {
367  EVT Ty = Op.getOperand(0).getValueType();
368  DebugLoc DL = Op.getDebugLoc();
369  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
370                             Op.getOperand(0), Op.getOperand(1));
371  SDValue Lo, Hi;
372
373  if (HasLo)
374    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
375                     DAG.getConstant(Mips::sub_lo, MVT::i32));
376  if (HasHi)
377    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
378                     DAG.getConstant(Mips::sub_hi, MVT::i32));
379
380  if (!HasLo || !HasHi)
381    return HasLo ? Lo : Hi;
382
383  SDValue Vals[] = { Lo, Hi };
384  return DAG.getMergeValues(Vals, 2, DL);
385}
386
387MachineBasicBlock * MipsSETargetLowering::
388emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
389  // $bb:
390  //  bposge32_pseudo $vr0
391  //  =>
392  // $bb:
393  //  bposge32 $tbb
394  // $fbb:
395  //  li $vr2, 0
396  //  b $sink
397  // $tbb:
398  //  li $vr1, 1
399  // $sink:
400  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
401
402  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
403  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
404  const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
405  DebugLoc DL = MI->getDebugLoc();
406  const BasicBlock *LLVM_BB = BB->getBasicBlock();
407  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
408  MachineFunction *F = BB->getParent();
409  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
410  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
411  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
412  F->insert(It, FBB);
413  F->insert(It, TBB);
414  F->insert(It, Sink);
415
416  // Transfer the remainder of BB and its successor edges to Sink.
417  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
418               BB->end());
419  Sink->transferSuccessorsAndUpdatePHIs(BB);
420
421  // Add successors.
422  BB->addSuccessor(FBB);
423  BB->addSuccessor(TBB);
424  FBB->addSuccessor(Sink);
425  TBB->addSuccessor(Sink);
426
427  // Insert the real bposge32 instruction to $BB.
428  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
429
430  // Fill $FBB.
431  unsigned VR2 = RegInfo.createVirtualRegister(RC);
432  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
433    .addReg(Mips::ZERO).addImm(0);
434  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
435
436  // Fill $TBB.
437  unsigned VR1 = RegInfo.createVirtualRegister(RC);
438  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
439    .addReg(Mips::ZERO).addImm(1);
440
441  // Insert phi function to $Sink.
442  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
443          MI->getOperand(0).getReg())
444    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
445
446  MI->eraseFromParent();   // The pseudo instruction is gone now.
447  return Sink;
448}
449