MipsSEISelLowering.h revision 09c7f4026afa46ca7ca67d47179013a340a5e944 
1//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MipsSEISELLOWERING_H
15#define MipsSEISELLOWERING_H
16
17#include "MipsISelLowering.h"
18#include "MipsRegisterInfo.h"
19
20namespace llvm {
21  class MipsSETargetLowering : public MipsTargetLowering  {
22  public:
23    explicit MipsSETargetLowering(MipsTargetMachine &TM);
24
25    /// \brief Enable MSA support for the given integer type and Register
26    /// class.
27    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
28    /// \brief Enable MSA support for the given floating-point type and
29    /// Register class.
30    void addMSAFloatType(MVT::SimpleValueType Ty,
31                         const TargetRegisterClass *RC);
32
33    virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
34
35    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
36
37    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
38
39    virtual MachineBasicBlock *
40    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
41
42    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
43                                    EVT VT) const {
44      return false;
45    }
46
47    virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
48      if (VT == MVT::Untyped)
49        return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
50                                     &Mips::ACC64RegClass;
51
52      return TargetLowering::getRepRegClassFor(VT);
53    }
54
55  private:
56    virtual bool
57    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
58                                      unsigned NextStackOffset,
59                                      const MipsFunctionInfo& FI) const;
60
61    virtual void
62    getOpndList(SmallVectorImpl<SDValue> &Ops,
63                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
64                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
65                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
66
67    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
68    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
69
70    SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
71                        SelectionDAG &DAG) const;
72
73    SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
74    SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
75    SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
76    SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
77    SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
78    /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
79    /// depending on the indices in the shuffle.
80    SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
81
82    MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
83                                    MachineBasicBlock *BB) const;
84    MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
85                                            MachineBasicBlock *BB,
86                                            unsigned BranchOp) const;
87    /// \brief Emit the COPY_FW pseudo instruction
88    MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
89                                   MachineBasicBlock *BB) const;
90    /// \brief Emit the COPY_FD pseudo instruction
91    MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
92                                   MachineBasicBlock *BB) const;
93    /// \brief Emit the INSERT_FW pseudo instruction
94    MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
95                                     MachineBasicBlock *BB) const;
96    /// \brief Emit the INSERT_FD pseudo instruction
97    MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
98                                     MachineBasicBlock *BB) const;
99    /// \brief Emit the FILL_FW pseudo instruction
100    MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
101                                   MachineBasicBlock *BB) const;
102    /// \brief Emit the FILL_FD pseudo instruction
103    MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
104                                   MachineBasicBlock *BB) const;
105    /// \brief Emit the FEXP2_W_1 pseudo instructions.
106    MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
107                                     MachineBasicBlock *BB) const;
108    /// \brief Emit the FEXP2_D_1 pseudo instructions.
109    MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
110                                     MachineBasicBlock *BB) const;
111  };
112}
113
114#endif // MipsSEISELLOWERING_H
115