MipsSEISelLowering.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MipsSEISELLOWERING_H
15#define MipsSEISELLOWERING_H
16
17#include "MipsISelLowering.h"
18#include "MipsRegisterInfo.h"
19
20namespace llvm {
21  class MipsSETargetLowering : public MipsTargetLowering  {
22  public:
23    explicit MipsSETargetLowering(MipsTargetMachine &TM);
24
25    /// \brief Enable MSA support for the given integer type and Register
26    /// class.
27    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
28    /// \brief Enable MSA support for the given floating-point type and
29    /// Register class.
30    void addMSAFloatType(MVT::SimpleValueType Ty,
31                         const TargetRegisterClass *RC);
32
33    virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
34                                               bool *Fast = 0) const override;
35
36    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
37
38    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
39
40    virtual MachineBasicBlock *
41    EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
42
43    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
44                                    EVT VT) const {
45      return false;
46    }
47
48    virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
49      if (VT == MVT::Untyped)
50        return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
51                                     &Mips::ACC64RegClass;
52
53      return TargetLowering::getRepRegClassFor(VT);
54    }
55
56  private:
57    virtual bool
58    isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
59                                      unsigned NextStackOffset,
60                                      const MipsFunctionInfo& FI) const;
61
62    virtual void
63    getOpndList(SmallVectorImpl<SDValue> &Ops,
64                std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
65                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
66                CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
67
68    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
69    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
70
71    SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
72                        SelectionDAG &DAG) const;
73
74    SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
75    SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
76    SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
77    SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
78    SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
79    /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
80    /// depending on the indices in the shuffle.
81    SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
82
83    MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
84                                    MachineBasicBlock *BB) const;
85    MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
86                                            MachineBasicBlock *BB,
87                                            unsigned BranchOp) const;
88    /// \brief Emit the COPY_FW pseudo instruction
89    MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
90                                   MachineBasicBlock *BB) const;
91    /// \brief Emit the COPY_FD pseudo instruction
92    MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
93                                   MachineBasicBlock *BB) const;
94    /// \brief Emit the INSERT_FW pseudo instruction
95    MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
96                                     MachineBasicBlock *BB) const;
97    /// \brief Emit the INSERT_FD pseudo instruction
98    MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
99                                     MachineBasicBlock *BB) const;
100    /// \brief Emit the FILL_FW pseudo instruction
101    MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
102                                   MachineBasicBlock *BB) const;
103    /// \brief Emit the FILL_FD pseudo instruction
104    MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
105                                   MachineBasicBlock *BB) const;
106    /// \brief Emit the FEXP2_W_1 pseudo instructions.
107    MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
108                                     MachineBasicBlock *BB) const;
109    /// \brief Emit the FEXP2_D_1 pseudo instructions.
110    MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
111                                     MachineBasicBlock *BB) const;
112  };
113}
114
115#endif // MipsSEISELLOWERING_H
116