MipsSEInstrInfo.cpp revision 0b926427670de6e0ed855ef93f220a3f51ed1eab 
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
28                                   cl::desc("Expand double precision loads and "
29                                            "stores to their single precision "
30                                            "counterparts."));
31
32MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
33  : MipsInstrInfo(tm,
34                  tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
35    RI(*tm.getSubtargetImpl()),
36    IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
37
38const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
39  return RI;
40}
41
42/// isLoadFromStackSlot - If the specified machine instruction is a direct
43/// load from a stack slot, return the virtual or physical register number of
44/// the destination along with the FrameIndex of the loaded stack slot.  If
45/// not, return 0.  This predicate must return 0 if the instruction has
46/// any side effects other than loading from the stack slot.
47unsigned MipsSEInstrInfo::
48isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
49{
50  unsigned Opc = MI->getOpcode();
51
52  if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
53      (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
54      (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
55      (Opc == Mips::LDC164_P8)) {
56    if ((MI->getOperand(1).isFI()) && // is a stack slot
57        (MI->getOperand(2).isImm()) &&  // the imm is zero
58        (isZeroImm(MI->getOperand(2)))) {
59      FrameIndex = MI->getOperand(1).getIndex();
60      return MI->getOperand(0).getReg();
61    }
62  }
63
64  return 0;
65}
66
67/// isStoreToStackSlot - If the specified machine instruction is a direct
68/// store to a stack slot, return the virtual or physical register number of
69/// the source reg along with the FrameIndex of the loaded stack slot.  If
70/// not, return 0.  This predicate must return 0 if the instruction has
71/// any side effects other than storing to the stack slot.
72unsigned MipsSEInstrInfo::
73isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
74{
75  unsigned Opc = MI->getOpcode();
76
77  if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
78      (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
79      (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
80      (Opc == Mips::SDC164_P8)) {
81    if ((MI->getOperand(1).isFI()) && // is a stack slot
82        (MI->getOperand(2).isImm()) &&  // the imm is zero
83        (isZeroImm(MI->getOperand(2)))) {
84      FrameIndex = MI->getOperand(1).getIndex();
85      return MI->getOperand(0).getReg();
86    }
87  }
88  return 0;
89}
90
91void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92                                  MachineBasicBlock::iterator I, DebugLoc DL,
93                                  unsigned DestReg, unsigned SrcReg,
94                                  bool KillSrc) const {
95  unsigned Opc = 0, ZeroReg = 0;
96
97  if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
98    if (Mips::CPURegsRegClass.contains(SrcReg))
99      Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
100    else if (Mips::CCRRegClass.contains(SrcReg))
101      Opc = Mips::CFC1;
102    else if (Mips::FGR32RegClass.contains(SrcReg))
103      Opc = Mips::MFC1;
104    else if (Mips::HIRegsRegClass.contains(SrcReg))
105      Opc = Mips::MFHI, SrcReg = 0;
106    else if (Mips::LORegsRegClass.contains(SrcReg))
107      Opc = Mips::MFLO, SrcReg = 0;
108    else if (Mips::HIRegsDSPRegClass.contains(SrcReg))
109      Opc = Mips::MFHI_DSP;
110    else if (Mips::LORegsDSPRegClass.contains(SrcReg))
111      Opc = Mips::MFLO_DSP;
112    else if (Mips::DSPCCRegClass.contains(SrcReg)) {
113      BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
114        .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
115      return;
116    }
117  }
118  else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
119    if (Mips::CCRRegClass.contains(DestReg))
120      Opc = Mips::CTC1;
121    else if (Mips::FGR32RegClass.contains(DestReg))
122      Opc = Mips::MTC1;
123    else if (Mips::HIRegsRegClass.contains(DestReg))
124      Opc = Mips::MTHI, DestReg = 0;
125    else if (Mips::LORegsRegClass.contains(DestReg))
126      Opc = Mips::MTLO, DestReg = 0;
127    else if (Mips::HIRegsDSPRegClass.contains(DestReg))
128      Opc = Mips::MTHI_DSP;
129    else if (Mips::LORegsDSPRegClass.contains(DestReg))
130      Opc = Mips::MTLO_DSP;
131    else if (Mips::DSPCCRegClass.contains(DestReg)) {
132      BuildMI(MBB, I, DL, get(Mips::WRDSP))
133        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134        .addReg(DestReg, RegState::ImplicitDefine);
135      return;
136    }
137  }
138  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
139    Opc = Mips::FMOV_S;
140  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
141    Opc = Mips::FMOV_D32;
142  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
143    Opc = Mips::FMOV_D64;
144  else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
145    if (Mips::CPU64RegsRegClass.contains(SrcReg))
146      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
147    else if (Mips::HIRegs64RegClass.contains(SrcReg))
148      Opc = Mips::MFHI64, SrcReg = 0;
149    else if (Mips::LORegs64RegClass.contains(SrcReg))
150      Opc = Mips::MFLO64, SrcReg = 0;
151    else if (Mips::FGR64RegClass.contains(SrcReg))
152      Opc = Mips::DMFC1;
153  }
154  else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
155    if (Mips::HIRegs64RegClass.contains(DestReg))
156      Opc = Mips::MTHI64, DestReg = 0;
157    else if (Mips::LORegs64RegClass.contains(DestReg))
158      Opc = Mips::MTLO64, DestReg = 0;
159    else if (Mips::FGR64RegClass.contains(DestReg))
160      Opc = Mips::DMTC1;
161  }
162
163  assert(Opc && "Cannot copy registers");
164
165  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
166
167  if (DestReg)
168    MIB.addReg(DestReg, RegState::Define);
169
170  if (SrcReg)
171    MIB.addReg(SrcReg, getKillRegState(KillSrc));
172
173  if (ZeroReg)
174    MIB.addReg(ZeroReg);
175}
176
177void MipsSEInstrInfo::
178storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
179                unsigned SrcReg, bool isKill, int FI,
180                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
181                int64_t Offset) const {
182  DebugLoc DL;
183  if (I != MBB.end()) DL = I->getDebugLoc();
184  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
185
186  unsigned Opc = 0;
187
188  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
189    Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
190  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
191    Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
192  else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
193    Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
194  else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
195    Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
196  else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
197    Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
198  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
199    Opc = IsN64 ? Mips::STORE_CCOND_DSP_P8 : Mips::STORE_CCOND_DSP;
200  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
201    Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
202  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
203    Opc = Mips::SDC1;
204  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
205    Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
206
207  assert(Opc && "Register class not handled!");
208  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
209    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
210}
211
212void MipsSEInstrInfo::
213loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
214                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
215                 const TargetRegisterInfo *TRI, int64_t Offset) const {
216  DebugLoc DL;
217  if (I != MBB.end()) DL = I->getDebugLoc();
218  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
219  unsigned Opc = 0;
220
221  if (Mips::CPURegsRegClass.hasSubClassEq(RC))
222    Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
223  else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
224    Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
225  else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
226    Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
227  else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
228    Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
229  else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
230    Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
231  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
232    Opc = IsN64 ? Mips::LOAD_CCOND_DSP_P8 : Mips::LOAD_CCOND_DSP;
233  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
234    Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
235  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
236    Opc = Mips::LDC1;
237  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
238    Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
239
240  assert(Opc && "Register class not handled!");
241  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
242    .addMemOperand(MMO);
243}
244
245bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
246  MachineBasicBlock &MBB = *MI->getParent();
247
248  switch(MI->getDesc().getOpcode()) {
249  default:
250    return false;
251  case Mips::RetRA:
252    expandRetRA(MBB, MI, Mips::RET);
253    break;
254  case Mips::PseudoCVT_S_W:
255    expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
256    break;
257  case Mips::PseudoCVT_D32_W:
258    expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
259    break;
260  case Mips::PseudoCVT_S_L:
261    expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
262    break;
263  case Mips::PseudoCVT_D64_W:
264    expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
265    break;
266  case Mips::PseudoCVT_D64_L:
267    expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
268    break;
269  case Mips::BuildPairF64:
270    expandBuildPairF64(MBB, MI);
271    break;
272  case Mips::ExtractElementF64:
273    expandExtractElementF64(MBB, MI);
274    break;
275  case Mips::PseudoLDC1:
276    expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
277    break;
278  case Mips::PseudoSDC1:
279    expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1);
280    break;
281  case Mips::MIPSeh_return32:
282  case Mips::MIPSeh_return64:
283    expandEhReturn(MBB, MI);
284    break;
285  }
286
287  MBB.erase(MI);
288  return true;
289}
290
291/// getOppositeBranchOpc - Return the inverse of the specified
292/// opcode, e.g. turning BEQ to BNE.
293unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
294  switch (Opc) {
295  default:           llvm_unreachable("Illegal opcode!");
296  case Mips::BEQ:    return Mips::BNE;
297  case Mips::BNE:    return Mips::BEQ;
298  case Mips::BGTZ:   return Mips::BLEZ;
299  case Mips::BGEZ:   return Mips::BLTZ;
300  case Mips::BLTZ:   return Mips::BGEZ;
301  case Mips::BLEZ:   return Mips::BGTZ;
302  case Mips::BEQ64:  return Mips::BNE64;
303  case Mips::BNE64:  return Mips::BEQ64;
304  case Mips::BGTZ64: return Mips::BLEZ64;
305  case Mips::BGEZ64: return Mips::BLTZ64;
306  case Mips::BLTZ64: return Mips::BGEZ64;
307  case Mips::BLEZ64: return Mips::BGTZ64;
308  case Mips::BC1T:   return Mips::BC1F;
309  case Mips::BC1F:   return Mips::BC1T;
310  }
311}
312
313/// Adjust SP by Amount bytes.
314void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
315                                     MachineBasicBlock &MBB,
316                                     MachineBasicBlock::iterator I) const {
317  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
318  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
319  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
320  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
321
322  if (isInt<16>(Amount))// addi sp, sp, amount
323    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
324  else { // Expand immediate that doesn't fit in 16-bit.
325    unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
326    BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
327  }
328}
329
330/// This function generates the sequence of instructions needed to get the
331/// result of adding register REG and immediate IMM.
332unsigned
333MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
334                               MachineBasicBlock::iterator II, DebugLoc DL,
335                               unsigned *NewImm) const {
336  MipsAnalyzeImmediate AnalyzeImm;
337  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
338  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
339  unsigned Size = STI.isABI_N64() ? 64 : 32;
340  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
341  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
342  const TargetRegisterClass *RC = STI.isABI_N64() ?
343    &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
344  bool LastInstrIsADDiu = NewImm;
345
346  const MipsAnalyzeImmediate::InstSeq &Seq =
347    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
348  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
349
350  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
351
352  // The first instruction can be a LUi, which is different from other
353  // instructions (ADDiu, ORI and SLL) in that it does not have a register
354  // operand.
355  unsigned Reg = RegInfo.createVirtualRegister(RC);
356
357  if (Inst->Opc == LUi)
358    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
359  else
360    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
361      .addImm(SignExtend64<16>(Inst->ImmOpnd));
362
363  // Build the remaining instructions in Seq.
364  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
365    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
366      .addImm(SignExtend64<16>(Inst->ImmOpnd));
367
368  if (LastInstrIsADDiu)
369    *NewImm = Inst->ImmOpnd;
370
371  return Reg;
372}
373
374unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
375  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
376          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
377          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
378          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
379          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
380          Opc == Mips::J) ?
381         Opc : 0;
382}
383
384void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
385                                MachineBasicBlock::iterator I,
386                                unsigned Opc) const {
387  BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
388}
389
390std::pair<bool, bool>
391MipsSEInstrInfo::compareOpndSize(unsigned Opc,
392                                 const MachineFunction &MF) const {
393  const MCInstrDesc &Desc = get(Opc);
394  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
395  const MipsRegisterInfo *RI = &getRegisterInfo();
396  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
397  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
398
399  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
400}
401
402void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
403                                     MachineBasicBlock::iterator I,
404                                     unsigned CvtOpc, unsigned MovOpc,
405                                     bool IsI64) const {
406  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
407  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
408  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
409  unsigned KillSrc =  getKillRegState(Src.isKill());
410  DebugLoc DL = I->getDebugLoc();
411  unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven);
412  bool DstIsLarger, SrcIsLarger;
413
414  tie(DstIsLarger, SrcIsLarger) = compareOpndSize(CvtOpc, *MBB.getParent());
415
416  if (DstIsLarger)
417    TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
418
419  if (SrcIsLarger)
420    DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
421
422  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
423  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
424}
425
426void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
427                                          MachineBasicBlock::iterator I) const {
428  unsigned DstReg = I->getOperand(0).getReg();
429  unsigned SrcReg = I->getOperand(1).getReg();
430  unsigned N = I->getOperand(2).getImm();
431  const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
432  DebugLoc dl = I->getDebugLoc();
433
434  assert(N < 2 && "Invalid immediate");
435  unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
436  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
437
438  BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
439}
440
441void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
442                                       MachineBasicBlock::iterator I) const {
443  unsigned DstReg = I->getOperand(0).getReg();
444  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
445  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
446  DebugLoc dl = I->getDebugLoc();
447  const TargetRegisterInfo &TRI = getRegisterInfo();
448
449  // mtc1 Lo, $fp
450  // mtc1 Hi, $fp + 1
451  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
452    .addReg(LoReg);
453  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
454    .addReg(HiReg);
455}
456
457/// Add 4 to the displacement of operand MO.
458static void fixDisp(MachineOperand &MO) {
459  switch (MO.getType()) {
460  default:
461    llvm_unreachable("Unhandled operand type.");
462  case MachineOperand::MO_Immediate:
463    MO.setImm(MO.getImm() + 4);
464    break;
465  case MachineOperand::MO_GlobalAddress:
466  case MachineOperand::MO_ConstantPoolIndex:
467  case MachineOperand::MO_BlockAddress:
468  case MachineOperand::MO_TargetIndex:
469  case MachineOperand::MO_ExternalSymbol:
470    MO.setOffset(MO.getOffset() + 4);
471    break;
472  }
473}
474
475void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB,
476                                        MachineBasicBlock::iterator I,
477                                        unsigned OpcD, unsigned OpcS) const {
478  // If NoDPLoadStore is false, just change the opcode.
479  if (!NoDPLoadStore) {
480    genInstrWithNewOpc(OpcD, I);
481    return;
482  }
483
484  // Expand a double precision FP load or store to two single precision
485  // instructions.
486
487  const TargetRegisterInfo &TRI = getRegisterInfo();
488  const MachineOperand &ValReg = I->getOperand(0);
489  unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpeven);
490  unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpodd);
491
492  if (!TM.getSubtarget<MipsSubtarget>().isLittle())
493    std::swap(LoReg, HiReg);
494
495  // Create an instruction which loads from or stores to the lower memory
496  // address.
497  MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
498  MIB->getOperand(0).setReg(LoReg);
499
500  // Create an instruction which loads from or stores to the higher memory
501  // address.
502  MIB = genInstrWithNewOpc(OpcS, I);
503  MIB->getOperand(0).setReg(HiReg);
504  fixDisp(MIB->getOperand(2));
505}
506
507void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
508                                     MachineBasicBlock::iterator I) const {
509  // This pseudo instruction is generated as part of the lowering of
510  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
511  // indirect jump to TargetReg
512  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
513  unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
514  unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
515  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
516  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
517  unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
518  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
519  unsigned OffsetReg = I->getOperand(0).getReg();
520  unsigned TargetReg = I->getOperand(1).getReg();
521
522  // addu $ra, $v0, $zero
523  // addu $sp, $sp, $v1
524  // jr   $ra
525  if (TM.getRelocationModel() == Reloc::PIC_)
526    BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
527        .addReg(TargetReg).addReg(ZERO);
528  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
529      .addReg(TargetReg).addReg(ZERO);
530  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
531      .addReg(SP).addReg(OffsetReg);
532  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
533}
534
535const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
536  return new MipsSEInstrInfo(TM);
537}
538