MipsSEInstrInfo.cpp revision 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
28  : MipsInstrInfo(tm,
29                  tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
30    RI(*tm.getSubtargetImpl()),
31    IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
32
33const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
34  return RI;
35}
36
37/// isLoadFromStackSlot - If the specified machine instruction is a direct
38/// load from a stack slot, return the virtual or physical register number of
39/// the destination along with the FrameIndex of the loaded stack slot.  If
40/// not, return 0.  This predicate must return 0 if the instruction has
41/// any side effects other than loading from the stack slot.
42unsigned MipsSEInstrInfo::
43isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44{
45  unsigned Opc = MI->getOpcode();
46
47  if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
48      (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
49    if ((MI->getOperand(1).isFI()) && // is a stack slot
50        (MI->getOperand(2).isImm()) &&  // the imm is zero
51        (isZeroImm(MI->getOperand(2)))) {
52      FrameIndex = MI->getOperand(1).getIndex();
53      return MI->getOperand(0).getReg();
54    }
55  }
56
57  return 0;
58}
59
60/// isStoreToStackSlot - If the specified machine instruction is a direct
61/// store to a stack slot, return the virtual or physical register number of
62/// the source reg along with the FrameIndex of the loaded stack slot.  If
63/// not, return 0.  This predicate must return 0 if the instruction has
64/// any side effects other than storing to the stack slot.
65unsigned MipsSEInstrInfo::
66isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
67{
68  unsigned Opc = MI->getOpcode();
69
70  if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
71      (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
72    if ((MI->getOperand(1).isFI()) && // is a stack slot
73        (MI->getOperand(2).isImm()) &&  // the imm is zero
74        (isZeroImm(MI->getOperand(2)))) {
75      FrameIndex = MI->getOperand(1).getIndex();
76      return MI->getOperand(0).getReg();
77    }
78  }
79  return 0;
80}
81
82void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
83                                  MachineBasicBlock::iterator I, DebugLoc DL,
84                                  unsigned DestReg, unsigned SrcReg,
85                                  bool KillSrc) const {
86  unsigned Opc = 0, ZeroReg = 0;
87
88  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
89    if (Mips::GPR32RegClass.contains(SrcReg))
90      Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
91    else if (Mips::CCRRegClass.contains(SrcReg))
92      Opc = Mips::CFC1;
93    else if (Mips::FGR32RegClass.contains(SrcReg))
94      Opc = Mips::MFC1;
95    else if (Mips::HI32RegClass.contains(SrcReg))
96      Opc = Mips::MFHI, SrcReg = 0;
97    else if (Mips::LO32RegClass.contains(SrcReg))
98      Opc = Mips::MFLO, SrcReg = 0;
99    else if (Mips::HI32DSPRegClass.contains(SrcReg))
100      Opc = Mips::MFHI_DSP;
101    else if (Mips::LO32DSPRegClass.contains(SrcReg))
102      Opc = Mips::MFLO_DSP;
103    else if (Mips::DSPCCRegClass.contains(SrcReg)) {
104      BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
105        .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
106      return;
107    }
108    else if (Mips::MSACtrlRegClass.contains(SrcReg))
109      Opc = Mips::CFCMSA;
110  }
111  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
112    if (Mips::CCRRegClass.contains(DestReg))
113      Opc = Mips::CTC1;
114    else if (Mips::FGR32RegClass.contains(DestReg))
115      Opc = Mips::MTC1;
116    else if (Mips::HI32RegClass.contains(DestReg))
117      Opc = Mips::MTHI, DestReg = 0;
118    else if (Mips::LO32RegClass.contains(DestReg))
119      Opc = Mips::MTLO, DestReg = 0;
120    else if (Mips::HI32DSPRegClass.contains(DestReg))
121      Opc = Mips::MTHI_DSP;
122    else if (Mips::LO32DSPRegClass.contains(DestReg))
123      Opc = Mips::MTLO_DSP;
124    else if (Mips::DSPCCRegClass.contains(DestReg)) {
125      BuildMI(MBB, I, DL, get(Mips::WRDSP))
126        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
127        .addReg(DestReg, RegState::ImplicitDefine);
128      return;
129    }
130    else if (Mips::MSACtrlRegClass.contains(DestReg))
131      Opc = Mips::CTCMSA;
132  }
133  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
134    Opc = Mips::FMOV_S;
135  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
136    Opc = Mips::FMOV_D32;
137  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
138    Opc = Mips::FMOV_D64;
139  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
140    if (Mips::GPR64RegClass.contains(SrcReg))
141      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
142    else if (Mips::HI64RegClass.contains(SrcReg))
143      Opc = Mips::MFHI64, SrcReg = 0;
144    else if (Mips::LO64RegClass.contains(SrcReg))
145      Opc = Mips::MFLO64, SrcReg = 0;
146    else if (Mips::FGR64RegClass.contains(SrcReg))
147      Opc = Mips::DMFC1;
148  }
149  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
150    if (Mips::HI64RegClass.contains(DestReg))
151      Opc = Mips::MTHI64, DestReg = 0;
152    else if (Mips::LO64RegClass.contains(DestReg))
153      Opc = Mips::MTLO64, DestReg = 0;
154    else if (Mips::FGR64RegClass.contains(DestReg))
155      Opc = Mips::DMTC1;
156  }
157
158  assert(Opc && "Cannot copy registers");
159
160  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
161
162  if (DestReg)
163    MIB.addReg(DestReg, RegState::Define);
164
165  if (SrcReg)
166    MIB.addReg(SrcReg, getKillRegState(KillSrc));
167
168  if (ZeroReg)
169    MIB.addReg(ZeroReg);
170}
171
172void MipsSEInstrInfo::
173storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
174                unsigned SrcReg, bool isKill, int FI,
175                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
176                int64_t Offset) const {
177  DebugLoc DL;
178  if (I != MBB.end()) DL = I->getDebugLoc();
179  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
180
181  unsigned Opc = 0;
182
183  if (Mips::GPR32RegClass.hasSubClassEq(RC))
184    Opc = Mips::SW;
185  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
186    Opc = Mips::SD;
187  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
188    Opc = Mips::STORE_ACC64;
189  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
190    Opc = Mips::STORE_ACC64DSP;
191  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
192    Opc = Mips::STORE_ACC128;
193  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
194    Opc = Mips::STORE_CCOND_DSP;
195  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
196    Opc = Mips::SWC1;
197  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
198    Opc = Mips::SDC1;
199  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
200    Opc = Mips::SDC164;
201  else if (RC->hasType(MVT::v16i8))
202    Opc = Mips::ST_B;
203  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
204    Opc = Mips::ST_H;
205  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
206    Opc = Mips::ST_W;
207  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
208    Opc = Mips::ST_D;
209
210  assert(Opc && "Register class not handled!");
211  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
212    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
213}
214
215void MipsSEInstrInfo::
216loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
217                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
218                 const TargetRegisterInfo *TRI, int64_t Offset) const {
219  DebugLoc DL;
220  if (I != MBB.end()) DL = I->getDebugLoc();
221  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
222  unsigned Opc = 0;
223
224  if (Mips::GPR32RegClass.hasSubClassEq(RC))
225    Opc = Mips::LW;
226  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
227    Opc = Mips::LD;
228  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
229    Opc = Mips::LOAD_ACC64;
230  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
231    Opc = Mips::LOAD_ACC64DSP;
232  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
233    Opc = Mips::LOAD_ACC128;
234  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
235    Opc = Mips::LOAD_CCOND_DSP;
236  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
237    Opc = Mips::LWC1;
238  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
239    Opc = Mips::LDC1;
240  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
241    Opc = Mips::LDC164;
242  else if (RC->hasType(MVT::v16i8))
243    Opc = Mips::LD_B;
244  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
245    Opc = Mips::LD_H;
246  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
247    Opc = Mips::LD_W;
248  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
249    Opc = Mips::LD_D;
250
251  assert(Opc && "Register class not handled!");
252  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
253    .addMemOperand(MMO);
254}
255
256bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
257  MachineBasicBlock &MBB = *MI->getParent();
258
259  switch(MI->getDesc().getOpcode()) {
260  default:
261    return false;
262  case Mips::RetRA:
263    expandRetRA(MBB, MI, Mips::RET);
264    break;
265  case Mips::PseudoCVT_S_W:
266    expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
267    break;
268  case Mips::PseudoCVT_D32_W:
269    expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
270    break;
271  case Mips::PseudoCVT_S_L:
272    expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
273    break;
274  case Mips::PseudoCVT_D64_W:
275    expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
276    break;
277  case Mips::PseudoCVT_D64_L:
278    expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
279    break;
280  case Mips::BuildPairF64:
281    expandBuildPairF64(MBB, MI, false);
282    break;
283  case Mips::BuildPairF64_64:
284    expandBuildPairF64(MBB, MI, true);
285    break;
286  case Mips::ExtractElementF64:
287    expandExtractElementF64(MBB, MI, false);
288    break;
289  case Mips::ExtractElementF64_64:
290    expandExtractElementF64(MBB, MI, true);
291    break;
292  case Mips::MIPSeh_return32:
293  case Mips::MIPSeh_return64:
294    expandEhReturn(MBB, MI);
295    break;
296  }
297
298  MBB.erase(MI);
299  return true;
300}
301
302/// getOppositeBranchOpc - Return the inverse of the specified
303/// opcode, e.g. turning BEQ to BNE.
304unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
305  switch (Opc) {
306  default:           llvm_unreachable("Illegal opcode!");
307  case Mips::BEQ:    return Mips::BNE;
308  case Mips::BNE:    return Mips::BEQ;
309  case Mips::BGTZ:   return Mips::BLEZ;
310  case Mips::BGEZ:   return Mips::BLTZ;
311  case Mips::BLTZ:   return Mips::BGEZ;
312  case Mips::BLEZ:   return Mips::BGTZ;
313  case Mips::BEQ64:  return Mips::BNE64;
314  case Mips::BNE64:  return Mips::BEQ64;
315  case Mips::BGTZ64: return Mips::BLEZ64;
316  case Mips::BGEZ64: return Mips::BLTZ64;
317  case Mips::BLTZ64: return Mips::BGEZ64;
318  case Mips::BLEZ64: return Mips::BGTZ64;
319  case Mips::BC1T:   return Mips::BC1F;
320  case Mips::BC1F:   return Mips::BC1T;
321  }
322}
323
324/// Adjust SP by Amount bytes.
325void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
326                                     MachineBasicBlock &MBB,
327                                     MachineBasicBlock::iterator I) const {
328  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
329  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
330  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
331  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
332
333  if (isInt<16>(Amount))// addi sp, sp, amount
334    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
335  else { // Expand immediate that doesn't fit in 16-bit.
336    unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
337    BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
338  }
339}
340
341/// This function generates the sequence of instructions needed to get the
342/// result of adding register REG and immediate IMM.
343unsigned
344MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
345                               MachineBasicBlock::iterator II, DebugLoc DL,
346                               unsigned *NewImm) const {
347  MipsAnalyzeImmediate AnalyzeImm;
348  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
349  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
350  unsigned Size = STI.isABI_N64() ? 64 : 32;
351  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
352  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
353  const TargetRegisterClass *RC = STI.isABI_N64() ?
354    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
355  bool LastInstrIsADDiu = NewImm;
356
357  const MipsAnalyzeImmediate::InstSeq &Seq =
358    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
359  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
360
361  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
362
363  // The first instruction can be a LUi, which is different from other
364  // instructions (ADDiu, ORI and SLL) in that it does not have a register
365  // operand.
366  unsigned Reg = RegInfo.createVirtualRegister(RC);
367
368  if (Inst->Opc == LUi)
369    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
370  else
371    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
372      .addImm(SignExtend64<16>(Inst->ImmOpnd));
373
374  // Build the remaining instructions in Seq.
375  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
376    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
377      .addImm(SignExtend64<16>(Inst->ImmOpnd));
378
379  if (LastInstrIsADDiu)
380    *NewImm = Inst->ImmOpnd;
381
382  return Reg;
383}
384
385unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
386  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
387          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
388          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
389          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
390          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
391          Opc == Mips::J) ?
392         Opc : 0;
393}
394
395void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
396                                MachineBasicBlock::iterator I,
397                                unsigned Opc) const {
398  BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
399}
400
401std::pair<bool, bool>
402MipsSEInstrInfo::compareOpndSize(unsigned Opc,
403                                 const MachineFunction &MF) const {
404  const MCInstrDesc &Desc = get(Opc);
405  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
406  const MipsRegisterInfo *RI = &getRegisterInfo();
407  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
408  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
409
410  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
411}
412
413void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
414                                     MachineBasicBlock::iterator I,
415                                     unsigned CvtOpc, unsigned MovOpc,
416                                     bool IsI64) const {
417  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
418  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
419  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
420  unsigned KillSrc =  getKillRegState(Src.isKill());
421  DebugLoc DL = I->getDebugLoc();
422  bool DstIsLarger, SrcIsLarger;
423
424  tie(DstIsLarger, SrcIsLarger) = compareOpndSize(CvtOpc, *MBB.getParent());
425
426  if (DstIsLarger)
427    TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
428
429  if (SrcIsLarger)
430    DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
431
432  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
433  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
434}
435
436void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
437                                              MachineBasicBlock::iterator I,
438                                              bool FP64) const {
439  unsigned DstReg = I->getOperand(0).getReg();
440  unsigned SrcReg = I->getOperand(1).getReg();
441  unsigned N = I->getOperand(2).getImm();
442  DebugLoc dl = I->getDebugLoc();
443
444  assert(N < 2 && "Invalid immediate");
445  unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
446  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
447
448  if (SubIdx == Mips::sub_hi && FP64)
449    BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg);
450  else
451    BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
452}
453
454void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
455                                         MachineBasicBlock::iterator I,
456                                         bool FP64) const {
457  unsigned DstReg = I->getOperand(0).getReg();
458  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
459  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
460  DebugLoc dl = I->getDebugLoc();
461  const TargetRegisterInfo &TRI = getRegisterInfo();
462
463  // mtc1 Lo, $fp
464  // mtc1 Hi, $fp + 1
465  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
466    .addReg(LoReg);
467
468  if (FP64)
469    BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
470      .addReg(HiReg);
471  else
472    BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
473      .addReg(HiReg);
474}
475
476void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
477                                     MachineBasicBlock::iterator I) const {
478  // This pseudo instruction is generated as part of the lowering of
479  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
480  // indirect jump to TargetReg
481  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
482  unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
483  unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
484  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
485  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
486  unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
487  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
488  unsigned OffsetReg = I->getOperand(0).getReg();
489  unsigned TargetReg = I->getOperand(1).getReg();
490
491  // addu $ra, $v0, $zero
492  // addu $sp, $sp, $v1
493  // jr   $ra
494  if (TM.getRelocationModel() == Reloc::PIC_)
495    BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
496        .addReg(TargetReg).addReg(ZERO);
497  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
498      .addReg(TargetReg).addReg(ZERO);
499  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
500      .addReg(SP).addReg(OffsetReg);
501  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
502}
503
504const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
505  return new MipsSEInstrInfo(TM);
506}
507