MipsSEInstrInfo.cpp revision 99ad6ac65e8c97a0d3c9d884285dda01f793b7d1
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsSEInstrInfo.h" 15#include "InstPrinter/MipsInstPrinter.h" 16#include "MipsMachineFunction.h" 17#include "MipsTargetMachine.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/CodeGen/MachineInstrBuilder.h" 20#include "llvm/CodeGen/MachineRegisterInfo.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "llvm/Support/TargetRegistry.h" 23 24using namespace llvm; 25 26MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) 27 : MipsInstrInfo(tm, 28 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), 29 RI(*tm.getSubtargetImpl(), *this), 30 IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {} 31 32const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34} 35 36/// isLoadFromStackSlot - If the specified machine instruction is a direct 37/// load from a stack slot, return the virtual or physical register number of 38/// the destination along with the FrameIndex of the loaded stack slot. If 39/// not, return 0. This predicate must return 0 if the instruction has 40/// any side effects other than loading from the stack slot. 41unsigned MipsSEInstrInfo:: 42isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 43{ 44 unsigned Opc = MI->getOpcode(); 45 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || 49 (Opc == Mips::LDC164_P8)) { 50 if ((MI->getOperand(1).isFI()) && // is a stack slot 51 (MI->getOperand(2).isImm()) && // the imm is zero 52 (isZeroImm(MI->getOperand(2)))) { 53 FrameIndex = MI->getOperand(1).getIndex(); 54 return MI->getOperand(0).getReg(); 55 } 56 } 57 58 return 0; 59} 60 61/// isStoreToStackSlot - If the specified machine instruction is a direct 62/// store to a stack slot, return the virtual or physical register number of 63/// the source reg along with the FrameIndex of the loaded stack slot. If 64/// not, return 0. This predicate must return 0 if the instruction has 65/// any side effects other than storing to the stack slot. 66unsigned MipsSEInstrInfo:: 67isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 68{ 69 unsigned Opc = MI->getOpcode(); 70 71 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || 72 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || 73 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || 74 (Opc == Mips::SDC164_P8)) { 75 if ((MI->getOperand(1).isFI()) && // is a stack slot 76 (MI->getOperand(2).isImm()) && // the imm is zero 77 (isZeroImm(MI->getOperand(2)))) { 78 FrameIndex = MI->getOperand(1).getIndex(); 79 return MI->getOperand(0).getReg(); 80 } 81 } 82 return 0; 83} 84 85void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator I, DebugLoc DL, 87 unsigned DestReg, unsigned SrcReg, 88 bool KillSrc) const { 89 unsigned Opc = 0, ZeroReg = 0; 90 91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 92 if (Mips::CPURegsRegClass.contains(SrcReg)) 93 Opc = Mips::OR, ZeroReg = Mips::ZERO; 94 else if (Mips::CCRRegClass.contains(SrcReg)) 95 Opc = Mips::CFC1; 96 else if (Mips::FGR32RegClass.contains(SrcReg)) 97 Opc = Mips::MFC1; 98 else if (Mips::HIRegsRegClass.contains(SrcReg)) 99 Opc = Mips::MFHI, SrcReg = 0; 100 else if (Mips::LORegsRegClass.contains(SrcReg)) 101 Opc = Mips::MFLO, SrcReg = 0; 102 else if (Mips::HIRegsDSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LORegsDSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 } 112 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. 113 if (Mips::CCRRegClass.contains(DestReg)) 114 Opc = Mips::CTC1; 115 else if (Mips::FGR32RegClass.contains(DestReg)) 116 Opc = Mips::MTC1; 117 else if (Mips::HIRegsRegClass.contains(DestReg)) 118 Opc = Mips::MTHI, DestReg = 0; 119 else if (Mips::LORegsRegClass.contains(DestReg)) 120 Opc = Mips::MTLO, DestReg = 0; 121 else if (Mips::HIRegsDSPRegClass.contains(DestReg)) 122 Opc = Mips::MTHI_DSP; 123 else if (Mips::LORegsDSPRegClass.contains(DestReg)) 124 Opc = Mips::MTLO_DSP; 125 else if (Mips::DSPCCRegClass.contains(DestReg)) { 126 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 127 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 128 .addReg(DestReg, RegState::ImplicitDefine); 129 return; 130 } 131 } 132 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 133 Opc = Mips::FMOV_S; 134 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 135 Opc = Mips::FMOV_D32; 136 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 137 Opc = Mips::FMOV_D64; 138 else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) 139 Opc = Mips::MOVCCRToCCR; 140 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. 141 if (Mips::CPU64RegsRegClass.contains(SrcReg)) 142 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 143 else if (Mips::HIRegs64RegClass.contains(SrcReg)) 144 Opc = Mips::MFHI64, SrcReg = 0; 145 else if (Mips::LORegs64RegClass.contains(SrcReg)) 146 Opc = Mips::MFLO64, SrcReg = 0; 147 else if (Mips::FGR64RegClass.contains(SrcReg)) 148 Opc = Mips::DMFC1; 149 } 150 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 151 if (Mips::HIRegs64RegClass.contains(DestReg)) 152 Opc = Mips::MTHI64, DestReg = 0; 153 else if (Mips::LORegs64RegClass.contains(DestReg)) 154 Opc = Mips::MTLO64, DestReg = 0; 155 else if (Mips::FGR64RegClass.contains(DestReg)) 156 Opc = Mips::DMTC1; 157 } 158 159 assert(Opc && "Cannot copy registers"); 160 161 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 162 163 if (DestReg) 164 MIB.addReg(DestReg, RegState::Define); 165 166 if (SrcReg) 167 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 168 169 if (ZeroReg) 170 MIB.addReg(ZeroReg); 171} 172 173void MipsSEInstrInfo:: 174storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 175 unsigned SrcReg, bool isKill, int FI, 176 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 177 int64_t Offset) const { 178 DebugLoc DL; 179 if (I != MBB.end()) DL = I->getDebugLoc(); 180 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 181 182 unsigned Opc = 0; 183 184 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) 185 Opc = IsN64 ? Mips::SW_P8 : Mips::SW; 186 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) 187 Opc = IsN64 ? Mips::SD_P8 : Mips::SD; 188 else if (Mips::ACRegsRegClass.hasSubClassEq(RC)) 189 Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64; 190 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC)) 191 Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP; 192 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC)) 193 Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128; 194 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 195 Opc = IsN64 ? Mips::STORE_CCOND_DSP_P8 : Mips::STORE_CCOND_DSP; 196 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 197 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1; 198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 199 Opc = Mips::SDC1; 200 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 201 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164; 202 203 assert(Opc && "Register class not handled!"); 204 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 205 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 206} 207 208void MipsSEInstrInfo:: 209loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 210 unsigned DestReg, int FI, const TargetRegisterClass *RC, 211 const TargetRegisterInfo *TRI, int64_t Offset) const { 212 DebugLoc DL; 213 if (I != MBB.end()) DL = I->getDebugLoc(); 214 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 215 unsigned Opc = 0; 216 217 if (Mips::CPURegsRegClass.hasSubClassEq(RC)) 218 Opc = IsN64 ? Mips::LW_P8 : Mips::LW; 219 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC)) 220 Opc = IsN64 ? Mips::LD_P8 : Mips::LD; 221 else if (Mips::ACRegsRegClass.hasSubClassEq(RC)) 222 Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64; 223 else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC)) 224 Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP; 225 else if (Mips::ACRegs128RegClass.hasSubClassEq(RC)) 226 Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128; 227 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 228 Opc = IsN64 ? Mips::LOAD_CCOND_DSP_P8 : Mips::LOAD_CCOND_DSP; 229 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 230 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; 231 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 232 Opc = Mips::LDC1; 233 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 234 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164; 235 236 assert(Opc && "Register class not handled!"); 237 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) 238 .addMemOperand(MMO); 239} 240 241bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 242 MachineBasicBlock &MBB = *MI->getParent(); 243 244 switch(MI->getDesc().getOpcode()) { 245 default: 246 return false; 247 case Mips::RetRA: 248 ExpandRetRA(MBB, MI, Mips::RET); 249 break; 250 case Mips::BuildPairF64: 251 ExpandBuildPairF64(MBB, MI); 252 break; 253 case Mips::ExtractElementF64: 254 ExpandExtractElementF64(MBB, MI); 255 break; 256 case Mips::MIPSeh_return32: 257 case Mips::MIPSeh_return64: 258 ExpandEhReturn(MBB, MI); 259 break; 260 } 261 262 MBB.erase(MI); 263 return true; 264} 265 266/// GetOppositeBranchOpc - Return the inverse of the specified 267/// opcode, e.g. turning BEQ to BNE. 268unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const { 269 switch (Opc) { 270 default: llvm_unreachable("Illegal opcode!"); 271 case Mips::BEQ: return Mips::BNE; 272 case Mips::BNE: return Mips::BEQ; 273 case Mips::BGTZ: return Mips::BLEZ; 274 case Mips::BGEZ: return Mips::BLTZ; 275 case Mips::BLTZ: return Mips::BGEZ; 276 case Mips::BLEZ: return Mips::BGTZ; 277 case Mips::BEQ64: return Mips::BNE64; 278 case Mips::BNE64: return Mips::BEQ64; 279 case Mips::BGTZ64: return Mips::BLEZ64; 280 case Mips::BGEZ64: return Mips::BLTZ64; 281 case Mips::BLTZ64: return Mips::BGEZ64; 282 case Mips::BLEZ64: return Mips::BGTZ64; 283 case Mips::BC1T: return Mips::BC1F; 284 case Mips::BC1F: return Mips::BC1T; 285 } 286} 287 288/// Adjust SP by Amount bytes. 289void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 290 MachineBasicBlock &MBB, 291 MachineBasicBlock::iterator I) const { 292 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 293 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 294 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 295 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; 296 297 if (isInt<16>(Amount))// addi sp, sp, amount 298 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 299 else { // Expand immediate that doesn't fit in 16-bit. 300 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); 301 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 302 } 303} 304 305/// This function generates the sequence of instructions needed to get the 306/// result of adding register REG and immediate IMM. 307unsigned 308MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 309 MachineBasicBlock::iterator II, DebugLoc DL, 310 unsigned *NewImm) const { 311 MipsAnalyzeImmediate AnalyzeImm; 312 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 313 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 314 unsigned Size = STI.isABI_N64() ? 64 : 32; 315 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 316 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 317 const TargetRegisterClass *RC = STI.isABI_N64() ? 318 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass; 319 bool LastInstrIsADDiu = NewImm; 320 321 const MipsAnalyzeImmediate::InstSeq &Seq = 322 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 323 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 324 325 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 326 327 // The first instruction can be a LUi, which is different from other 328 // instructions (ADDiu, ORI and SLL) in that it does not have a register 329 // operand. 330 unsigned Reg = RegInfo.createVirtualRegister(RC); 331 332 if (Inst->Opc == LUi) 333 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 334 else 335 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 336 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 337 338 // Build the remaining instructions in Seq. 339 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 340 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 341 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 342 343 if (LastInstrIsADDiu) 344 *NewImm = Inst->ImmOpnd; 345 346 return Reg; 347} 348 349unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { 350 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 351 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 352 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || 353 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || 354 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || 355 Opc == Mips::J) ? 356 Opc : 0; 357} 358 359void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator I, 361 unsigned Opc) const { 362 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA); 363} 364 365void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator I) const { 367 unsigned DstReg = I->getOperand(0).getReg(); 368 unsigned SrcReg = I->getOperand(1).getReg(); 369 unsigned N = I->getOperand(2).getImm(); 370 const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1); 371 DebugLoc dl = I->getDebugLoc(); 372 373 assert(N < 2 && "Invalid immediate"); 374 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; 375 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 376 377 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); 378} 379 380void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator I) const { 382 unsigned DstReg = I->getOperand(0).getReg(); 383 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 384 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 385 DebugLoc dl = I->getDebugLoc(); 386 const TargetRegisterInfo &TRI = getRegisterInfo(); 387 388 // mtc1 Lo, $fp 389 // mtc1 Hi, $fp + 1 390 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven)) 391 .addReg(LoReg); 392 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd)) 393 .addReg(HiReg); 394} 395 396void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB, 397 MachineBasicBlock::iterator I) const { 398 // This pseudo instruction is generated as part of the lowering of 399 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 400 // indirect jump to TargetReg 401 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); 402 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 403 unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR; 404 unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR; 405 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 406 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; 407 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9; 408 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 409 unsigned OffsetReg = I->getOperand(0).getReg(); 410 unsigned TargetReg = I->getOperand(1).getReg(); 411 412 // or $ra, $v0, $zero 413 // addu $sp, $sp, $v1 414 // jr $ra 415 if (TM.getRelocationModel() == Reloc::PIC_) 416 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), T9) 417 .addReg(TargetReg).addReg(ZERO); 418 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA) 419 .addReg(TargetReg).addReg(ZERO); 420 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP) 421 .addReg(SP).addReg(OffsetReg); 422 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA); 423} 424 425const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) { 426 return new MipsSEInstrInfo(TM); 427} 428