MipsSEInstrInfo.cpp revision a98a486ad194c38293efcc5359d6ed2493f950dc 
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
28                                   cl::desc("Expand double precision loads and "
29                                            "stores to their single precision "
30                                            "counterparts."));
31
32MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
33  : MipsInstrInfo(tm,
34                  tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
35    RI(*tm.getSubtargetImpl()),
36    IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
37
38const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
39  return RI;
40}
41
42/// isLoadFromStackSlot - If the specified machine instruction is a direct
43/// load from a stack slot, return the virtual or physical register number of
44/// the destination along with the FrameIndex of the loaded stack slot.  If
45/// not, return 0.  This predicate must return 0 if the instruction has
46/// any side effects other than loading from the stack slot.
47unsigned MipsSEInstrInfo::
48isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
49{
50  unsigned Opc = MI->getOpcode();
51
52  if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
53      (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
54    if ((MI->getOperand(1).isFI()) && // is a stack slot
55        (MI->getOperand(2).isImm()) &&  // the imm is zero
56        (isZeroImm(MI->getOperand(2)))) {
57      FrameIndex = MI->getOperand(1).getIndex();
58      return MI->getOperand(0).getReg();
59    }
60  }
61
62  return 0;
63}
64
65/// isStoreToStackSlot - If the specified machine instruction is a direct
66/// store to a stack slot, return the virtual or physical register number of
67/// the source reg along with the FrameIndex of the loaded stack slot.  If
68/// not, return 0.  This predicate must return 0 if the instruction has
69/// any side effects other than storing to the stack slot.
70unsigned MipsSEInstrInfo::
71isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
72{
73  unsigned Opc = MI->getOpcode();
74
75  if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
76      (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
77    if ((MI->getOperand(1).isFI()) && // is a stack slot
78        (MI->getOperand(2).isImm()) &&  // the imm is zero
79        (isZeroImm(MI->getOperand(2)))) {
80      FrameIndex = MI->getOperand(1).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83  }
84  return 0;
85}
86
87void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
88                                  MachineBasicBlock::iterator I, DebugLoc DL,
89                                  unsigned DestReg, unsigned SrcReg,
90                                  bool KillSrc) const {
91  unsigned Opc = 0, ZeroReg = 0;
92
93  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
94    if (Mips::GPR32RegClass.contains(SrcReg))
95      Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
96    else if (Mips::CCRRegClass.contains(SrcReg))
97      Opc = Mips::CFC1;
98    else if (Mips::FGR32RegClass.contains(SrcReg))
99      Opc = Mips::MFC1;
100    else if (Mips::HI32RegClass.contains(SrcReg))
101      Opc = Mips::MFHI, SrcReg = 0;
102    else if (Mips::LO32RegClass.contains(SrcReg))
103      Opc = Mips::MFLO, SrcReg = 0;
104    else if (Mips::HI32DSPRegClass.contains(SrcReg))
105      Opc = Mips::MFHI_DSP;
106    else if (Mips::LO32DSPRegClass.contains(SrcReg))
107      Opc = Mips::MFLO_DSP;
108    else if (Mips::DSPCCRegClass.contains(SrcReg)) {
109      BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
110        .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
111      return;
112    }
113  }
114  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115    if (Mips::CCRRegClass.contains(DestReg))
116      Opc = Mips::CTC1;
117    else if (Mips::FGR32RegClass.contains(DestReg))
118      Opc = Mips::MTC1;
119    else if (Mips::HI32RegClass.contains(DestReg))
120      Opc = Mips::MTHI, DestReg = 0;
121    else if (Mips::LO32RegClass.contains(DestReg))
122      Opc = Mips::MTLO, DestReg = 0;
123    else if (Mips::HI32DSPRegClass.contains(DestReg))
124      Opc = Mips::MTHI_DSP;
125    else if (Mips::LO32DSPRegClass.contains(DestReg))
126      Opc = Mips::MTLO_DSP;
127    else if (Mips::DSPCCRegClass.contains(DestReg)) {
128      BuildMI(MBB, I, DL, get(Mips::WRDSP))
129        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130        .addReg(DestReg, RegState::ImplicitDefine);
131      return;
132    }
133  }
134  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
135    Opc = Mips::FMOV_S;
136  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
137    Opc = Mips::FMOV_D32;
138  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
139    Opc = Mips::FMOV_D64;
140  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
141    if (Mips::GPR64RegClass.contains(SrcReg))
142      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
143    else if (Mips::HI64RegClass.contains(SrcReg))
144      Opc = Mips::MFHI64, SrcReg = 0;
145    else if (Mips::LO64RegClass.contains(SrcReg))
146      Opc = Mips::MFLO64, SrcReg = 0;
147    else if (Mips::FGR64RegClass.contains(SrcReg))
148      Opc = Mips::DMFC1;
149  }
150  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
151    if (Mips::HI64RegClass.contains(DestReg))
152      Opc = Mips::MTHI64, DestReg = 0;
153    else if (Mips::LO64RegClass.contains(DestReg))
154      Opc = Mips::MTLO64, DestReg = 0;
155    else if (Mips::FGR64RegClass.contains(DestReg))
156      Opc = Mips::DMTC1;
157  }
158
159  assert(Opc && "Cannot copy registers");
160
161  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
162
163  if (DestReg)
164    MIB.addReg(DestReg, RegState::Define);
165
166  if (SrcReg)
167    MIB.addReg(SrcReg, getKillRegState(KillSrc));
168
169  if (ZeroReg)
170    MIB.addReg(ZeroReg);
171}
172
173void MipsSEInstrInfo::
174storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
175                unsigned SrcReg, bool isKill, int FI,
176                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
177                int64_t Offset) const {
178  DebugLoc DL;
179  if (I != MBB.end()) DL = I->getDebugLoc();
180  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
181
182  unsigned Opc = 0;
183
184  if (Mips::GPR32RegClass.hasSubClassEq(RC))
185    Opc = Mips::SW;
186  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
187    Opc = Mips::SD;
188  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
189    Opc = Mips::STORE_ACC64;
190  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
191    Opc = Mips::STORE_ACC64DSP;
192  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
193    Opc = Mips::STORE_ACC128;
194  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
195    Opc = Mips::STORE_CCOND_DSP;
196  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
197    Opc = Mips::SWC1;
198  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
199    Opc = Mips::SDC1;
200  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
201    Opc = Mips::SDC164;
202
203  assert(Opc && "Register class not handled!");
204  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
205    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
206}
207
208void MipsSEInstrInfo::
209loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
210                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
211                 const TargetRegisterInfo *TRI, int64_t Offset) const {
212  DebugLoc DL;
213  if (I != MBB.end()) DL = I->getDebugLoc();
214  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
215  unsigned Opc = 0;
216
217  if (Mips::GPR32RegClass.hasSubClassEq(RC))
218    Opc = Mips::LW;
219  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
220    Opc = Mips::LD;
221  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
222    Opc = Mips::LOAD_ACC64;
223  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
224    Opc = Mips::LOAD_ACC64DSP;
225  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
226    Opc = Mips::LOAD_ACC128;
227  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
228    Opc = Mips::LOAD_CCOND_DSP;
229  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
230    Opc = Mips::LWC1;
231  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
232    Opc = Mips::LDC1;
233  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
234    Opc = Mips::LDC164;
235
236  assert(Opc && "Register class not handled!");
237  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
238    .addMemOperand(MMO);
239}
240
241bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
242  MachineBasicBlock &MBB = *MI->getParent();
243
244  switch(MI->getDesc().getOpcode()) {
245  default:
246    return false;
247  case Mips::RetRA:
248    expandRetRA(MBB, MI, Mips::RET);
249    break;
250  case Mips::PseudoCVT_S_W:
251    expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
252    break;
253  case Mips::PseudoCVT_D32_W:
254    expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
255    break;
256  case Mips::PseudoCVT_S_L:
257    expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
258    break;
259  case Mips::PseudoCVT_D64_W:
260    expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
261    break;
262  case Mips::PseudoCVT_D64_L:
263    expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
264    break;
265  case Mips::BuildPairF64:
266    expandBuildPairF64(MBB, MI);
267    break;
268  case Mips::ExtractElementF64:
269    expandExtractElementF64(MBB, MI);
270    break;
271  case Mips::PseudoLDC1:
272    expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1);
273    break;
274  case Mips::PseudoSDC1:
275    expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1);
276    break;
277  case Mips::MIPSeh_return32:
278  case Mips::MIPSeh_return64:
279    expandEhReturn(MBB, MI);
280    break;
281  }
282
283  MBB.erase(MI);
284  return true;
285}
286
287/// getOppositeBranchOpc - Return the inverse of the specified
288/// opcode, e.g. turning BEQ to BNE.
289unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
290  switch (Opc) {
291  default:           llvm_unreachable("Illegal opcode!");
292  case Mips::BEQ:    return Mips::BNE;
293  case Mips::BNE:    return Mips::BEQ;
294  case Mips::BGTZ:   return Mips::BLEZ;
295  case Mips::BGEZ:   return Mips::BLTZ;
296  case Mips::BLTZ:   return Mips::BGEZ;
297  case Mips::BLEZ:   return Mips::BGTZ;
298  case Mips::BEQ64:  return Mips::BNE64;
299  case Mips::BNE64:  return Mips::BEQ64;
300  case Mips::BGTZ64: return Mips::BLEZ64;
301  case Mips::BGEZ64: return Mips::BLTZ64;
302  case Mips::BLTZ64: return Mips::BGEZ64;
303  case Mips::BLEZ64: return Mips::BGTZ64;
304  case Mips::BC1T:   return Mips::BC1F;
305  case Mips::BC1F:   return Mips::BC1T;
306  }
307}
308
309/// Adjust SP by Amount bytes.
310void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
311                                     MachineBasicBlock &MBB,
312                                     MachineBasicBlock::iterator I) const {
313  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
314  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
315  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
316  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
317
318  if (isInt<16>(Amount))// addi sp, sp, amount
319    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
320  else { // Expand immediate that doesn't fit in 16-bit.
321    unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
322    BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
323  }
324}
325
326/// This function generates the sequence of instructions needed to get the
327/// result of adding register REG and immediate IMM.
328unsigned
329MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
330                               MachineBasicBlock::iterator II, DebugLoc DL,
331                               unsigned *NewImm) const {
332  MipsAnalyzeImmediate AnalyzeImm;
333  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
334  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
335  unsigned Size = STI.isABI_N64() ? 64 : 32;
336  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
337  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
338  const TargetRegisterClass *RC = STI.isABI_N64() ?
339    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
340  bool LastInstrIsADDiu = NewImm;
341
342  const MipsAnalyzeImmediate::InstSeq &Seq =
343    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
344  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
345
346  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
347
348  // The first instruction can be a LUi, which is different from other
349  // instructions (ADDiu, ORI and SLL) in that it does not have a register
350  // operand.
351  unsigned Reg = RegInfo.createVirtualRegister(RC);
352
353  if (Inst->Opc == LUi)
354    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
355  else
356    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
357      .addImm(SignExtend64<16>(Inst->ImmOpnd));
358
359  // Build the remaining instructions in Seq.
360  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
361    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
362      .addImm(SignExtend64<16>(Inst->ImmOpnd));
363
364  if (LastInstrIsADDiu)
365    *NewImm = Inst->ImmOpnd;
366
367  return Reg;
368}
369
370unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
371  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
372          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
373          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
374          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
375          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
376          Opc == Mips::J) ?
377         Opc : 0;
378}
379
380void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
381                                MachineBasicBlock::iterator I,
382                                unsigned Opc) const {
383  BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
384}
385
386std::pair<bool, bool>
387MipsSEInstrInfo::compareOpndSize(unsigned Opc,
388                                 const MachineFunction &MF) const {
389  const MCInstrDesc &Desc = get(Opc);
390  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
391  const MipsRegisterInfo *RI = &getRegisterInfo();
392  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
393  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
394
395  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
396}
397
398void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
399                                     MachineBasicBlock::iterator I,
400                                     unsigned CvtOpc, unsigned MovOpc,
401                                     bool IsI64) const {
402  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
403  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
404  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
405  unsigned KillSrc =  getKillRegState(Src.isKill());
406  DebugLoc DL = I->getDebugLoc();
407  unsigned SubIdx = (IsI64 ? Mips::sub_32 : Mips::sub_fpeven);
408  bool DstIsLarger, SrcIsLarger;
409
410  tie(DstIsLarger, SrcIsLarger) = compareOpndSize(CvtOpc, *MBB.getParent());
411
412  if (DstIsLarger)
413    TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
414
415  if (SrcIsLarger)
416    DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
417
418  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
419  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
420}
421
422void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
423                                          MachineBasicBlock::iterator I) const {
424  unsigned DstReg = I->getOperand(0).getReg();
425  unsigned SrcReg = I->getOperand(1).getReg();
426  unsigned N = I->getOperand(2).getImm();
427  const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
428  DebugLoc dl = I->getDebugLoc();
429
430  assert(N < 2 && "Invalid immediate");
431  unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
432  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
433
434  BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
435}
436
437void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
438                                       MachineBasicBlock::iterator I) const {
439  unsigned DstReg = I->getOperand(0).getReg();
440  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
441  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
442  DebugLoc dl = I->getDebugLoc();
443  const TargetRegisterInfo &TRI = getRegisterInfo();
444
445  // mtc1 Lo, $fp
446  // mtc1 Hi, $fp + 1
447  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
448    .addReg(LoReg);
449  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
450    .addReg(HiReg);
451}
452
453/// Add 4 to the displacement of operand MO.
454static void fixDisp(MachineOperand &MO) {
455  switch (MO.getType()) {
456  default:
457    llvm_unreachable("Unhandled operand type.");
458  case MachineOperand::MO_Immediate:
459    MO.setImm(MO.getImm() + 4);
460    break;
461  case MachineOperand::MO_GlobalAddress:
462  case MachineOperand::MO_ConstantPoolIndex:
463  case MachineOperand::MO_BlockAddress:
464  case MachineOperand::MO_TargetIndex:
465  case MachineOperand::MO_ExternalSymbol:
466    MO.setOffset(MO.getOffset() + 4);
467    break;
468  }
469}
470
471void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB,
472                                        MachineBasicBlock::iterator I,
473                                        unsigned OpcD, unsigned OpcS) const {
474  // If NoDPLoadStore is false, just change the opcode.
475  if (!NoDPLoadStore) {
476    genInstrWithNewOpc(OpcD, I);
477    return;
478  }
479
480  // Expand a double precision FP load or store to two single precision
481  // instructions.
482
483  const TargetRegisterInfo &TRI = getRegisterInfo();
484  const MachineOperand &ValReg = I->getOperand(0);
485  unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpeven);
486  unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpodd);
487
488  if (!TM.getSubtarget<MipsSubtarget>().isLittle())
489    std::swap(LoReg, HiReg);
490
491  // Create an instruction which loads from or stores to the lower memory
492  // address.
493  MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
494  MIB->getOperand(0).setReg(LoReg);
495
496  // Create an instruction which loads from or stores to the higher memory
497  // address.
498  MIB = genInstrWithNewOpc(OpcS, I);
499  MIB->getOperand(0).setReg(HiReg);
500  fixDisp(MIB->getOperand(2));
501}
502
503void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
504                                     MachineBasicBlock::iterator I) const {
505  // This pseudo instruction is generated as part of the lowering of
506  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
507  // indirect jump to TargetReg
508  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
509  unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
510  unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
511  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
512  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
513  unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
514  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
515  unsigned OffsetReg = I->getOperand(0).getReg();
516  unsigned TargetReg = I->getOperand(1).getReg();
517
518  // addu $ra, $v0, $zero
519  // addu $sp, $sp, $v1
520  // jr   $ra
521  if (TM.getRelocationModel() == Reloc::PIC_)
522    BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
523        .addReg(TargetReg).addReg(ZERO);
524  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
525      .addReg(TargetReg).addReg(ZERO);
526  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
527      .addReg(SP).addReg(OffsetReg);
528  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
529}
530
531const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
532  return new MipsSEInstrInfo(TM);
533}
534