MipsSEInstrInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSEInstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
28  : MipsInstrInfo(tm,
29                  tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
30    RI(*tm.getSubtargetImpl()),
31    IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
32
33const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
34  return RI;
35}
36
37/// isLoadFromStackSlot - If the specified machine instruction is a direct
38/// load from a stack slot, return the virtual or physical register number of
39/// the destination along with the FrameIndex of the loaded stack slot.  If
40/// not, return 0.  This predicate must return 0 if the instruction has
41/// any side effects other than loading from the stack slot.
42unsigned MipsSEInstrInfo::
43isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44{
45  unsigned Opc = MI->getOpcode();
46
47  if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
48      (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
49    if ((MI->getOperand(1).isFI()) && // is a stack slot
50        (MI->getOperand(2).isImm()) &&  // the imm is zero
51        (isZeroImm(MI->getOperand(2)))) {
52      FrameIndex = MI->getOperand(1).getIndex();
53      return MI->getOperand(0).getReg();
54    }
55  }
56
57  return 0;
58}
59
60/// isStoreToStackSlot - If the specified machine instruction is a direct
61/// store to a stack slot, return the virtual or physical register number of
62/// the source reg along with the FrameIndex of the loaded stack slot.  If
63/// not, return 0.  This predicate must return 0 if the instruction has
64/// any side effects other than storing to the stack slot.
65unsigned MipsSEInstrInfo::
66isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
67{
68  unsigned Opc = MI->getOpcode();
69
70  if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
71      (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
72    if ((MI->getOperand(1).isFI()) && // is a stack slot
73        (MI->getOperand(2).isImm()) &&  // the imm is zero
74        (isZeroImm(MI->getOperand(2)))) {
75      FrameIndex = MI->getOperand(1).getIndex();
76      return MI->getOperand(0).getReg();
77    }
78  }
79  return 0;
80}
81
82void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
83                                  MachineBasicBlock::iterator I, DebugLoc DL,
84                                  unsigned DestReg, unsigned SrcReg,
85                                  bool KillSrc) const {
86  unsigned Opc = 0, ZeroReg = 0;
87  bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
88
89  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
90    if (Mips::GPR32RegClass.contains(SrcReg)) {
91      if (isMicroMips)
92        Opc = Mips::MOVE16_MM;
93      else
94        Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
95    } else if (Mips::CCRRegClass.contains(SrcReg))
96      Opc = Mips::CFC1;
97    else if (Mips::FGR32RegClass.contains(SrcReg))
98      Opc = Mips::MFC1;
99    else if (Mips::HI32RegClass.contains(SrcReg)) {
100      Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
101      SrcReg = 0;
102    } else if (Mips::LO32RegClass.contains(SrcReg)) {
103      Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
104      SrcReg = 0;
105    } else if (Mips::HI32DSPRegClass.contains(SrcReg))
106      Opc = Mips::MFHI_DSP;
107    else if (Mips::LO32DSPRegClass.contains(SrcReg))
108      Opc = Mips::MFLO_DSP;
109    else if (Mips::DSPCCRegClass.contains(SrcReg)) {
110      BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
111        .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
112      return;
113    }
114    else if (Mips::MSACtrlRegClass.contains(SrcReg))
115      Opc = Mips::CFCMSA;
116  }
117  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
118    if (Mips::CCRRegClass.contains(DestReg))
119      Opc = Mips::CTC1;
120    else if (Mips::FGR32RegClass.contains(DestReg))
121      Opc = Mips::MTC1;
122    else if (Mips::HI32RegClass.contains(DestReg))
123      Opc = Mips::MTHI, DestReg = 0;
124    else if (Mips::LO32RegClass.contains(DestReg))
125      Opc = Mips::MTLO, DestReg = 0;
126    else if (Mips::HI32DSPRegClass.contains(DestReg))
127      Opc = Mips::MTHI_DSP;
128    else if (Mips::LO32DSPRegClass.contains(DestReg))
129      Opc = Mips::MTLO_DSP;
130    else if (Mips::DSPCCRegClass.contains(DestReg)) {
131      BuildMI(MBB, I, DL, get(Mips::WRDSP))
132        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
133        .addReg(DestReg, RegState::ImplicitDefine);
134      return;
135    }
136    else if (Mips::MSACtrlRegClass.contains(DestReg))
137      Opc = Mips::CTCMSA;
138  }
139  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140    Opc = Mips::FMOV_S;
141  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142    Opc = Mips::FMOV_D32;
143  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144    Opc = Mips::FMOV_D64;
145  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146    if (Mips::GPR64RegClass.contains(SrcReg))
147      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
148    else if (Mips::HI64RegClass.contains(SrcReg))
149      Opc = Mips::MFHI64, SrcReg = 0;
150    else if (Mips::LO64RegClass.contains(SrcReg))
151      Opc = Mips::MFLO64, SrcReg = 0;
152    else if (Mips::FGR64RegClass.contains(SrcReg))
153      Opc = Mips::DMFC1;
154  }
155  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156    if (Mips::HI64RegClass.contains(DestReg))
157      Opc = Mips::MTHI64, DestReg = 0;
158    else if (Mips::LO64RegClass.contains(DestReg))
159      Opc = Mips::MTLO64, DestReg = 0;
160    else if (Mips::FGR64RegClass.contains(DestReg))
161      Opc = Mips::DMTC1;
162  }
163  else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164    if (Mips::MSA128BRegClass.contains(SrcReg))
165      Opc = Mips::MOVE_V;
166  }
167
168  assert(Opc && "Cannot copy registers");
169
170  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
171
172  if (DestReg)
173    MIB.addReg(DestReg, RegState::Define);
174
175  if (SrcReg)
176    MIB.addReg(SrcReg, getKillRegState(KillSrc));
177
178  if (ZeroReg)
179    MIB.addReg(ZeroReg);
180}
181
182void MipsSEInstrInfo::
183storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184                unsigned SrcReg, bool isKill, int FI,
185                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186                int64_t Offset) const {
187  DebugLoc DL;
188  if (I != MBB.end()) DL = I->getDebugLoc();
189  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
190
191  unsigned Opc = 0;
192
193  if (Mips::GPR32RegClass.hasSubClassEq(RC))
194    Opc = Mips::SW;
195  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196    Opc = Mips::SD;
197  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
198    Opc = Mips::STORE_ACC64;
199  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
200    Opc = Mips::STORE_ACC64DSP;
201  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
202    Opc = Mips::STORE_ACC128;
203  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
204    Opc = Mips::STORE_CCOND_DSP;
205  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206    Opc = Mips::SWC1;
207  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208    Opc = Mips::SDC1;
209  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
210    Opc = Mips::SDC164;
211  else if (RC->hasType(MVT::v16i8))
212    Opc = Mips::ST_B;
213  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
214    Opc = Mips::ST_H;
215  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
216    Opc = Mips::ST_W;
217  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
218    Opc = Mips::ST_D;
219
220  assert(Opc && "Register class not handled!");
221  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
222    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
223}
224
225void MipsSEInstrInfo::
226loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
227                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
228                 const TargetRegisterInfo *TRI, int64_t Offset) const {
229  DebugLoc DL;
230  if (I != MBB.end()) DL = I->getDebugLoc();
231  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
232  unsigned Opc = 0;
233
234  if (Mips::GPR32RegClass.hasSubClassEq(RC))
235    Opc = Mips::LW;
236  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
237    Opc = Mips::LD;
238  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
239    Opc = Mips::LOAD_ACC64;
240  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
241    Opc = Mips::LOAD_ACC64DSP;
242  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
243    Opc = Mips::LOAD_ACC128;
244  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
245    Opc = Mips::LOAD_CCOND_DSP;
246  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
247    Opc = Mips::LWC1;
248  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
249    Opc = Mips::LDC1;
250  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
251    Opc = Mips::LDC164;
252  else if (RC->hasType(MVT::v16i8))
253    Opc = Mips::LD_B;
254  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
255    Opc = Mips::LD_H;
256  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
257    Opc = Mips::LD_W;
258  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
259    Opc = Mips::LD_D;
260
261  assert(Opc && "Register class not handled!");
262  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
263    .addMemOperand(MMO);
264}
265
266bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
267  MachineBasicBlock &MBB = *MI->getParent();
268  bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
269  unsigned Opc;
270
271  switch(MI->getDesc().getOpcode()) {
272  default:
273    return false;
274  case Mips::RetRA:
275    expandRetRA(MBB, MI, Mips::RET);
276    break;
277  case Mips::PseudoMFHI:
278    Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
279    expandPseudoMFHiLo(MBB, MI, Opc);
280    break;
281  case Mips::PseudoMFLO:
282    Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
283    expandPseudoMFHiLo(MBB, MI, Opc);
284    break;
285  case Mips::PseudoMFHI64:
286    expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
287    break;
288  case Mips::PseudoMFLO64:
289    expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
290    break;
291  case Mips::PseudoMTLOHI:
292    expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
293    break;
294  case Mips::PseudoMTLOHI64:
295    expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
296    break;
297  case Mips::PseudoMTLOHI_DSP:
298    expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
299    break;
300  case Mips::PseudoCVT_S_W:
301    expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
302    break;
303  case Mips::PseudoCVT_D32_W:
304    expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
305    break;
306  case Mips::PseudoCVT_S_L:
307    expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
308    break;
309  case Mips::PseudoCVT_D64_W:
310    expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
311    break;
312  case Mips::PseudoCVT_D64_L:
313    expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
314    break;
315  case Mips::BuildPairF64:
316    expandBuildPairF64(MBB, MI, false);
317    break;
318  case Mips::BuildPairF64_64:
319    expandBuildPairF64(MBB, MI, true);
320    break;
321  case Mips::ExtractElementF64:
322    expandExtractElementF64(MBB, MI, false);
323    break;
324  case Mips::ExtractElementF64_64:
325    expandExtractElementF64(MBB, MI, true);
326    break;
327  case Mips::MIPSeh_return32:
328  case Mips::MIPSeh_return64:
329    expandEhReturn(MBB, MI);
330    break;
331  }
332
333  MBB.erase(MI);
334  return true;
335}
336
337/// getOppositeBranchOpc - Return the inverse of the specified
338/// opcode, e.g. turning BEQ to BNE.
339unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
340  switch (Opc) {
341  default:           llvm_unreachable("Illegal opcode!");
342  case Mips::BEQ:    return Mips::BNE;
343  case Mips::BNE:    return Mips::BEQ;
344  case Mips::BGTZ:   return Mips::BLEZ;
345  case Mips::BGEZ:   return Mips::BLTZ;
346  case Mips::BLTZ:   return Mips::BGEZ;
347  case Mips::BLEZ:   return Mips::BGTZ;
348  case Mips::BEQ64:  return Mips::BNE64;
349  case Mips::BNE64:  return Mips::BEQ64;
350  case Mips::BGTZ64: return Mips::BLEZ64;
351  case Mips::BGEZ64: return Mips::BLTZ64;
352  case Mips::BLTZ64: return Mips::BGEZ64;
353  case Mips::BLEZ64: return Mips::BGTZ64;
354  case Mips::BC1T:   return Mips::BC1F;
355  case Mips::BC1F:   return Mips::BC1T;
356  }
357}
358
359/// Adjust SP by Amount bytes.
360void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
361                                     MachineBasicBlock &MBB,
362                                     MachineBasicBlock::iterator I) const {
363  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
364  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
365  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
366  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
367
368  if (isInt<16>(Amount))// addi sp, sp, amount
369    BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
370  else { // Expand immediate that doesn't fit in 16-bit.
371    unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
372    BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
373  }
374}
375
376/// This function generates the sequence of instructions needed to get the
377/// result of adding register REG and immediate IMM.
378unsigned
379MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
380                               MachineBasicBlock::iterator II, DebugLoc DL,
381                               unsigned *NewImm) const {
382  MipsAnalyzeImmediate AnalyzeImm;
383  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
384  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
385  unsigned Size = STI.isABI_N64() ? 64 : 32;
386  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
387  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
388  const TargetRegisterClass *RC = STI.isABI_N64() ?
389    &Mips::GPR64RegClass : &Mips::GPR32RegClass;
390  bool LastInstrIsADDiu = NewImm;
391
392  const MipsAnalyzeImmediate::InstSeq &Seq =
393    AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
394  MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
395
396  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
397
398  // The first instruction can be a LUi, which is different from other
399  // instructions (ADDiu, ORI and SLL) in that it does not have a register
400  // operand.
401  unsigned Reg = RegInfo.createVirtualRegister(RC);
402
403  if (Inst->Opc == LUi)
404    BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
405  else
406    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
407      .addImm(SignExtend64<16>(Inst->ImmOpnd));
408
409  // Build the remaining instructions in Seq.
410  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
411    BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
412      .addImm(SignExtend64<16>(Inst->ImmOpnd));
413
414  if (LastInstrIsADDiu)
415    *NewImm = Inst->ImmOpnd;
416
417  return Reg;
418}
419
420unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
421  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
422          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
423          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
424          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
425          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
426          Opc == Mips::J) ?
427         Opc : 0;
428}
429
430void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
431                                MachineBasicBlock::iterator I,
432                                unsigned Opc) const {
433  BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
434}
435
436std::pair<bool, bool>
437MipsSEInstrInfo::compareOpndSize(unsigned Opc,
438                                 const MachineFunction &MF) const {
439  const MCInstrDesc &Desc = get(Opc);
440  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
441  const MipsRegisterInfo *RI = &getRegisterInfo();
442  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
443  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
444
445  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
446}
447
448void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
449                                         MachineBasicBlock::iterator I,
450                                         unsigned NewOpc) const {
451  BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
452}
453
454void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
455                                         MachineBasicBlock::iterator I,
456                                         unsigned LoOpc,
457                                         unsigned HiOpc,
458                                         bool HasExplicitDef) const {
459  // Expand
460  //  lo_hi pseudomtlohi $gpr0, $gpr1
461  // to these two instructions:
462  //  mtlo $gpr0
463  //  mthi $gpr1
464
465  DebugLoc DL = I->getDebugLoc();
466  const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
467  MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
468  MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
469  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
470  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
471
472  // Add lo/hi registers if the mtlo/hi instructions created have explicit
473  // def registers.
474  if (HasExplicitDef) {
475    unsigned DstReg = I->getOperand(0).getReg();
476    unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
477    unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
478    LoInst.addReg(DstLo, RegState::Define);
479    HiInst.addReg(DstHi, RegState::Define);
480  }
481}
482
483void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
484                                     MachineBasicBlock::iterator I,
485                                     unsigned CvtOpc, unsigned MovOpc,
486                                     bool IsI64) const {
487  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
488  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
489  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
490  unsigned KillSrc =  getKillRegState(Src.isKill());
491  DebugLoc DL = I->getDebugLoc();
492  bool DstIsLarger, SrcIsLarger;
493
494  std::tie(DstIsLarger, SrcIsLarger) =
495      compareOpndSize(CvtOpc, *MBB.getParent());
496
497  if (DstIsLarger)
498    TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
499
500  if (SrcIsLarger)
501    DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
502
503  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
504  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
505}
506
507void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
508                                              MachineBasicBlock::iterator I,
509                                              bool FP64) const {
510  unsigned DstReg = I->getOperand(0).getReg();
511  unsigned SrcReg = I->getOperand(1).getReg();
512  unsigned N = I->getOperand(2).getImm();
513  DebugLoc dl = I->getDebugLoc();
514
515  assert(N < 2 && "Invalid immediate");
516  unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
517  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
518
519  if (SubIdx == Mips::sub_hi && FP64) {
520    // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
521    //        temporarily work around a widespread bug in the -mfp64 support.
522    //        The problem is that none of the 32-bit fpu ops mention the fact
523    //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
524    //        requires a major overhaul of the FPU implementation which can't
525    //        be done right now due to time constraints.
526    //        MFHC1 is one of two instructions that are affected since they are
527    //        the only instructions that don't read the lower 32-bits.
528    //        We therefore pretend that it reads the bottom 32-bits to
529    //        artificially create a dependency and prevent the scheduler
530    //        changing the behaviour of the code.
531    BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
532        SrcReg, RegState::Implicit);
533  } else
534    BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
535}
536
537void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
538                                         MachineBasicBlock::iterator I,
539                                         bool FP64) const {
540  unsigned DstReg = I->getOperand(0).getReg();
541  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
542  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
543  DebugLoc dl = I->getDebugLoc();
544  const TargetRegisterInfo &TRI = getRegisterInfo();
545
546  // For FP32 mode:
547  //   mtc1 Lo, $fp
548  //   mtc1 Hi, $fp + 1
549  // For FP64 mode:
550  //   mtc1 Lo, $fp
551  //   mthc1 Hi, $fp
552
553  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
554    .addReg(LoReg);
555
556  if (FP64) {
557    // FIXME: The .addReg(DstReg, RegState::Implicit) is a white lie used to
558    //        temporarily work around a widespread bug in the -mfp64 support.
559    //        The problem is that none of the 32-bit fpu ops mention the fact
560    //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
561    //        requires a major overhaul of the FPU implementation which can't
562    //        be done right now due to time constraints.
563    //        MTHC1 is one of two instructions that are affected since they are
564    //        the only instructions that don't read the lower 32-bits.
565    //        We therefore pretend that it reads the bottom 32-bits to
566    //        artificially create a dependency and prevent the scheduler
567    //        changing the behaviour of the code.
568    BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
569        .addReg(HiReg)
570        .addReg(DstReg, RegState::Implicit);
571  } else
572    BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
573      .addReg(HiReg);
574}
575
576void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
577                                     MachineBasicBlock::iterator I) const {
578  // This pseudo instruction is generated as part of the lowering of
579  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
580  // indirect jump to TargetReg
581  const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
582  unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
583  unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
584  unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
585  unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
586  unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
587  unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
588  unsigned OffsetReg = I->getOperand(0).getReg();
589  unsigned TargetReg = I->getOperand(1).getReg();
590
591  // addu $ra, $v0, $zero
592  // addu $sp, $sp, $v1
593  // jr   $ra
594  if (TM.getRelocationModel() == Reloc::PIC_)
595    BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
596        .addReg(TargetReg).addReg(ZERO);
597  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
598      .addReg(TargetReg).addReg(ZERO);
599  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
600      .addReg(SP).addReg(OffsetReg);
601  BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
602}
603
604const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
605  return new MipsSEInstrInfo(TM);
606}
607