1//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSEINSTRUCTIONINFO_H
15#define MIPSSEINSTRUCTIONINFO_H
16
17#include "MipsInstrInfo.h"
18#include "MipsSERegisterInfo.h"
19
20namespace llvm {
21
22class MipsSEInstrInfo : public MipsInstrInfo {
23  const MipsSERegisterInfo RI;
24  bool IsN64;
25
26public:
27  explicit MipsSEInstrInfo(MipsTargetMachine &TM);
28
29  const MipsRegisterInfo &getRegisterInfo() const override;
30
31  /// isLoadFromStackSlot - If the specified machine instruction is a direct
32  /// load from a stack slot, return the virtual or physical register number of
33  /// the destination along with the FrameIndex of the loaded stack slot.  If
34  /// not, return 0.  This predicate must return 0 if the instruction has
35  /// any side effects other than loading from the stack slot.
36  unsigned isLoadFromStackSlot(const MachineInstr *MI,
37                               int &FrameIndex) const override;
38
39  /// isStoreToStackSlot - If the specified machine instruction is a direct
40  /// store to a stack slot, return the virtual or physical register number of
41  /// the source reg along with the FrameIndex of the loaded stack slot.  If
42  /// not, return 0.  This predicate must return 0 if the instruction has
43  /// any side effects other than storing to the stack slot.
44  unsigned isStoreToStackSlot(const MachineInstr *MI,
45                              int &FrameIndex) const override;
46
47  void copyPhysReg(MachineBasicBlock &MBB,
48                   MachineBasicBlock::iterator MI, DebugLoc DL,
49                   unsigned DestReg, unsigned SrcReg,
50                   bool KillSrc) const override;
51
52  void storeRegToStack(MachineBasicBlock &MBB,
53                       MachineBasicBlock::iterator MI,
54                       unsigned SrcReg, bool isKill, int FrameIndex,
55                       const TargetRegisterClass *RC,
56                       const TargetRegisterInfo *TRI,
57                       int64_t Offset) const override;
58
59  void loadRegFromStack(MachineBasicBlock &MBB,
60                        MachineBasicBlock::iterator MI,
61                        unsigned DestReg, int FrameIndex,
62                        const TargetRegisterClass *RC,
63                        const TargetRegisterInfo *TRI,
64                        int64_t Offset) const override;
65
66  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
67
68  unsigned getOppositeBranchOpc(unsigned Opc) const override;
69
70  /// Adjust SP by Amount bytes.
71  void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
72                      MachineBasicBlock::iterator I) const;
73
74  /// Emit a series of instructions to load an immediate. If NewImm is a
75  /// non-NULL parameter, the last instruction is not emitted, but instead
76  /// its immediate operand is returned in NewImm.
77  unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
78                         MachineBasicBlock::iterator II, DebugLoc DL,
79                         unsigned *NewImm) const;
80
81private:
82  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
83
84  void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
85
86  std::pair<bool, bool> compareOpndSize(unsigned Opc,
87                                        const MachineFunction &MF) const;
88
89  void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
90                          unsigned NewOpc) const;
91
92  void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
93                          unsigned LoOpc, unsigned HiOpc,
94                          bool HasExplicitDef) const;
95
96  /// Expand pseudo Int-to-FP conversion instructions.
97  ///
98  /// For example, the following pseudo instruction
99  ///  PseudoCVT_D32_W D2, A5
100  /// gets expanded into these two instructions:
101  ///  MTC1 F4, A5
102  ///  CVT_D32_W D2, F4
103  ///
104  /// We do this expansion post-RA to avoid inserting a floating point copy
105  /// instruction between MTC1 and CVT_D32_W.
106  void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107                      unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
108
109  void expandExtractElementF64(MachineBasicBlock &MBB,
110                               MachineBasicBlock::iterator I, bool FP64) const;
111  void expandBuildPairF64(MachineBasicBlock &MBB,
112                          MachineBasicBlock::iterator I, bool FP64) const;
113  void expandEhReturn(MachineBasicBlock &MBB,
114                      MachineBasicBlock::iterator I) const;
115};
116
117}
118
119#endif
120