MipsSERegisterInfo.cpp revision ff4b604f961aa9b9ec2f05a5c31885b19fa636e4 
1//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MipsSERegisterInfo.h"
16#include "Mips.h"
17#include "MipsAnalyzeImmediate.h"
18#include "MipsMachineFunction.h"
19#include "MipsSEInstrInfo.h"
20#include "MipsSubtarget.h"
21#include "llvm/ADT/BitVector.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/ValueTypes.h"
28#include "llvm/DebugInfo.h"
29#include "llvm/IR/Constants.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Type.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/Target/TargetFrameLowering.h"
37#include "llvm/Target/TargetInstrInfo.h"
38#include "llvm/Target/TargetMachine.h"
39#include "llvm/Target/TargetOptions.h"
40
41using namespace llvm;
42
43MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
44  : MipsRegisterInfo(ST) {}
45
46bool MipsSERegisterInfo::
47requiresRegisterScavenging(const MachineFunction &MF) const {
48  return true;
49}
50
51bool MipsSERegisterInfo::
52requiresFrameIndexScavenging(const MachineFunction &MF) const {
53  return true;
54}
55
56const TargetRegisterClass *
57MipsSERegisterInfo::intRegClass(unsigned Size) const {
58  if (Size == 4)
59    return &Mips::GPR32RegClass;
60
61  assert(Size == 8);
62  return &Mips::GPR64RegClass;
63}
64
65void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
66                                     unsigned OpNo, int FrameIndex,
67                                     uint64_t StackSize,
68                                     int64_t SPOffset) const {
69  MachineInstr &MI = *II;
70  MachineFunction &MF = *MI.getParent()->getParent();
71  MachineFrameInfo *MFI = MF.getFrameInfo();
72  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
73
74  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
75  int MinCSFI = 0;
76  int MaxCSFI = -1;
77
78  if (CSI.size()) {
79    MinCSFI = CSI[0].getFrameIdx();
80    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
81  }
82
83  bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
84
85  // The following stack frame objects are always referenced relative to $sp:
86  //  1. Outgoing arguments.
87  //  2. Pointer to dynamically allocated stack space.
88  //  3. Locations for callee-saved registers.
89  //  4. Locations for eh data registers.
90  // Everything else is referenced relative to whatever register
91  // getFrameRegister() returns.
92  unsigned FrameReg;
93
94  if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
95    FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
96  else
97    FrameReg = getFrameRegister(MF);
98
99  // Calculate final offset.
100  // - There is no need to change the offset if the frame object is one of the
101  //   following: an outgoing argument, pointer to a dynamically allocated
102  //   stack space or a $gp restore location,
103  // - If the frame object is any of the following, its offset must be adjusted
104  //   by adding the size of the stack:
105  //   incoming argument, callee-saved register location or local variable.
106  bool IsKill = false;
107  int64_t Offset;
108
109  Offset = SPOffset + (int64_t)StackSize;
110  Offset += MI.getOperand(OpNo + 1).getImm();
111
112  DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
113
114  // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
115  // field.
116  if (!MI.isDebugValue()) {
117    if (!isInt<16>(Offset)) {
118      MachineBasicBlock &MBB = *MI.getParent();
119      DebugLoc DL = II->getDebugLoc();
120      unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
121      unsigned NewImm;
122      const MipsSEInstrInfo &TII =
123          *static_cast<const MipsSEInstrInfo *>(
124               MBB.getParent()->getTarget().getInstrInfo());
125      unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
126      BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
127        .addReg(Reg, RegState::Kill);
128
129      FrameReg = Reg;
130      Offset = SignExtend64<16>(NewImm);
131      IsKill = true;
132    }
133  }
134
135  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
136  MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
137}
138