MipsSubtarget.h revision 434c0bd2a5c3c7ebaa8ca10dd7e4fdb1f25e92a0 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSUBTARGET_H
15#define MIPSSUBTARGET_H
16
17#include "MCTargetDesc/MipsReginfo.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Target/TargetSubtargetInfo.h"
21
22#include <string>
23
24#define GET_SUBTARGETINFO_HEADER
25#include "MipsGenSubtargetInfo.inc"
26
27namespace llvm {
28class StringRef;
29
30class MipsTargetMachine;
31
32class MipsSubtarget : public MipsGenSubtargetInfo {
33  virtual void anchor();
34
35public:
36  // NOTE: O64 will not be supported.
37  enum MipsABIEnum {
38    UnknownABI, O32, N32, N64, EABI
39  };
40
41protected:
42
43  enum MipsArchEnum {
44    Mips32, Mips32r2, Mips64, Mips64r2
45  };
46
47  // Mips architecture version
48  MipsArchEnum MipsArchVersion;
49
50  // Mips supported ABIs
51  MipsABIEnum MipsABI;
52
53  // IsLittle - The target is Little Endian
54  bool IsLittle;
55
56  // IsSingleFloat - The target only supports single precision float
57  // point operations. This enable the target to use all 32 32-bit
58  // floating point registers instead of only using even ones.
59  bool IsSingleFloat;
60
61  // IsFP64bit - The target processor has 64-bit floating point registers.
62  bool IsFP64bit;
63
64  // IsFP64bit - General-purpose registers are 64 bits wide
65  bool IsGP64bit;
66
67  // HasVFPU - Processor has a vector floating point unit.
68  bool HasVFPU;
69
70  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
71  bool IsLinux;
72
73  // UseSmallSection - Small section is used.
74  bool UseSmallSection;
75
76  /// Features related to the presence of specific instructions.
77
78  // HasSEInReg - SEB and SEH (signext in register) instructions.
79  bool HasSEInReg;
80
81  // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
82  bool HasCondMov;
83
84  // HasSwap - Byte and half swap instructions.
85  bool HasSwap;
86
87  // HasBitCount - Count leading '1' and '0' bits.
88  bool HasBitCount;
89
90  // HasFPIdx -- Floating point indexed load/store instructions.
91  bool HasFPIdx;
92
93  // InMips16 -- can process Mips16 instructions
94  bool InMips16Mode;
95
96  // Mips16 hard float
97  bool InMips16HardFloat;
98
99  // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
100  bool PreviousInMips16Mode;
101
102  // InMicroMips -- can process MicroMips instructions
103  bool InMicroMipsMode;
104
105  // HasDSP, HasDSPR2 -- supports DSP ASE.
106  bool HasDSP, HasDSPR2;
107
108  // Allow mixed Mips16 and Mips32 in one source file
109  bool AllowMixed16_32;
110
111  // Optimize for space by compiling all functions as Mips 16 unless
112  // it needs floating point. Functions needing floating point are
113  // compiled as Mips32
114  bool Os16;
115
116  InstrItineraryData InstrItins;
117
118  // The instance to the register info section object
119  MipsReginfo MRI;
120
121  // Relocation Model
122  Reloc::Model RM;
123
124  // We can override the determination of whether we are in mips16 mode
125  // as from the command line
126  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
127
128  MipsTargetMachine *TM;
129
130public:
131  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
132                                     AntiDepBreakMode& Mode,
133                                     RegClassVector& CriticalPathRCs) const;
134
135  /// Only O32 and EABI supported right now.
136  bool isABI_EABI() const { return MipsABI == EABI; }
137  bool isABI_N64() const { return MipsABI == N64; }
138  bool isABI_N32() const { return MipsABI == N32; }
139  bool isABI_O32() const { return MipsABI == O32; }
140  unsigned getTargetABI() const { return MipsABI; }
141
142  /// This constructor initializes the data members to match that
143  /// of the specified triple.
144  MipsSubtarget(const std::string &TT, const std::string &CPU,
145                const std::string &FS, bool little, Reloc::Model RM,
146                MipsTargetMachine *TM);
147
148  /// ParseSubtargetFeatures - Parses features string setting specified
149  /// subtarget options.  Definition of function is auto generated by tblgen.
150  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
151
152  bool hasMips32() const { return MipsArchVersion >= Mips32; }
153  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
154                                   MipsArchVersion == Mips64r2; }
155  bool hasMips64() const { return MipsArchVersion >= Mips64; }
156  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
157
158  bool isLittle() const { return IsLittle; }
159  bool isFP64bit() const { return IsFP64bit; }
160  bool isGP64bit() const { return IsGP64bit; }
161  bool isGP32bit() const { return !IsGP64bit; }
162  bool isSingleFloat() const { return IsSingleFloat; }
163  bool isNotSingleFloat() const { return !IsSingleFloat; }
164  bool hasVFPU() const { return HasVFPU; }
165  bool inMips16Mode() const {
166    switch (OverrideMode) {
167    case NoOverride:
168      return InMips16Mode;
169    case Mips16Override:
170      return true;
171    case NoMips16Override:
172      return false;
173    }
174    llvm_unreachable("Unexpected mode");
175  }
176  bool inMips16ModeDefault() const {
177    return InMips16Mode;
178  }
179  bool inMips16HardFloat() const {
180    return inMips16Mode() && InMips16HardFloat;
181  }
182  bool inMicroMipsMode() const { return InMicroMipsMode; }
183  bool hasDSP() const { return HasDSP; }
184  bool hasDSPR2() const { return HasDSPR2; }
185  bool isLinux() const { return IsLinux; }
186  bool useSmallSection() const { return UseSmallSection; }
187
188  bool hasStandardEncoding() const { return !inMips16Mode(); }
189
190  /// Features related to the presence of specific instructions.
191  bool hasSEInReg()   const { return HasSEInReg; }
192  bool hasCondMov()   const { return HasCondMov; }
193  bool hasSwap()      const { return HasSwap; }
194  bool hasBitCount()  const { return HasBitCount; }
195  bool hasFPIdx()     const { return HasFPIdx; }
196
197  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
198  bool allowMixed16_32() const { return inMips16ModeDefault() |
199                                        AllowMixed16_32;}
200
201  bool os16() const { return Os16;};
202
203  // Grab MipsRegInfo object
204  const MipsReginfo &getMReginfo() const { return MRI; }
205
206  // Grab relocation model
207  Reloc::Model getRelocationModel() const {return RM;}
208
209  /// \brief Reset the subtarget for the Mips target.
210  void resetSubtarget(MachineFunction *MF);
211
212
213};
214} // End llvm namespace
215
216#endif
217