MipsSubtarget.h revision 74adad6de8cf947257a53bb08364fa0f4f71b10e
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the Mips specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef MIPSSUBTARGET_H 15#define MIPSSUBTARGET_H 16 17#include "MCTargetDesc/MipsReginfo.h" 18#include "llvm/MC/MCInstrItineraries.h" 19#include "llvm/Support/ErrorHandling.h" 20#include "llvm/Target/TargetSubtargetInfo.h" 21 22#include <string> 23 24#define GET_SUBTARGETINFO_HEADER 25#include "MipsGenSubtargetInfo.inc" 26 27namespace llvm { 28class StringRef; 29 30class MipsTargetMachine; 31 32class MipsSubtarget : public MipsGenSubtargetInfo { 33 virtual void anchor(); 34 35public: 36 // NOTE: O64 will not be supported. 37 enum MipsABIEnum { 38 UnknownABI, O32, N32, N64, EABI 39 }; 40 41protected: 42 43 enum MipsArchEnum { 44 Mips32, Mips32r2, Mips64, Mips64r2 45 }; 46 47 // Mips architecture version 48 MipsArchEnum MipsArchVersion; 49 50 // Mips supported ABIs 51 MipsABIEnum MipsABI; 52 53 // IsLittle - The target is Little Endian 54 bool IsLittle; 55 56 // IsSingleFloat - The target only supports single precision float 57 // point operations. This enable the target to use all 32 32-bit 58 // floating point registers instead of only using even ones. 59 bool IsSingleFloat; 60 61 // IsFP64bit - The target processor has 64-bit floating point registers. 62 bool IsFP64bit; 63 64 // IsFP64bit - General-purpose registers are 64 bits wide 65 bool IsGP64bit; 66 67 // HasVFPU - Processor has a vector floating point unit. 68 bool HasVFPU; 69 70 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 71 bool IsLinux; 72 73 // UseSmallSection - Small section is used. 74 bool UseSmallSection; 75 76 /// Features related to the presence of specific instructions. 77 78 // HasSEInReg - SEB and SEH (signext in register) instructions. 79 bool HasSEInReg; 80 81 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions. 82 bool HasCondMov; 83 84 // HasSwap - Byte and half swap instructions. 85 bool HasSwap; 86 87 // HasBitCount - Count leading '1' and '0' bits. 88 bool HasBitCount; 89 90 // HasFPIdx -- Floating point indexed load/store instructions. 91 bool HasFPIdx; 92 93 // InMips16 -- can process Mips16 instructions 94 bool InMips16Mode; 95 96 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode 97 bool PreviousInMips16Mode; 98 99 // InMicroMips -- can process MicroMips instructions 100 bool InMicroMipsMode; 101 102 // HasDSP, HasDSPR2 -- supports DSP ASE. 103 bool HasDSP, HasDSPR2; 104 105 // Allow mixed Mips16 and Mips32 in one source file 106 bool AllowMixed16_32; 107 108 // Optimize for space by compiling all functions as Mips 16 unless 109 // it needs floating point. Functions needing floating point are 110 // compiled as Mips32 111 bool Os16; 112 113 InstrItineraryData InstrItins; 114 115 // The instance to the register info section object 116 MipsReginfo MRI; 117 118 // Relocation Model 119 Reloc::Model RM; 120 121 // We can override the determination of whether we are in mips16 mode 122 // as from the command line 123 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 124 125 MipsTargetMachine *TM; 126 127public: 128 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 129 AntiDepBreakMode& Mode, 130 RegClassVector& CriticalPathRCs) const; 131 132 /// Only O32 and EABI supported right now. 133 bool isABI_EABI() const { return MipsABI == EABI; } 134 bool isABI_N64() const { return MipsABI == N64; } 135 bool isABI_N32() const { return MipsABI == N32; } 136 bool isABI_O32() const { return MipsABI == O32; } 137 unsigned getTargetABI() const { return MipsABI; } 138 139 /// This constructor initializes the data members to match that 140 /// of the specified triple. 141 MipsSubtarget(const std::string &TT, const std::string &CPU, 142 const std::string &FS, bool little, Reloc::Model RM, 143 MipsTargetMachine *TM); 144 145 /// ParseSubtargetFeatures - Parses features string setting specified 146 /// subtarget options. Definition of function is auto generated by tblgen. 147 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 148 149 bool hasMips32() const { return MipsArchVersion >= Mips32; } 150 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 || 151 MipsArchVersion == Mips64r2; } 152 bool hasMips64() const { return MipsArchVersion >= Mips64; } 153 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; } 154 155 bool isLittle() const { return IsLittle; } 156 bool isFP64bit() const { return IsFP64bit; } 157 bool isGP64bit() const { return IsGP64bit; } 158 bool isGP32bit() const { return !IsGP64bit; } 159 bool isSingleFloat() const { return IsSingleFloat; } 160 bool isNotSingleFloat() const { return !IsSingleFloat; } 161 bool hasVFPU() const { return HasVFPU; } 162 bool inMips16Mode() const { 163 switch (OverrideMode) { 164 case NoOverride: 165 return InMips16Mode; 166 case Mips16Override: 167 return true; 168 case NoMips16Override: 169 return false; 170 } 171 llvm_unreachable("Unexpected mode"); 172 } 173 bool inMips16ModeDefault() { 174 return InMips16Mode; 175 } 176 bool inMicroMipsMode() const { return InMicroMipsMode; } 177 bool hasDSP() const { return HasDSP; } 178 bool hasDSPR2() const { return HasDSPR2; } 179 bool isLinux() const { return IsLinux; } 180 bool useSmallSection() const { return UseSmallSection; } 181 182 bool hasStandardEncoding() const { return !inMips16Mode(); } 183 184 /// Features related to the presence of specific instructions. 185 bool hasSEInReg() const { return HasSEInReg; } 186 bool hasCondMov() const { return HasCondMov; } 187 bool hasSwap() const { return HasSwap; } 188 bool hasBitCount() const { return HasBitCount; } 189 bool hasFPIdx() const { return HasFPIdx; } 190 191 bool allowMixed16_32() const { return AllowMixed16_32;}; 192 193 bool os16() const { return Os16;}; 194 195 // Grab MipsRegInfo object 196 const MipsReginfo &getMReginfo() const { return MRI; } 197 198 // Grab relocation model 199 Reloc::Model getRelocationModel() const {return RM;} 200 201 /// \brief Reset the subtarget for the Mips target. 202 void resetSubtarget(MachineFunction *MF); 203 204 205}; 206} // End llvm namespace 207 208#endif 209