MipsSubtarget.h revision c673f9c6fecb0f828845ada7ea5458f66f896283 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSUBTARGET_H
15#define MIPSSUBTARGET_H
16
17#include "MCTargetDesc/MipsReginfo.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Target/TargetSubtargetInfo.h"
21
22#include <string>
23
24#define GET_SUBTARGETINFO_HEADER
25#include "MipsGenSubtargetInfo.inc"
26
27namespace llvm {
28class StringRef;
29
30class MipsTargetMachine;
31
32class MipsSubtarget : public MipsGenSubtargetInfo {
33  virtual void anchor();
34
35public:
36  // NOTE: O64 will not be supported.
37  enum MipsABIEnum {
38    UnknownABI, O32, N32, N64, EABI
39  };
40
41protected:
42
43  enum MipsArchEnum {
44    Mips32, Mips32r2, Mips64, Mips64r2
45  };
46
47  // Mips architecture version
48  MipsArchEnum MipsArchVersion;
49
50  // Mips supported ABIs
51  MipsABIEnum MipsABI;
52
53  // IsLittle - The target is Little Endian
54  bool IsLittle;
55
56  // IsSingleFloat - The target only supports single precision float
57  // point operations. This enable the target to use all 32 32-bit
58  // floating point registers instead of only using even ones.
59  bool IsSingleFloat;
60
61  // IsFP64bit - The target processor has 64-bit floating point registers.
62  bool IsFP64bit;
63
64  // IsFP64bit - General-purpose registers are 64 bits wide
65  bool IsGP64bit;
66
67  // HasVFPU - Processor has a vector floating point unit.
68  bool HasVFPU;
69
70  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
71  bool IsLinux;
72
73  // UseSmallSection - Small section is used.
74  bool UseSmallSection;
75
76  /// Features related to the presence of specific instructions.
77
78  // HasSEInReg - SEB and SEH (signext in register) instructions.
79  bool HasSEInReg;
80
81  // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
82  bool HasCondMov;
83
84  // HasSwap - Byte and half swap instructions.
85  bool HasSwap;
86
87  // HasBitCount - Count leading '1' and '0' bits.
88  bool HasBitCount;
89
90  // HasFPIdx -- Floating point indexed load/store instructions.
91  bool HasFPIdx;
92
93  // InMips16 -- can process Mips16 instructions
94  bool InMips16Mode;
95
96  // Mips16 hard float
97  bool InMips16HardFloat;
98
99  // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
100  bool PreviousInMips16Mode;
101
102  // InMicroMips -- can process MicroMips instructions
103  bool InMicroMipsMode;
104
105  // HasDSP, HasDSPR2 -- supports DSP ASE.
106  bool HasDSP, HasDSPR2;
107
108  // Allow mixed Mips16 and Mips32 in one source file
109  bool AllowMixed16_32;
110
111  // Optimize for space by compiling all functions as Mips 16 unless
112  // it needs floating point. Functions needing floating point are
113  // compiled as Mips32
114  bool Os16;
115
116  // HasMSA -- supports MSA ASE.
117  bool HasMSA;
118
119  InstrItineraryData InstrItins;
120
121  // The instance to the register info section object
122  MipsReginfo MRI;
123
124  // Relocation Model
125  Reloc::Model RM;
126
127  // We can override the determination of whether we are in mips16 mode
128  // as from the command line
129  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
130
131  MipsTargetMachine *TM;
132
133public:
134  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
135                                     AntiDepBreakMode& Mode,
136                                     RegClassVector& CriticalPathRCs) const;
137
138  /// Only O32 and EABI supported right now.
139  bool isABI_EABI() const { return MipsABI == EABI; }
140  bool isABI_N64() const { return MipsABI == N64; }
141  bool isABI_N32() const { return MipsABI == N32; }
142  bool isABI_O32() const { return MipsABI == O32; }
143  unsigned getTargetABI() const { return MipsABI; }
144
145  /// This constructor initializes the data members to match that
146  /// of the specified triple.
147  MipsSubtarget(const std::string &TT, const std::string &CPU,
148                const std::string &FS, bool little, Reloc::Model RM,
149                MipsTargetMachine *TM);
150
151  /// ParseSubtargetFeatures - Parses features string setting specified
152  /// subtarget options.  Definition of function is auto generated by tblgen.
153  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
154
155  bool hasMips32() const { return MipsArchVersion >= Mips32; }
156  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
157                                   MipsArchVersion == Mips64r2; }
158  bool hasMips64() const { return MipsArchVersion >= Mips64; }
159  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
160
161  bool isLittle() const { return IsLittle; }
162  bool isFP64bit() const { return IsFP64bit; }
163  bool isNotFP64bit() const { return !IsFP64bit; }
164  bool isGP64bit() const { return IsGP64bit; }
165  bool isGP32bit() const { return !IsGP64bit; }
166  bool isSingleFloat() const { return IsSingleFloat; }
167  bool isNotSingleFloat() const { return !IsSingleFloat; }
168  bool hasVFPU() const { return HasVFPU; }
169  bool inMips16Mode() const {
170    switch (OverrideMode) {
171    case NoOverride:
172      return InMips16Mode;
173    case Mips16Override:
174      return true;
175    case NoMips16Override:
176      return false;
177    }
178    llvm_unreachable("Unexpected mode");
179  }
180  bool inMips16ModeDefault() const {
181    return InMips16Mode;
182  }
183  bool inMips16HardFloat() const {
184    return inMips16Mode() && InMips16HardFloat;
185  }
186  bool inMicroMipsMode() const { return InMicroMipsMode; }
187  bool hasDSP() const { return HasDSP; }
188  bool hasDSPR2() const { return HasDSPR2; }
189  bool hasMSA() const { return HasMSA; }
190  bool isLinux() const { return IsLinux; }
191  bool useSmallSection() const { return UseSmallSection; }
192
193  bool hasStandardEncoding() const { return !inMips16Mode(); }
194
195  bool mipsSEUsesSoftFloat() const;
196
197  /// Features related to the presence of specific instructions.
198  bool hasSEInReg()   const { return HasSEInReg; }
199  bool hasCondMov()   const { return HasCondMov; }
200  bool hasSwap()      const { return HasSwap; }
201  bool hasBitCount()  const { return HasBitCount; }
202  bool hasFPIdx()     const { return HasFPIdx; }
203
204  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
205  bool allowMixed16_32() const { return inMips16ModeDefault() |
206                                        AllowMixed16_32;}
207
208  bool os16() const { return Os16;};
209
210  // Grab MipsRegInfo object
211  const MipsReginfo &getMReginfo() const { return MRI; }
212
213  // Grab relocation model
214  Reloc::Model getRelocationModel() const {return RM;}
215
216  /// \brief Reset the subtarget for the Mips target.
217  void resetSubtarget(MachineFunction *MF);
218
219
220};
221} // End llvm namespace
222
223#endif
224