MipsSubtarget.h revision dba14301f0098f9fc5c0d244bf334f55a6a21960 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSUBTARGET_H
15#define MIPSSUBTARGET_H
16
17#include "MCTargetDesc/MipsReginfo.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "MipsGenSubtargetInfo.inc"
24
25namespace llvm {
26class StringRef;
27
28class MipsSubtarget : public MipsGenSubtargetInfo {
29  virtual void anchor();
30
31public:
32  // NOTE: O64 will not be supported.
33  enum MipsABIEnum {
34    UnknownABI, O32, N32, N64, EABI
35  };
36
37protected:
38
39  enum MipsArchEnum {
40    Mips32, Mips32r2, Mips64, Mips64r2
41  };
42
43  // Mips architecture version
44  MipsArchEnum MipsArchVersion;
45
46  // Mips supported ABIs
47  MipsABIEnum MipsABI;
48
49  // IsLittle - The target is Little Endian
50  bool IsLittle;
51
52  // IsSingleFloat - The target only supports single precision float
53  // point operations. This enable the target to use all 32 32-bit
54  // floating point registers instead of only using even ones.
55  bool IsSingleFloat;
56
57  // IsFP64bit - The target processor has 64-bit floating point registers.
58  bool IsFP64bit;
59
60  // IsFP64bit - General-purpose registers are 64 bits wide
61  bool IsGP64bit;
62
63  // HasVFPU - Processor has a vector floating point unit.
64  bool HasVFPU;
65
66  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
67  bool IsLinux;
68
69  // UseSmallSection - Small section is used.
70  bool UseSmallSection;
71
72  /// Features related to the presence of specific instructions.
73
74  // HasSEInReg - SEB and SEH (signext in register) instructions.
75  bool HasSEInReg;
76
77  // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
78  bool HasCondMov;
79
80  // HasSwap - Byte and half swap instructions.
81  bool HasSwap;
82
83  // HasBitCount - Count leading '1' and '0' bits.
84  bool HasBitCount;
85
86  // HasFPIdx -- Floating point indexed load/store instructions.
87  bool HasFPIdx;
88
89  // InMips16 -- can process Mips16 instructions
90  bool InMips16Mode;
91
92  // HasDSP, HasDSPR2 -- supports DSP ASE.
93  bool HasDSP, HasDSPR2;
94
95  // IsAndroid -- target is android
96  bool IsAndroid;
97
98  InstrItineraryData InstrItins;
99
100  // The instance to the register info section object
101  MipsReginfo MRI;
102
103  // Relocation Model
104  Reloc::Model RM;
105
106public:
107  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
108                                     AntiDepBreakMode& Mode,
109                                     RegClassVector& CriticalPathRCs) const;
110
111  /// Only O32 and EABI supported right now.
112  bool isABI_EABI() const { return MipsABI == EABI; }
113  bool isABI_N64() const { return MipsABI == N64; }
114  bool isABI_N32() const { return MipsABI == N32; }
115  bool isABI_O32() const { return MipsABI == O32; }
116  unsigned getTargetABI() const { return MipsABI; }
117
118  /// This constructor initializes the data members to match that
119  /// of the specified triple.
120  MipsSubtarget(const std::string &TT, const std::string &CPU,
121                const std::string &FS, bool little, Reloc::Model RM);
122
123  /// ParseSubtargetFeatures - Parses features string setting specified
124  /// subtarget options.  Definition of function is auto generated by tblgen.
125  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
126
127  bool hasMips32() const { return MipsArchVersion >= Mips32; }
128  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
129                                   MipsArchVersion == Mips64r2; }
130  bool hasMips64() const { return MipsArchVersion >= Mips64; }
131  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
132
133  bool isLittle() const { return IsLittle; }
134  bool isFP64bit() const { return IsFP64bit; }
135  bool isGP64bit() const { return IsGP64bit; }
136  bool isGP32bit() const { return !IsGP64bit; }
137  bool isSingleFloat() const { return IsSingleFloat; }
138  bool isNotSingleFloat() const { return !IsSingleFloat; }
139  bool hasVFPU() const { return HasVFPU; }
140  bool inMips16Mode() const { return InMips16Mode; }
141  bool hasDSP() const { return HasDSP; }
142  bool hasDSPR2() const { return HasDSPR2; }
143  bool isAndroid() const { return IsAndroid; }
144  bool isLinux() const { return IsLinux; }
145  bool useSmallSection() const { return UseSmallSection; }
146
147  bool hasStandardEncoding() const { return !inMips16Mode(); }
148
149  /// Features related to the presence of specific instructions.
150  bool hasSEInReg()   const { return HasSEInReg; }
151  bool hasCondMov()   const { return HasCondMov; }
152  bool hasSwap()      const { return HasSwap; }
153  bool hasBitCount()  const { return HasBitCount; }
154  bool hasFPIdx()     const { return HasFPIdx; }
155
156  // Grab MipsRegInfo object
157  const MipsReginfo &getMReginfo() const { return MRI; }
158
159  // Grab relocation model
160  Reloc::Model getRelocationModel() const {return RM;}
161};
162} // End llvm namespace
163
164#endif
165