MipsSubtarget.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSSUBTARGET_H
15#define MIPSSUBTARGET_H
16
17#include "llvm/MC/MCInstrItineraries.h"
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "MipsGenSubtargetInfo.inc"
24
25namespace llvm {
26class StringRef;
27
28class MipsTargetMachine;
29
30class MipsSubtarget : public MipsGenSubtargetInfo {
31  virtual void anchor();
32
33public:
34  // NOTE: O64 will not be supported.
35  enum MipsABIEnum {
36    UnknownABI, O32, N32, N64, EABI
37  };
38
39protected:
40  enum MipsArchEnum {
41    Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
42    Mips64r2, Mips64r6
43  };
44
45  // Mips architecture version
46  MipsArchEnum MipsArchVersion;
47
48  // Mips supported ABIs
49  MipsABIEnum MipsABI;
50
51  // IsLittle - The target is Little Endian
52  bool IsLittle;
53
54  // IsSingleFloat - The target only supports single precision float
55  // point operations. This enable the target to use all 32 32-bit
56  // floating point registers instead of only using even ones.
57  bool IsSingleFloat;
58
59  // IsFP64bit - The target processor has 64-bit floating point registers.
60  bool IsFP64bit;
61
62  // IsNan2008 - IEEE 754-2008 NaN encoding.
63  bool IsNaN2008bit;
64
65  // IsFP64bit - General-purpose registers are 64 bits wide
66  bool IsGP64bit;
67
68  // HasVFPU - Processor has a vector floating point unit.
69  bool HasVFPU;
70
71  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
72  bool HasCnMips;
73
74  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
75  bool IsLinux;
76
77  // UseSmallSection - Small section is used.
78  bool UseSmallSection;
79
80  /// Features related to the presence of specific instructions.
81
82  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
83  bool HasMips3_32;
84
85  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
86  bool HasMips3_32r2;
87
88  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
89  bool HasMips4_32;
90
91  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
92  bool HasMips4_32r2;
93
94  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
95  bool HasMips5_32r2;
96
97  // InMips16 -- can process Mips16 instructions
98  bool InMips16Mode;
99
100  // Mips16 hard float
101  bool InMips16HardFloat;
102
103  // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
104  bool PreviousInMips16Mode;
105
106  // InMicroMips -- can process MicroMips instructions
107  bool InMicroMipsMode;
108
109  // HasDSP, HasDSPR2 -- supports DSP ASE.
110  bool HasDSP, HasDSPR2;
111
112  // Allow mixed Mips16 and Mips32 in one source file
113  bool AllowMixed16_32;
114
115  // Optimize for space by compiling all functions as Mips 16 unless
116  // it needs floating point. Functions needing floating point are
117  // compiled as Mips32
118  bool Os16;
119
120  // HasMSA -- supports MSA ASE.
121  bool HasMSA;
122
123  InstrItineraryData InstrItins;
124
125  // Relocation Model
126  Reloc::Model RM;
127
128  // We can override the determination of whether we are in mips16 mode
129  // as from the command line
130  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
131
132  MipsTargetMachine *TM;
133
134  Triple TargetTriple;
135public:
136  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
137                             AntiDepBreakMode& Mode,
138                             RegClassVector& CriticalPathRCs) const override;
139
140  /// Only O32 and EABI supported right now.
141  bool isABI_EABI() const { return MipsABI == EABI; }
142  bool isABI_N64() const { return MipsABI == N64; }
143  bool isABI_N32() const { return MipsABI == N32; }
144  bool isABI_O32() const { return MipsABI == O32; }
145  unsigned getTargetABI() const { return MipsABI; }
146
147  /// This constructor initializes the data members to match that
148  /// of the specified triple.
149  MipsSubtarget(const std::string &TT, const std::string &CPU,
150                const std::string &FS, bool little, Reloc::Model RM,
151                MipsTargetMachine *TM);
152
153  /// ParseSubtargetFeatures - Parses features string setting specified
154  /// subtarget options.  Definition of function is auto generated by tblgen.
155  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
156
157  bool hasMips2() const { return MipsArchVersion >= Mips2; }
158  bool hasMips3() const { return MipsArchVersion >= Mips3; }
159  bool hasMips4_32() const { return HasMips4_32; }
160  bool hasMips4_32r2() const { return HasMips4_32r2; }
161  bool hasMips32() const { return MipsArchVersion >= Mips32; }
162  bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
163                                   MipsArchVersion == Mips64r2; }
164  bool hasMips32r6() const { return MipsArchVersion == Mips32r6 ||
165                                   MipsArchVersion == Mips64r6; }
166  bool hasMips64() const { return MipsArchVersion >= Mips64; }
167  bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
168  bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
169
170  bool hasCnMips() const { return HasCnMips; }
171
172  bool isLittle() const { return IsLittle; }
173  bool isFP64bit() const { return IsFP64bit; }
174  bool isNaN2008() const { return IsNaN2008bit; }
175  bool isNotFP64bit() const { return !IsFP64bit; }
176  bool isGP64bit() const { return IsGP64bit; }
177  bool isGP32bit() const { return !IsGP64bit; }
178  bool isSingleFloat() const { return IsSingleFloat; }
179  bool isNotSingleFloat() const { return !IsSingleFloat; }
180  bool hasVFPU() const { return HasVFPU; }
181  bool inMips16Mode() const {
182    switch (OverrideMode) {
183    case NoOverride:
184      return InMips16Mode;
185    case Mips16Override:
186      return true;
187    case NoMips16Override:
188      return false;
189    }
190    llvm_unreachable("Unexpected mode");
191  }
192  bool inMips16ModeDefault() const {
193    return InMips16Mode;
194  }
195  bool inMips16HardFloat() const {
196    return inMips16Mode() && InMips16HardFloat;
197  }
198  bool inMicroMipsMode() const { return InMicroMipsMode; }
199  bool hasDSP() const { return HasDSP; }
200  bool hasDSPR2() const { return HasDSPR2; }
201  bool hasMSA() const { return HasMSA; }
202  bool isLinux() const { return IsLinux; }
203  bool useSmallSection() const { return UseSmallSection; }
204
205  bool hasStandardEncoding() const { return !inMips16Mode(); }
206
207  bool mipsSEUsesSoftFloat() const;
208
209  bool enableLongBranchPass() const {
210    return hasStandardEncoding() || allowMixed16_32();
211  }
212
213  /// Features related to the presence of specific instructions.
214  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
215
216  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
217  bool allowMixed16_32() const { return inMips16ModeDefault() |
218                                        AllowMixed16_32;}
219
220  bool os16() const { return Os16;};
221
222  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
223  bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
224
225  // for now constant islands are on for the whole compilation unit but we only
226  // really use them if in addition we are in mips16 mode
227  static bool useConstantIslands();
228
229  unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
230
231  // Grab relocation model
232  Reloc::Model getRelocationModel() const {return RM;}
233
234  /// \brief Reset the subtarget for the Mips target.
235  void resetSubtarget(MachineFunction *MF);
236
237  /// Does the system support unaligned memory access.
238  ///
239  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
240  /// specify which component of the system provides it. Hardware, software, and
241  /// hybrid implementations are all valid.
242  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
243};
244} // End llvm namespace
245
246#endif
247