MipsTargetMachine.cpp revision 0d91c0b519e0053931bf9502ebeaf44d397812f0 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Mips target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsTargetMachine.h"
15#include "Mips.h"
16#include "MipsFrameLowering.h"
17#include "MipsInstrInfo.h"
18#include "llvm/PassManager.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/Support/TargetRegistry.h"
21using namespace llvm;
22
23extern "C" void LLVMInitializeMipsTarget() {
24  // Register the target.
25  RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
26  RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
27  RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
28  RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
29}
30
31// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
32// The stack is always 8 byte aligned
33// On function prologue, the stack is created by decrementing
34// its pointer. Once decremented, all references are done with positive
35// offset from the stack/frame pointer, using StackGrowsUp enables
36// an easier handling.
37// Using CodeModel::Large enables different CALL behavior.
38MipsTargetMachine::
39MipsTargetMachine(const Target &T, StringRef TT,
40                  StringRef CPU, StringRef FS, const TargetOptions &Options,
41                  Reloc::Model RM, CodeModel::Model CM,
42                  CodeGenOpt::Level OL,
43                  bool isLittle)
44  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45    Subtarget(TT, CPU, FS, isLittle, RM),
46    DL(isLittle ?
47               (Subtarget.isABI_N64() ?
48                "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
49                "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
50               (Subtarget.isABI_N64() ?
51                "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
52                "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
53    InstrInfo(MipsInstrInfo::create(*this)),
54    FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
55    TLInfo(*this), TSInfo(*this), JITInfo(),
56    STTI(&TLInfo), VTTI(&TLInfo) {
57}
58
59void MipsebTargetMachine::anchor() { }
60
61MipsebTargetMachine::
62MipsebTargetMachine(const Target &T, StringRef TT,
63                    StringRef CPU, StringRef FS, const TargetOptions &Options,
64                    Reloc::Model RM, CodeModel::Model CM,
65                    CodeGenOpt::Level OL)
66  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
67
68void MipselTargetMachine::anchor() { }
69
70MipselTargetMachine::
71MipselTargetMachine(const Target &T, StringRef TT,
72                    StringRef CPU, StringRef FS, const TargetOptions &Options,
73                    Reloc::Model RM, CodeModel::Model CM,
74                    CodeGenOpt::Level OL)
75  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
76
77namespace {
78/// Mips Code Generator Pass Configuration Options.
79class MipsPassConfig : public TargetPassConfig {
80public:
81  MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
82    : TargetPassConfig(TM, PM) {}
83
84  MipsTargetMachine &getMipsTargetMachine() const {
85    return getTM<MipsTargetMachine>();
86  }
87
88  const MipsSubtarget &getMipsSubtarget() const {
89    return *getMipsTargetMachine().getSubtargetImpl();
90  }
91
92  virtual bool addInstSelector();
93  virtual bool addPreEmitPass();
94};
95} // namespace
96
97TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
98  return new MipsPassConfig(this, PM);
99}
100
101// Install an instruction selector pass using
102// the ISelDag to gen Mips code.
103bool MipsPassConfig::addInstSelector() {
104  addPass(createMipsISelDag(getMipsTargetMachine()));
105  return false;
106}
107
108// Implemented by targets that want to run passes immediately before
109// machine code is emitted. return true if -print-machineinstrs should
110// print out the code after the passes.
111bool MipsPassConfig::addPreEmitPass() {
112  MipsTargetMachine &TM = getMipsTargetMachine();
113  addPass(createMipsDelaySlotFillerPass(TM));
114
115  // NOTE: long branch has not been implemented for mips16.
116  if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
117    addPass(createMipsLongBranchPass(TM));
118
119  return true;
120}
121
122bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
123                                       JITCodeEmitter &JCE) {
124  // Machine code emitter pass for Mips.
125  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
126  return false;
127}
128