MipsTargetMachine.cpp revision 3f0ef85f44e6af948e3048b3368c7e81cf227a8f 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Mips target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsTargetMachine.h"
15#include "Mips.h"
16#include "MipsFrameLowering.h"
17#include "MipsInstrInfo.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/PassManager.h"
20#include "llvm/Support/TargetRegistry.h"
21using namespace llvm;
22
23extern "C" void LLVMInitializeMipsTarget() {
24  // Register the target.
25  RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
26  RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
27  RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
28  RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
29}
30
31// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
32// The stack is always 8 byte aligned
33// On function prologue, the stack is created by decrementing
34// its pointer. Once decremented, all references are done with positive
35// offset from the stack/frame pointer, using StackGrowsUp enables
36// an easier handling.
37// Using CodeModel::Large enables different CALL behavior.
38MipsTargetMachine::
39MipsTargetMachine(const Target &T, StringRef TT,
40                  StringRef CPU, StringRef FS, const TargetOptions &Options,
41                  Reloc::Model RM, CodeModel::Model CM,
42                  CodeGenOpt::Level OL,
43                  bool isLittle)
44  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45    Subtarget(TT, CPU, FS, isLittle, RM),
46    DL(isLittle ?
47               (Subtarget.isABI_N64() ?
48                "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
49                "n32:64-S128" :
50                "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64") :
51               (Subtarget.isABI_N64() ?
52                "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
53                "n32:64-S128" :
54                "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")),
55    InstrInfo(MipsInstrInfo::create(*this)),
56    FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
57    TLInfo(*this), TSInfo(*this), JITInfo(),
58    STTI(&TLInfo), VTTI(&TLInfo) {
59}
60
61void MipsebTargetMachine::anchor() { }
62
63MipsebTargetMachine::
64MipsebTargetMachine(const Target &T, StringRef TT,
65                    StringRef CPU, StringRef FS, const TargetOptions &Options,
66                    Reloc::Model RM, CodeModel::Model CM,
67                    CodeGenOpt::Level OL)
68  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
69
70void MipselTargetMachine::anchor() { }
71
72MipselTargetMachine::
73MipselTargetMachine(const Target &T, StringRef TT,
74                    StringRef CPU, StringRef FS, const TargetOptions &Options,
75                    Reloc::Model RM, CodeModel::Model CM,
76                    CodeGenOpt::Level OL)
77  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
78
79namespace {
80/// Mips Code Generator Pass Configuration Options.
81class MipsPassConfig : public TargetPassConfig {
82public:
83  MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
84    : TargetPassConfig(TM, PM) {}
85
86  MipsTargetMachine &getMipsTargetMachine() const {
87    return getTM<MipsTargetMachine>();
88  }
89
90  const MipsSubtarget &getMipsSubtarget() const {
91    return *getMipsTargetMachine().getSubtargetImpl();
92  }
93
94  virtual bool addInstSelector();
95  virtual bool addPreEmitPass();
96};
97} // namespace
98
99TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
100  return new MipsPassConfig(this, PM);
101}
102
103// Install an instruction selector pass using
104// the ISelDag to gen Mips code.
105bool MipsPassConfig::addInstSelector() {
106  addPass(createMipsISelDag(getMipsTargetMachine()));
107  return false;
108}
109
110// Implemented by targets that want to run passes immediately before
111// machine code is emitted. return true if -print-machineinstrs should
112// print out the code after the passes.
113bool MipsPassConfig::addPreEmitPass() {
114  MipsTargetMachine &TM = getMipsTargetMachine();
115  addPass(createMipsDelaySlotFillerPass(TM));
116
117  // NOTE: long branch has not been implemented for mips16.
118  if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
119    addPass(createMipsLongBranchPass(TM));
120
121  return true;
122}
123
124bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
125                                       JITCodeEmitter &JCE) {
126  // Machine code emitter pass for Mips.
127  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
128  return false;
129}
130