MipsTargetMachine.cpp revision a430cb613b6e93c05f128b04323c57acfd08686d 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Mips target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsTargetMachine.h"
15#include "Mips.h"
16#include "MipsFrameLowering.h"
17#include "MipsInstrInfo.h"
18#include "MipsModuleISelDAGToDAG.h"
19#include "MipsSEFrameLowering.h"
20#include "MipsSEInstrInfo.h"
21#include "MipsSEISelLowering.h"
22#include "MipsSEISelDAGToDAG.h"
23#include "Mips16FrameLowering.h"
24#include "Mips16InstrInfo.h"
25#include "Mips16ISelDAGToDAG.h"
26#include "Mips16ISelLowering.h"
27#include "llvm/Analysis/TargetTransformInfo.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/PassManager.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/raw_ostream.h"
32#include "llvm/Support/TargetRegistry.h"
33using namespace llvm;
34
35
36
37extern "C" void LLVMInitializeMipsTarget() {
38  // Register the target.
39  RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
40  RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
41  RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
42  RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
43}
44
45// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
46// The stack is always 8 byte aligned
47// On function prologue, the stack is created by decrementing
48// its pointer. Once decremented, all references are done with positive
49// offset from the stack/frame pointer, using StackGrowsUp enables
50// an easier handling.
51// Using CodeModel::Large enables different CALL behavior.
52MipsTargetMachine::
53MipsTargetMachine(const Target &T, StringRef TT,
54                  StringRef CPU, StringRef FS, const TargetOptions &Options,
55                  Reloc::Model RM, CodeModel::Model CM,
56                  CodeGenOpt::Level OL,
57                  bool isLittle)
58  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59    Subtarget(TT, CPU, FS, isLittle, RM, this),
60    DL(isLittle ?
61               (Subtarget.isABI_N64() ?
62                "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
63                "n32:64-S128" :
64                "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64") :
65               (Subtarget.isABI_N64() ?
66                "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-"
67                "n32:64-S128" :
68                "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")),
69    InstrInfo(MipsInstrInfo::create(*this)),
70    FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
71    TLInfo(MipsTargetLowering::create(*this)),
72    TSInfo(*this), JITInfo() {
73}
74
75
76void MipsTargetMachine::setHelperClassesMips16() {
77  InstrInfoSE.swap(InstrInfo);
78  FrameLoweringSE.swap(FrameLowering);
79  TLInfoSE.swap(TLInfo);
80  if (!InstrInfo16) {
81    InstrInfo.reset(MipsInstrInfo::create(*this));
82    FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
83    TLInfo.reset(MipsTargetLowering::create(*this));
84  } else {
85    InstrInfo16.swap(InstrInfo);
86    FrameLowering16.swap(FrameLowering);
87    TLInfo16.swap(TLInfo);
88  }
89  assert(TLInfo && "null target lowering 16");
90  assert(InstrInfo && "null instr info 16");
91  assert(FrameLowering && "null frame lowering 16");
92}
93
94void MipsTargetMachine::setHelperClassesMipsSE() {
95  InstrInfo16.swap(InstrInfo);
96  FrameLowering16.swap(FrameLowering);
97  TLInfo16.swap(TLInfo);
98  if (!InstrInfoSE) {
99    InstrInfo.reset(MipsInstrInfo::create(*this));
100    FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
101    TLInfo.reset(MipsTargetLowering::create(*this));
102  } else {
103    InstrInfoSE.swap(InstrInfo);
104    FrameLoweringSE.swap(FrameLowering);
105    TLInfoSE.swap(TLInfo);
106  }
107  assert(TLInfo && "null target lowering in SE");
108  assert(InstrInfo && "null instr info SE");
109  assert(FrameLowering && "null frame lowering SE");
110}
111void MipsebTargetMachine::anchor() { }
112
113MipsebTargetMachine::
114MipsebTargetMachine(const Target &T, StringRef TT,
115                    StringRef CPU, StringRef FS, const TargetOptions &Options,
116                    Reloc::Model RM, CodeModel::Model CM,
117                    CodeGenOpt::Level OL)
118  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
119
120void MipselTargetMachine::anchor() { }
121
122MipselTargetMachine::
123MipselTargetMachine(const Target &T, StringRef TT,
124                    StringRef CPU, StringRef FS, const TargetOptions &Options,
125                    Reloc::Model RM, CodeModel::Model CM,
126                    CodeGenOpt::Level OL)
127  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
128
129namespace {
130/// Mips Code Generator Pass Configuration Options.
131class MipsPassConfig : public TargetPassConfig {
132public:
133  MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
134    : TargetPassConfig(TM, PM) {}
135
136  MipsTargetMachine &getMipsTargetMachine() const {
137    return getTM<MipsTargetMachine>();
138  }
139
140  const MipsSubtarget &getMipsSubtarget() const {
141    return *getMipsTargetMachine().getSubtargetImpl();
142  }
143
144  virtual bool addInstSelector();
145  virtual bool addPreEmitPass();
146};
147} // namespace
148
149TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
150  return new MipsPassConfig(this, PM);
151}
152
153// Install an instruction selector pass using
154// the ISelDag to gen Mips code.
155bool MipsPassConfig::addInstSelector() {
156  if (getMipsSubtarget().allowMixed16_32()) {
157    addPass(createMipsModuleISelDag(getMipsTargetMachine()));
158    addPass(createMips16ISelDag(getMipsTargetMachine()));
159    addPass(createMipsSEISelDag(getMipsTargetMachine()));
160  } else {
161    addPass(createMipsISelDag(getMipsTargetMachine()));
162  }
163  return false;
164}
165
166void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
167  if (Subtarget.allowMixed16_32()) {
168    DEBUG(errs() << "No ");
169    //FIXME: The Basic Target Transform Info
170    // pass needs to become a function pass instead of
171    // being an immutable pass and then this method as it exists now
172    // would be unnecessary.
173    PM.add(createNoTargetTransformInfoPass());
174  } else
175    LLVMTargetMachine::addAnalysisPasses(PM);
176  DEBUG(errs() << "Target Transform Info Pass Added\n");
177}
178
179// Implemented by targets that want to run passes immediately before
180// machine code is emitted. return true if -print-machineinstrs should
181// print out the code after the passes.
182bool MipsPassConfig::addPreEmitPass() {
183  MipsTargetMachine &TM = getMipsTargetMachine();
184  const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
185  addPass(createMipsDelaySlotFillerPass(TM));
186
187  if (Subtarget.hasStandardEncoding() ||
188      Subtarget.allowMixed16_32())
189    addPass(createMipsLongBranchPass(TM));
190  if (Subtarget.inMips16Mode() ||
191      Subtarget.allowMixed16_32())
192    addPass(createMipsConstantIslandPass(TM));
193
194  return true;
195}
196
197bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
198                                       JITCodeEmitter &JCE) {
199  // Machine code emitter pass for Mips.
200  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
201  return false;
202}
203