MipsTargetMachine.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Mips target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsTargetMachine.h"
15#include "Mips.h"
16#include "Mips16FrameLowering.h"
17#include "Mips16HardFloat.h"
18#include "Mips16ISelDAGToDAG.h"
19#include "Mips16ISelLowering.h"
20#include "Mips16InstrInfo.h"
21#include "MipsFrameLowering.h"
22#include "MipsInstrInfo.h"
23#include "MipsModuleISelDAGToDAG.h"
24#include "MipsOs16.h"
25#include "MipsSEFrameLowering.h"
26#include "MipsSEISelDAGToDAG.h"
27#include "MipsSEISelLowering.h"
28#include "MipsSEInstrInfo.h"
29#include "llvm/Analysis/TargetTransformInfo.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/PassManager.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/TargetRegistry.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Transforms/Scalar.h"
36using namespace llvm;
37
38#define DEBUG_TYPE "mips"
39
40extern "C" void LLVMInitializeMipsTarget() {
41  // Register the target.
42  RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43  RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44  RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45  RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
46}
47
48static std::string computeDataLayout(const MipsSubtarget &ST) {
49  std::string Ret = "";
50
51  // There are both little and big endian mips.
52  if (ST.isLittle())
53    Ret += "e";
54  else
55    Ret += "E";
56
57  Ret += "-m:m";
58
59  // Pointers are 32 bit on some ABIs.
60  if (!ST.isABI_N64())
61    Ret += "-p:32:32";
62
63  // 8 and 16 bit integers only need no have natural alignment, but try to
64  // align them to 32 bits. 64 bit integers have natural alignment.
65  Ret += "-i8:8:32-i16:16:32-i64:64";
66
67  // 32 bit registers are always available and the stack is at least 64 bit
68  // aligned. On N64 64 bit registers are also available and the stack is
69  // 128 bit aligned.
70  if (ST.isABI_N64() || ST.isABI_N32())
71    Ret += "-n32:64-S128";
72  else
73    Ret += "-n32-S64";
74
75  return Ret;
76}
77
78// On function prologue, the stack is created by decrementing
79// its pointer. Once decremented, all references are done with positive
80// offset from the stack/frame pointer, using StackGrowsUp enables
81// an easier handling.
82// Using CodeModel::Large enables different CALL behavior.
83MipsTargetMachine::
84MipsTargetMachine(const Target &T, StringRef TT,
85                  StringRef CPU, StringRef FS, const TargetOptions &Options,
86                  Reloc::Model RM, CodeModel::Model CM,
87                  CodeGenOpt::Level OL,
88                  bool isLittle)
89  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
90    Subtarget(TT, CPU, FS, isLittle, RM, this),
91    DL(computeDataLayout(Subtarget)),
92    InstrInfo(MipsInstrInfo::create(*this)),
93    FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
94    TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
95    InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
96  initAsmInfo();
97}
98
99
100void MipsTargetMachine::setHelperClassesMips16() {
101  InstrInfoSE.swap(InstrInfo);
102  FrameLoweringSE.swap(FrameLowering);
103  TLInfoSE.swap(TLInfo);
104  if (!InstrInfo16) {
105    InstrInfo.reset(MipsInstrInfo::create(*this));
106    FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
107    TLInfo.reset(MipsTargetLowering::create(*this));
108  } else {
109    InstrInfo16.swap(InstrInfo);
110    FrameLowering16.swap(FrameLowering);
111    TLInfo16.swap(TLInfo);
112  }
113  assert(TLInfo && "null target lowering 16");
114  assert(InstrInfo && "null instr info 16");
115  assert(FrameLowering && "null frame lowering 16");
116}
117
118void MipsTargetMachine::setHelperClassesMipsSE() {
119  InstrInfo16.swap(InstrInfo);
120  FrameLowering16.swap(FrameLowering);
121  TLInfo16.swap(TLInfo);
122  if (!InstrInfoSE) {
123    InstrInfo.reset(MipsInstrInfo::create(*this));
124    FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
125    TLInfo.reset(MipsTargetLowering::create(*this));
126  } else {
127    InstrInfoSE.swap(InstrInfo);
128    FrameLoweringSE.swap(FrameLowering);
129    TLInfoSE.swap(TLInfo);
130  }
131  assert(TLInfo && "null target lowering in SE");
132  assert(InstrInfo && "null instr info SE");
133  assert(FrameLowering && "null frame lowering SE");
134}
135void MipsebTargetMachine::anchor() { }
136
137MipsebTargetMachine::
138MipsebTargetMachine(const Target &T, StringRef TT,
139                    StringRef CPU, StringRef FS, const TargetOptions &Options,
140                    Reloc::Model RM, CodeModel::Model CM,
141                    CodeGenOpt::Level OL)
142  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
143
144void MipselTargetMachine::anchor() { }
145
146MipselTargetMachine::
147MipselTargetMachine(const Target &T, StringRef TT,
148                    StringRef CPU, StringRef FS, const TargetOptions &Options,
149                    Reloc::Model RM, CodeModel::Model CM,
150                    CodeGenOpt::Level OL)
151  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
152
153namespace {
154/// Mips Code Generator Pass Configuration Options.
155class MipsPassConfig : public TargetPassConfig {
156public:
157  MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
158    : TargetPassConfig(TM, PM) {
159    // The current implementation of long branch pass requires a scratch
160    // register ($at) to be available before branch instructions. Tail merging
161    // can break this requirement, so disable it when long branch pass is
162    // enabled.
163    EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
164  }
165
166  MipsTargetMachine &getMipsTargetMachine() const {
167    return getTM<MipsTargetMachine>();
168  }
169
170  const MipsSubtarget &getMipsSubtarget() const {
171    return *getMipsTargetMachine().getSubtargetImpl();
172  }
173
174  void addIRPasses() override;
175  bool addInstSelector() override;
176  void addMachineSSAOptimization() override;
177  bool addPreEmitPass() override;
178
179  bool addPreRegAlloc() override;
180
181};
182} // namespace
183
184TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
185  return new MipsPassConfig(this, PM);
186}
187
188void MipsPassConfig::addIRPasses() {
189  TargetPassConfig::addIRPasses();
190  if (getMipsSubtarget().os16())
191    addPass(createMipsOs16(getMipsTargetMachine()));
192  if (getMipsSubtarget().inMips16HardFloat())
193    addPass(createMips16HardFloat(getMipsTargetMachine()));
194  addPass(createPartiallyInlineLibCallsPass());
195}
196// Install an instruction selector pass using
197// the ISelDag to gen Mips code.
198bool MipsPassConfig::addInstSelector() {
199  if (getMipsSubtarget().allowMixed16_32()) {
200    addPass(createMipsModuleISelDag(getMipsTargetMachine()));
201    addPass(createMips16ISelDag(getMipsTargetMachine()));
202    addPass(createMipsSEISelDag(getMipsTargetMachine()));
203  } else {
204    addPass(createMipsISelDag(getMipsTargetMachine()));
205  }
206  return false;
207}
208
209void MipsPassConfig::addMachineSSAOptimization() {
210  addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
211  TargetPassConfig::addMachineSSAOptimization();
212}
213
214bool MipsPassConfig::addPreRegAlloc() {
215  if (getOptLevel() == CodeGenOpt::None) {
216    addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
217    return true;
218  }
219  else
220    return false;
221}
222
223void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
224  if (Subtarget.allowMixed16_32()) {
225    DEBUG(errs() << "No ");
226    //FIXME: The Basic Target Transform Info
227    // pass needs to become a function pass instead of
228    // being an immutable pass and then this method as it exists now
229    // would be unnecessary.
230    PM.add(createNoTargetTransformInfoPass());
231  } else
232    LLVMTargetMachine::addAnalysisPasses(PM);
233  DEBUG(errs() << "Target Transform Info Pass Added\n");
234}
235
236// Implemented by targets that want to run passes immediately before
237// machine code is emitted. return true if -print-machineinstrs should
238// print out the code after the passes.
239bool MipsPassConfig::addPreEmitPass() {
240  MipsTargetMachine &TM = getMipsTargetMachine();
241  const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
242  addPass(createMipsDelaySlotFillerPass(TM));
243
244  if (Subtarget.enableLongBranchPass())
245    addPass(createMipsLongBranchPass(TM));
246  if (Subtarget.inMips16Mode() ||
247      Subtarget.allowMixed16_32())
248    addPass(createMipsConstantIslandPass(TM));
249
250  return true;
251}
252
253bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
254                                       JITCodeEmitter &JCE) {
255  // Machine code emitter pass for Mips.
256  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
257  return false;
258}
259