NVPTXInstrInfo.h revision 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 
1//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the niversity of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the NVPTX implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef NVPTXINSTRUCTIONINFO_H
15#define NVPTXINSTRUCTIONINFO_H
16
17#include "NVPTX.h"
18#include "NVPTXRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "NVPTXGenInstrInfo.inc"
23
24namespace llvm {
25
26class NVPTXInstrInfo : public NVPTXGenInstrInfo {
27  NVPTXTargetMachine &TM;
28  const NVPTXRegisterInfo RegInfo;
29  virtual void anchor();
30public:
31  explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
32
33  virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
34
35  /* The following virtual functions are used in register allocation.
36   * They are not implemented because the existing interface and the logic
37   * at the caller side do not work for the elementized vector load and store.
38   *
39   * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40   *                                  int &FrameIndex) const;
41   * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42   *                                 int &FrameIndex) const;
43   * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
44   *                              MachineBasicBlock::iterator MBBI,
45   *                             unsigned SrcReg, bool isKill, int FrameIndex,
46   *                              const TargetRegisterClass *RC) const;
47   * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
48   *                               MachineBasicBlock::iterator MBBI,
49   *                               unsigned DestReg, int FrameIndex,
50   *                               const TargetRegisterClass *RC) const;
51   */
52
53  virtual void copyPhysReg(
54      MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
55      unsigned DestReg, unsigned SrcReg, bool KillSrc) const;
56  virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
57                           unsigned &DestReg) const;
58  bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
59  bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
60  bool isReadSpecialReg(MachineInstr &MI) const;
61
62  virtual bool CanTailMerge(const MachineInstr *MI) const;
63  // Branch analysis.
64  virtual bool AnalyzeBranch(
65      MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
66      SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
67  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
68  virtual unsigned InsertBranch(
69      MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
70      const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
71  unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
72    return MI.getOperand(2).getImm();
73  }
74
75};
76
77} // namespace llvm
78
79#endif
80