PPCAsmParser.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/PPCMCTargetDesc.h"
11#include "MCTargetDesc/PPCMCExpr.h"
12#include "PPCTargetStreamer.h"
13#include "llvm/ADT/STLExtras.h"
14#include "llvm/ADT/SmallString.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCParser/MCAsmLexer.h"
22#include "llvm/MC/MCParser/MCAsmParser.h"
23#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCTargetAsmParser.h"
28#include "llvm/Support/SourceMgr.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31
32using namespace llvm;
33
34namespace {
35
36static unsigned RRegs[32] = {
37  PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44  PPC::R28, PPC::R29, PPC::R30, PPC::R31
45};
46static unsigned RRegsNoR0[32] = {
47  PPC::ZERO,
48            PPC::R1,  PPC::R2,  PPC::R3,
49  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55  PPC::R28, PPC::R29, PPC::R30, PPC::R31
56};
57static unsigned XRegs[32] = {
58  PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65  PPC::X28, PPC::X29, PPC::X30, PPC::X31
66};
67static unsigned XRegsNoX0[32] = {
68  PPC::ZERO8,
69            PPC::X1,  PPC::X2,  PPC::X3,
70  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76  PPC::X28, PPC::X29, PPC::X30, PPC::X31
77};
78static unsigned FRegs[32] = {
79  PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80  PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81  PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86  PPC::F28, PPC::F29, PPC::F30, PPC::F31
87};
88static unsigned VRegs[32] = {
89  PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90  PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91  PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96  PPC::V28, PPC::V29, PPC::V30, PPC::V31
97};
98static unsigned VSRegs[64] = {
99  PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100  PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101  PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107
108  PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109  PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110  PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111  PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112  PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113  PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114  PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115  PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116};
117static unsigned VSFRegs[64] = {
118  PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119  PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120  PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126
127  PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128  PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129  PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135};
136static unsigned CRBITRegs[32] = {
137  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
138  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
139  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
140  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
141  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
142  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
143  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
144  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
145};
146static unsigned CRRegs[8] = {
147  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
148  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
149};
150
151// Evaluate an expression containing condition register
152// or condition register field symbols.  Returns positive
153// value on success, or -1 on error.
154static int64_t
155EvaluateCRExpr(const MCExpr *E) {
156  switch (E->getKind()) {
157  case MCExpr::Target:
158    return -1;
159
160  case MCExpr::Constant: {
161    int64_t Res = cast<MCConstantExpr>(E)->getValue();
162    return Res < 0 ? -1 : Res;
163  }
164
165  case MCExpr::SymbolRef: {
166    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
167    StringRef Name = SRE->getSymbol().getName();
168
169    if (Name == "lt") return 0;
170    if (Name == "gt") return 1;
171    if (Name == "eq") return 2;
172    if (Name == "so") return 3;
173    if (Name == "un") return 3;
174
175    if (Name == "cr0") return 0;
176    if (Name == "cr1") return 1;
177    if (Name == "cr2") return 2;
178    if (Name == "cr3") return 3;
179    if (Name == "cr4") return 4;
180    if (Name == "cr5") return 5;
181    if (Name == "cr6") return 6;
182    if (Name == "cr7") return 7;
183
184    return -1;
185  }
186
187  case MCExpr::Unary:
188    return -1;
189
190  case MCExpr::Binary: {
191    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
192    int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
193    int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
194    int64_t Res;
195
196    if (LHSVal < 0 || RHSVal < 0)
197      return -1;
198
199    switch (BE->getOpcode()) {
200    default: return -1;
201    case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
202    case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
203    }
204
205    return Res < 0 ? -1 : Res;
206  }
207  }
208
209  llvm_unreachable("Invalid expression kind!");
210}
211
212struct PPCOperand;
213
214class PPCAsmParser : public MCTargetAsmParser {
215  MCSubtargetInfo &STI;
216  MCAsmParser &Parser;
217  const MCInstrInfo &MII;
218  bool IsPPC64;
219  bool IsDarwin;
220
221  MCAsmParser &getParser() const { return Parser; }
222  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
223
224  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
225  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
226
227  bool isPPC64() const { return IsPPC64; }
228  bool isDarwin() const { return IsDarwin; }
229
230  bool MatchRegisterName(const AsmToken &Tok,
231                         unsigned &RegNo, int64_t &IntVal);
232
233  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
234
235  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
236                                        PPCMCExpr::VariantKind &Variant);
237  const MCExpr *FixupVariantKind(const MCExpr *E);
238  bool ParseExpression(const MCExpr *&EVal);
239  bool ParseDarwinExpression(const MCExpr *&EVal);
240
241  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
242
243  bool ParseDirectiveWord(unsigned Size, SMLoc L);
244  bool ParseDirectiveTC(unsigned Size, SMLoc L);
245  bool ParseDirectiveMachine(SMLoc L);
246  bool ParseDarwinDirectiveMachine(SMLoc L);
247
248  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
249                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
250                               MCStreamer &Out, unsigned &ErrorInfo,
251                               bool MatchingInlineAsm);
252
253  void ProcessInstruction(MCInst &Inst,
254                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
255
256  /// @name Auto-generated Match Functions
257  /// {
258
259#define GET_ASSEMBLER_HEADER
260#include "PPCGenAsmMatcher.inc"
261
262  /// }
263
264
265public:
266  PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
267               const MCInstrInfo &_MII)
268      : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
269    // Check for 64-bit vs. 32-bit pointer mode.
270    Triple TheTriple(STI.getTargetTriple());
271    IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
272               TheTriple.getArch() == Triple::ppc64le);
273    IsDarwin = TheTriple.isMacOSX();
274    // Initialize the set of available features.
275    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276  }
277
278  virtual bool ParseInstruction(ParseInstructionInfo &Info,
279                                StringRef Name, SMLoc NameLoc,
280                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
281
282  virtual bool ParseDirective(AsmToken DirectiveID);
283
284  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
285
286  virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
287                                            MCSymbolRefExpr::VariantKind,
288                                            MCContext &Ctx);
289};
290
291/// PPCOperand - Instances of this class represent a parsed PowerPC machine
292/// instruction.
293struct PPCOperand : public MCParsedAsmOperand {
294  enum KindTy {
295    Token,
296    Immediate,
297    Expression,
298    TLSRegister
299  } Kind;
300
301  SMLoc StartLoc, EndLoc;
302  bool IsPPC64;
303
304  struct TokOp {
305    const char *Data;
306    unsigned Length;
307  };
308
309  struct ImmOp {
310    int64_t Val;
311  };
312
313  struct ExprOp {
314    const MCExpr *Val;
315    int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
316  };
317
318  struct TLSRegOp {
319    const MCSymbolRefExpr *Sym;
320  };
321
322  union {
323    struct TokOp Tok;
324    struct ImmOp Imm;
325    struct ExprOp Expr;
326    struct TLSRegOp TLSReg;
327  };
328
329  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
330public:
331  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
332    Kind = o.Kind;
333    StartLoc = o.StartLoc;
334    EndLoc = o.EndLoc;
335    IsPPC64 = o.IsPPC64;
336    switch (Kind) {
337    case Token:
338      Tok = o.Tok;
339      break;
340    case Immediate:
341      Imm = o.Imm;
342      break;
343    case Expression:
344      Expr = o.Expr;
345      break;
346    case TLSRegister:
347      TLSReg = o.TLSReg;
348      break;
349    }
350  }
351
352  /// getStartLoc - Get the location of the first token of this operand.
353  SMLoc getStartLoc() const { return StartLoc; }
354
355  /// getEndLoc - Get the location of the last token of this operand.
356  SMLoc getEndLoc() const { return EndLoc; }
357
358  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
359  bool isPPC64() const { return IsPPC64; }
360
361  int64_t getImm() const {
362    assert(Kind == Immediate && "Invalid access!");
363    return Imm.Val;
364  }
365
366  const MCExpr *getExpr() const {
367    assert(Kind == Expression && "Invalid access!");
368    return Expr.Val;
369  }
370
371  int64_t getExprCRVal() const {
372    assert(Kind == Expression && "Invalid access!");
373    return Expr.CRVal;
374  }
375
376  const MCExpr *getTLSReg() const {
377    assert(Kind == TLSRegister && "Invalid access!");
378    return TLSReg.Sym;
379  }
380
381  unsigned getReg() const {
382    assert(isRegNumber() && "Invalid access!");
383    return (unsigned) Imm.Val;
384  }
385
386  unsigned getVSReg() const {
387    assert(isVSRegNumber() && "Invalid access!");
388    return (unsigned) Imm.Val;
389  }
390
391  unsigned getCCReg() const {
392    assert(isCCRegNumber() && "Invalid access!");
393    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
394  }
395
396  unsigned getCRBit() const {
397    assert(isCRBitNumber() && "Invalid access!");
398    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
399  }
400
401  unsigned getCRBitMask() const {
402    assert(isCRBitMask() && "Invalid access!");
403    return 7 - countTrailingZeros<uint64_t>(Imm.Val);
404  }
405
406  bool isToken() const { return Kind == Token; }
407  bool isImm() const { return Kind == Immediate || Kind == Expression; }
408  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
409  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
410  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
411  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
412  bool isU16Imm() const { return Kind == Expression ||
413                                 (Kind == Immediate && isUInt<16>(getImm())); }
414  bool isS16Imm() const { return Kind == Expression ||
415                                 (Kind == Immediate && isInt<16>(getImm())); }
416  bool isS16ImmX4() const { return Kind == Expression ||
417                                   (Kind == Immediate && isInt<16>(getImm()) &&
418                                    (getImm() & 3) == 0); }
419  bool isS17Imm() const { return Kind == Expression ||
420                                 (Kind == Immediate && isInt<17>(getImm())); }
421  bool isTLSReg() const { return Kind == TLSRegister; }
422  bool isDirectBr() const { return Kind == Expression ||
423                                   (Kind == Immediate && isInt<26>(getImm()) &&
424                                    (getImm() & 3) == 0); }
425  bool isCondBr() const { return Kind == Expression ||
426                                 (Kind == Immediate && isInt<16>(getImm()) &&
427                                  (getImm() & 3) == 0); }
428  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
429  bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
430  bool isCCRegNumber() const { return (Kind == Expression
431                                       && isUInt<3>(getExprCRVal())) ||
432                                      (Kind == Immediate
433                                       && isUInt<3>(getImm())); }
434  bool isCRBitNumber() const { return (Kind == Expression
435                                       && isUInt<5>(getExprCRVal())) ||
436                                      (Kind == Immediate
437                                       && isUInt<5>(getImm())); }
438  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
439                                    isPowerOf2_32(getImm()); }
440  bool isMem() const { return false; }
441  bool isReg() const { return false; }
442
443  void addRegOperands(MCInst &Inst, unsigned N) const {
444    llvm_unreachable("addRegOperands");
445  }
446
447  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
448    assert(N == 1 && "Invalid number of operands!");
449    Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
450  }
451
452  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
453    assert(N == 1 && "Invalid number of operands!");
454    Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
455  }
456
457  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
458    assert(N == 1 && "Invalid number of operands!");
459    Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
460  }
461
462  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
463    assert(N == 1 && "Invalid number of operands!");
464    Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
465  }
466
467  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
468    if (isPPC64())
469      addRegG8RCOperands(Inst, N);
470    else
471      addRegGPRCOperands(Inst, N);
472  }
473
474  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
475    if (isPPC64())
476      addRegG8RCNoX0Operands(Inst, N);
477    else
478      addRegGPRCNoR0Operands(Inst, N);
479  }
480
481  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
482    assert(N == 1 && "Invalid number of operands!");
483    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
484  }
485
486  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
487    assert(N == 1 && "Invalid number of operands!");
488    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
489  }
490
491  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
492    assert(N == 1 && "Invalid number of operands!");
493    Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
494  }
495
496  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
497    assert(N == 1 && "Invalid number of operands!");
498    Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
499  }
500
501  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
502    assert(N == 1 && "Invalid number of operands!");
503    Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
504  }
505
506  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
507    assert(N == 1 && "Invalid number of operands!");
508    Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
509  }
510
511  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
512    assert(N == 1 && "Invalid number of operands!");
513    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
514  }
515
516  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
517    assert(N == 1 && "Invalid number of operands!");
518    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
519  }
520
521  void addImmOperands(MCInst &Inst, unsigned N) const {
522    assert(N == 1 && "Invalid number of operands!");
523    if (Kind == Immediate)
524      Inst.addOperand(MCOperand::CreateImm(getImm()));
525    else
526      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
527  }
528
529  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
530    assert(N == 1 && "Invalid number of operands!");
531    if (Kind == Immediate)
532      Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
533    else
534      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
535  }
536
537  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
538    assert(N == 1 && "Invalid number of operands!");
539    Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
540  }
541
542  StringRef getToken() const {
543    assert(Kind == Token && "Invalid access!");
544    return StringRef(Tok.Data, Tok.Length);
545  }
546
547  virtual void print(raw_ostream &OS) const;
548
549  static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
550    PPCOperand *Op = new PPCOperand(Token);
551    Op->Tok.Data = Str.data();
552    Op->Tok.Length = Str.size();
553    Op->StartLoc = S;
554    Op->EndLoc = S;
555    Op->IsPPC64 = IsPPC64;
556    return Op;
557  }
558
559  static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
560                                               bool IsPPC64) {
561    // Allocate extra memory for the string and copy it.
562    void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
563    PPCOperand *Op = new (Mem) PPCOperand(Token);
564    Op->Tok.Data = (const char *)(Op + 1);
565    Op->Tok.Length = Str.size();
566    std::memcpy((char *)(Op + 1), Str.data(), Str.size());
567    Op->StartLoc = S;
568    Op->EndLoc = S;
569    Op->IsPPC64 = IsPPC64;
570    return Op;
571  }
572
573  static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
574    PPCOperand *Op = new PPCOperand(Immediate);
575    Op->Imm.Val = Val;
576    Op->StartLoc = S;
577    Op->EndLoc = E;
578    Op->IsPPC64 = IsPPC64;
579    return Op;
580  }
581
582  static PPCOperand *CreateExpr(const MCExpr *Val,
583                                SMLoc S, SMLoc E, bool IsPPC64) {
584    PPCOperand *Op = new PPCOperand(Expression);
585    Op->Expr.Val = Val;
586    Op->Expr.CRVal = EvaluateCRExpr(Val);
587    Op->StartLoc = S;
588    Op->EndLoc = E;
589    Op->IsPPC64 = IsPPC64;
590    return Op;
591  }
592
593  static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
594                                  SMLoc S, SMLoc E, bool IsPPC64) {
595    PPCOperand *Op = new PPCOperand(TLSRegister);
596    Op->TLSReg.Sym = Sym;
597    Op->StartLoc = S;
598    Op->EndLoc = E;
599    Op->IsPPC64 = IsPPC64;
600    return Op;
601  }
602
603  static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
604                                      SMLoc S, SMLoc E, bool IsPPC64) {
605    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
606      return CreateImm(CE->getValue(), S, E, IsPPC64);
607
608    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
609      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
610        return CreateTLSReg(SRE, S, E, IsPPC64);
611
612    return CreateExpr(Val, S, E, IsPPC64);
613  }
614};
615
616} // end anonymous namespace.
617
618void PPCOperand::print(raw_ostream &OS) const {
619  switch (Kind) {
620  case Token:
621    OS << "'" << getToken() << "'";
622    break;
623  case Immediate:
624    OS << getImm();
625    break;
626  case Expression:
627    getExpr()->print(OS);
628    break;
629  case TLSRegister:
630    getTLSReg()->print(OS);
631    break;
632  }
633}
634
635
636void PPCAsmParser::
637ProcessInstruction(MCInst &Inst,
638                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
639  int Opcode = Inst.getOpcode();
640  switch (Opcode) {
641  case PPC::LAx: {
642    MCInst TmpInst;
643    TmpInst.setOpcode(PPC::LA);
644    TmpInst.addOperand(Inst.getOperand(0));
645    TmpInst.addOperand(Inst.getOperand(2));
646    TmpInst.addOperand(Inst.getOperand(1));
647    Inst = TmpInst;
648    break;
649  }
650  case PPC::SUBI: {
651    MCInst TmpInst;
652    int64_t N = Inst.getOperand(2).getImm();
653    TmpInst.setOpcode(PPC::ADDI);
654    TmpInst.addOperand(Inst.getOperand(0));
655    TmpInst.addOperand(Inst.getOperand(1));
656    TmpInst.addOperand(MCOperand::CreateImm(-N));
657    Inst = TmpInst;
658    break;
659  }
660  case PPC::SUBIS: {
661    MCInst TmpInst;
662    int64_t N = Inst.getOperand(2).getImm();
663    TmpInst.setOpcode(PPC::ADDIS);
664    TmpInst.addOperand(Inst.getOperand(0));
665    TmpInst.addOperand(Inst.getOperand(1));
666    TmpInst.addOperand(MCOperand::CreateImm(-N));
667    Inst = TmpInst;
668    break;
669  }
670  case PPC::SUBIC: {
671    MCInst TmpInst;
672    int64_t N = Inst.getOperand(2).getImm();
673    TmpInst.setOpcode(PPC::ADDIC);
674    TmpInst.addOperand(Inst.getOperand(0));
675    TmpInst.addOperand(Inst.getOperand(1));
676    TmpInst.addOperand(MCOperand::CreateImm(-N));
677    Inst = TmpInst;
678    break;
679  }
680  case PPC::SUBICo: {
681    MCInst TmpInst;
682    int64_t N = Inst.getOperand(2).getImm();
683    TmpInst.setOpcode(PPC::ADDICo);
684    TmpInst.addOperand(Inst.getOperand(0));
685    TmpInst.addOperand(Inst.getOperand(1));
686    TmpInst.addOperand(MCOperand::CreateImm(-N));
687    Inst = TmpInst;
688    break;
689  }
690  case PPC::EXTLWI:
691  case PPC::EXTLWIo: {
692    MCInst TmpInst;
693    int64_t N = Inst.getOperand(2).getImm();
694    int64_t B = Inst.getOperand(3).getImm();
695    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
696    TmpInst.addOperand(Inst.getOperand(0));
697    TmpInst.addOperand(Inst.getOperand(1));
698    TmpInst.addOperand(MCOperand::CreateImm(B));
699    TmpInst.addOperand(MCOperand::CreateImm(0));
700    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
701    Inst = TmpInst;
702    break;
703  }
704  case PPC::EXTRWI:
705  case PPC::EXTRWIo: {
706    MCInst TmpInst;
707    int64_t N = Inst.getOperand(2).getImm();
708    int64_t B = Inst.getOperand(3).getImm();
709    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
710    TmpInst.addOperand(Inst.getOperand(0));
711    TmpInst.addOperand(Inst.getOperand(1));
712    TmpInst.addOperand(MCOperand::CreateImm(B + N));
713    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
714    TmpInst.addOperand(MCOperand::CreateImm(31));
715    Inst = TmpInst;
716    break;
717  }
718  case PPC::INSLWI:
719  case PPC::INSLWIo: {
720    MCInst TmpInst;
721    int64_t N = Inst.getOperand(2).getImm();
722    int64_t B = Inst.getOperand(3).getImm();
723    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
724    TmpInst.addOperand(Inst.getOperand(0));
725    TmpInst.addOperand(Inst.getOperand(0));
726    TmpInst.addOperand(Inst.getOperand(1));
727    TmpInst.addOperand(MCOperand::CreateImm(32 - B));
728    TmpInst.addOperand(MCOperand::CreateImm(B));
729    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
730    Inst = TmpInst;
731    break;
732  }
733  case PPC::INSRWI:
734  case PPC::INSRWIo: {
735    MCInst TmpInst;
736    int64_t N = Inst.getOperand(2).getImm();
737    int64_t B = Inst.getOperand(3).getImm();
738    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
739    TmpInst.addOperand(Inst.getOperand(0));
740    TmpInst.addOperand(Inst.getOperand(0));
741    TmpInst.addOperand(Inst.getOperand(1));
742    TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
743    TmpInst.addOperand(MCOperand::CreateImm(B));
744    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
745    Inst = TmpInst;
746    break;
747  }
748  case PPC::ROTRWI:
749  case PPC::ROTRWIo: {
750    MCInst TmpInst;
751    int64_t N = Inst.getOperand(2).getImm();
752    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
753    TmpInst.addOperand(Inst.getOperand(0));
754    TmpInst.addOperand(Inst.getOperand(1));
755    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
756    TmpInst.addOperand(MCOperand::CreateImm(0));
757    TmpInst.addOperand(MCOperand::CreateImm(31));
758    Inst = TmpInst;
759    break;
760  }
761  case PPC::SLWI:
762  case PPC::SLWIo: {
763    MCInst TmpInst;
764    int64_t N = Inst.getOperand(2).getImm();
765    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
766    TmpInst.addOperand(Inst.getOperand(0));
767    TmpInst.addOperand(Inst.getOperand(1));
768    TmpInst.addOperand(MCOperand::CreateImm(N));
769    TmpInst.addOperand(MCOperand::CreateImm(0));
770    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
771    Inst = TmpInst;
772    break;
773  }
774  case PPC::SRWI:
775  case PPC::SRWIo: {
776    MCInst TmpInst;
777    int64_t N = Inst.getOperand(2).getImm();
778    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
779    TmpInst.addOperand(Inst.getOperand(0));
780    TmpInst.addOperand(Inst.getOperand(1));
781    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
782    TmpInst.addOperand(MCOperand::CreateImm(N));
783    TmpInst.addOperand(MCOperand::CreateImm(31));
784    Inst = TmpInst;
785    break;
786  }
787  case PPC::CLRRWI:
788  case PPC::CLRRWIo: {
789    MCInst TmpInst;
790    int64_t N = Inst.getOperand(2).getImm();
791    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
792    TmpInst.addOperand(Inst.getOperand(0));
793    TmpInst.addOperand(Inst.getOperand(1));
794    TmpInst.addOperand(MCOperand::CreateImm(0));
795    TmpInst.addOperand(MCOperand::CreateImm(0));
796    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
797    Inst = TmpInst;
798    break;
799  }
800  case PPC::CLRLSLWI:
801  case PPC::CLRLSLWIo: {
802    MCInst TmpInst;
803    int64_t B = Inst.getOperand(2).getImm();
804    int64_t N = Inst.getOperand(3).getImm();
805    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
806    TmpInst.addOperand(Inst.getOperand(0));
807    TmpInst.addOperand(Inst.getOperand(1));
808    TmpInst.addOperand(MCOperand::CreateImm(N));
809    TmpInst.addOperand(MCOperand::CreateImm(B - N));
810    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
811    Inst = TmpInst;
812    break;
813  }
814  case PPC::EXTLDI:
815  case PPC::EXTLDIo: {
816    MCInst TmpInst;
817    int64_t N = Inst.getOperand(2).getImm();
818    int64_t B = Inst.getOperand(3).getImm();
819    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
820    TmpInst.addOperand(Inst.getOperand(0));
821    TmpInst.addOperand(Inst.getOperand(1));
822    TmpInst.addOperand(MCOperand::CreateImm(B));
823    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
824    Inst = TmpInst;
825    break;
826  }
827  case PPC::EXTRDI:
828  case PPC::EXTRDIo: {
829    MCInst TmpInst;
830    int64_t N = Inst.getOperand(2).getImm();
831    int64_t B = Inst.getOperand(3).getImm();
832    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
833    TmpInst.addOperand(Inst.getOperand(0));
834    TmpInst.addOperand(Inst.getOperand(1));
835    TmpInst.addOperand(MCOperand::CreateImm(B + N));
836    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
837    Inst = TmpInst;
838    break;
839  }
840  case PPC::INSRDI:
841  case PPC::INSRDIo: {
842    MCInst TmpInst;
843    int64_t N = Inst.getOperand(2).getImm();
844    int64_t B = Inst.getOperand(3).getImm();
845    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
846    TmpInst.addOperand(Inst.getOperand(0));
847    TmpInst.addOperand(Inst.getOperand(0));
848    TmpInst.addOperand(Inst.getOperand(1));
849    TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
850    TmpInst.addOperand(MCOperand::CreateImm(B));
851    Inst = TmpInst;
852    break;
853  }
854  case PPC::ROTRDI:
855  case PPC::ROTRDIo: {
856    MCInst TmpInst;
857    int64_t N = Inst.getOperand(2).getImm();
858    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
859    TmpInst.addOperand(Inst.getOperand(0));
860    TmpInst.addOperand(Inst.getOperand(1));
861    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
862    TmpInst.addOperand(MCOperand::CreateImm(0));
863    Inst = TmpInst;
864    break;
865  }
866  case PPC::SLDI:
867  case PPC::SLDIo: {
868    MCInst TmpInst;
869    int64_t N = Inst.getOperand(2).getImm();
870    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
871    TmpInst.addOperand(Inst.getOperand(0));
872    TmpInst.addOperand(Inst.getOperand(1));
873    TmpInst.addOperand(MCOperand::CreateImm(N));
874    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
875    Inst = TmpInst;
876    break;
877  }
878  case PPC::SRDI:
879  case PPC::SRDIo: {
880    MCInst TmpInst;
881    int64_t N = Inst.getOperand(2).getImm();
882    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
883    TmpInst.addOperand(Inst.getOperand(0));
884    TmpInst.addOperand(Inst.getOperand(1));
885    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
886    TmpInst.addOperand(MCOperand::CreateImm(N));
887    Inst = TmpInst;
888    break;
889  }
890  case PPC::CLRRDI:
891  case PPC::CLRRDIo: {
892    MCInst TmpInst;
893    int64_t N = Inst.getOperand(2).getImm();
894    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
895    TmpInst.addOperand(Inst.getOperand(0));
896    TmpInst.addOperand(Inst.getOperand(1));
897    TmpInst.addOperand(MCOperand::CreateImm(0));
898    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
899    Inst = TmpInst;
900    break;
901  }
902  case PPC::CLRLSLDI:
903  case PPC::CLRLSLDIo: {
904    MCInst TmpInst;
905    int64_t B = Inst.getOperand(2).getImm();
906    int64_t N = Inst.getOperand(3).getImm();
907    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
908    TmpInst.addOperand(Inst.getOperand(0));
909    TmpInst.addOperand(Inst.getOperand(1));
910    TmpInst.addOperand(MCOperand::CreateImm(N));
911    TmpInst.addOperand(MCOperand::CreateImm(B - N));
912    Inst = TmpInst;
913    break;
914  }
915  }
916}
917
918bool PPCAsmParser::
919MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
920                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
921                        MCStreamer &Out, unsigned &ErrorInfo,
922                        bool MatchingInlineAsm) {
923  MCInst Inst;
924
925  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
926  default: break;
927  case Match_Success:
928    // Post-process instructions (typically extended mnemonics)
929    ProcessInstruction(Inst, Operands);
930    Inst.setLoc(IDLoc);
931    Out.EmitInstruction(Inst, STI);
932    return false;
933  case Match_MissingFeature:
934    return Error(IDLoc, "instruction use requires an option to be enabled");
935  case Match_MnemonicFail:
936      return Error(IDLoc, "unrecognized instruction mnemonic");
937  case Match_InvalidOperand: {
938    SMLoc ErrorLoc = IDLoc;
939    if (ErrorInfo != ~0U) {
940      if (ErrorInfo >= Operands.size())
941        return Error(IDLoc, "too few operands for instruction");
942
943      ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
944      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
945    }
946
947    return Error(ErrorLoc, "invalid operand for instruction");
948  }
949  }
950
951  llvm_unreachable("Implement any new match types added!");
952}
953
954bool PPCAsmParser::
955MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
956  if (Tok.is(AsmToken::Identifier)) {
957    StringRef Name = Tok.getString();
958
959    if (Name.equals_lower("lr")) {
960      RegNo = isPPC64()? PPC::LR8 : PPC::LR;
961      IntVal = 8;
962      return false;
963    } else if (Name.equals_lower("ctr")) {
964      RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
965      IntVal = 9;
966      return false;
967    } else if (Name.equals_lower("vrsave")) {
968      RegNo = PPC::VRSAVE;
969      IntVal = 256;
970      return false;
971    } else if (Name.startswith_lower("r") &&
972               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
973      RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
974      return false;
975    } else if (Name.startswith_lower("f") &&
976               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
977      RegNo = FRegs[IntVal];
978      return false;
979    } else if (Name.startswith_lower("v") &&
980               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
981      RegNo = VRegs[IntVal];
982      return false;
983    } else if (Name.startswith_lower("cr") &&
984               !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
985      RegNo = CRRegs[IntVal];
986      return false;
987    }
988  }
989
990  return true;
991}
992
993bool PPCAsmParser::
994ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
995  const AsmToken &Tok = Parser.getTok();
996  StartLoc = Tok.getLoc();
997  EndLoc = Tok.getEndLoc();
998  RegNo = 0;
999  int64_t IntVal;
1000
1001  if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1002    Parser.Lex(); // Eat identifier token.
1003    return false;
1004  }
1005
1006  return Error(StartLoc, "invalid register name");
1007}
1008
1009/// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1010/// the expression and check for VK_PPC_LO/HI/HA
1011/// symbol variants.  If all symbols with modifier use the same
1012/// variant, return the corresponding PPCMCExpr::VariantKind,
1013/// and a modified expression using the default symbol variant.
1014/// Otherwise, return NULL.
1015const MCExpr *PPCAsmParser::
1016ExtractModifierFromExpr(const MCExpr *E,
1017                        PPCMCExpr::VariantKind &Variant) {
1018  MCContext &Context = getParser().getContext();
1019  Variant = PPCMCExpr::VK_PPC_None;
1020
1021  switch (E->getKind()) {
1022  case MCExpr::Target:
1023  case MCExpr::Constant:
1024    return 0;
1025
1026  case MCExpr::SymbolRef: {
1027    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1028
1029    switch (SRE->getKind()) {
1030    case MCSymbolRefExpr::VK_PPC_LO:
1031      Variant = PPCMCExpr::VK_PPC_LO;
1032      break;
1033    case MCSymbolRefExpr::VK_PPC_HI:
1034      Variant = PPCMCExpr::VK_PPC_HI;
1035      break;
1036    case MCSymbolRefExpr::VK_PPC_HA:
1037      Variant = PPCMCExpr::VK_PPC_HA;
1038      break;
1039    case MCSymbolRefExpr::VK_PPC_HIGHER:
1040      Variant = PPCMCExpr::VK_PPC_HIGHER;
1041      break;
1042    case MCSymbolRefExpr::VK_PPC_HIGHERA:
1043      Variant = PPCMCExpr::VK_PPC_HIGHERA;
1044      break;
1045    case MCSymbolRefExpr::VK_PPC_HIGHEST:
1046      Variant = PPCMCExpr::VK_PPC_HIGHEST;
1047      break;
1048    case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1049      Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1050      break;
1051    default:
1052      return 0;
1053    }
1054
1055    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1056  }
1057
1058  case MCExpr::Unary: {
1059    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1060    const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1061    if (!Sub)
1062      return 0;
1063    return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1064  }
1065
1066  case MCExpr::Binary: {
1067    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1068    PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1069    const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1070    const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1071
1072    if (!LHS && !RHS)
1073      return 0;
1074
1075    if (!LHS) LHS = BE->getLHS();
1076    if (!RHS) RHS = BE->getRHS();
1077
1078    if (LHSVariant == PPCMCExpr::VK_PPC_None)
1079      Variant = RHSVariant;
1080    else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1081      Variant = LHSVariant;
1082    else if (LHSVariant == RHSVariant)
1083      Variant = LHSVariant;
1084    else
1085      return 0;
1086
1087    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1088  }
1089  }
1090
1091  llvm_unreachable("Invalid expression kind!");
1092}
1093
1094/// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1095/// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1096/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1097/// FIXME: This is a hack.
1098const MCExpr *PPCAsmParser::
1099FixupVariantKind(const MCExpr *E) {
1100  MCContext &Context = getParser().getContext();
1101
1102  switch (E->getKind()) {
1103  case MCExpr::Target:
1104  case MCExpr::Constant:
1105    return E;
1106
1107  case MCExpr::SymbolRef: {
1108    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1109    MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1110
1111    switch (SRE->getKind()) {
1112    case MCSymbolRefExpr::VK_TLSGD:
1113      Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1114      break;
1115    case MCSymbolRefExpr::VK_TLSLD:
1116      Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1117      break;
1118    default:
1119      return E;
1120    }
1121    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1122  }
1123
1124  case MCExpr::Unary: {
1125    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1126    const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1127    if (Sub == UE->getSubExpr())
1128      return E;
1129    return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1130  }
1131
1132  case MCExpr::Binary: {
1133    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1134    const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1135    const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1136    if (LHS == BE->getLHS() && RHS == BE->getRHS())
1137      return E;
1138    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1139  }
1140  }
1141
1142  llvm_unreachable("Invalid expression kind!");
1143}
1144
1145/// ParseExpression.  This differs from the default "parseExpression" in that
1146/// it handles modifiers.
1147bool PPCAsmParser::
1148ParseExpression(const MCExpr *&EVal) {
1149
1150  if (isDarwin())
1151    return ParseDarwinExpression(EVal);
1152
1153  // (ELF Platforms)
1154  // Handle \code @l/@ha \endcode
1155  if (getParser().parseExpression(EVal))
1156    return true;
1157
1158  EVal = FixupVariantKind(EVal);
1159
1160  PPCMCExpr::VariantKind Variant;
1161  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1162  if (E)
1163    EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1164
1165  return false;
1166}
1167
1168/// ParseDarwinExpression.  (MachO Platforms)
1169/// This differs from the default "parseExpression" in that it handles detection
1170/// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1171/// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1172/// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1173/// for this to be done at a higher level.
1174bool PPCAsmParser::
1175ParseDarwinExpression(const MCExpr *&EVal) {
1176  PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1177  switch (getLexer().getKind()) {
1178  default:
1179    break;
1180  case AsmToken::Identifier:
1181    // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1182    // something starting with any other char should be part of the
1183    // asm syntax.  If handwritten asm includes an identifier like lo16,
1184    // then all bets are off - but no-one would do that, right?
1185    StringRef poss = Parser.getTok().getString();
1186    if (poss.equals_lower("lo16")) {
1187      Variant = PPCMCExpr::VK_PPC_LO;
1188    } else if (poss.equals_lower("hi16")) {
1189      Variant = PPCMCExpr::VK_PPC_HI;
1190    } else if (poss.equals_lower("ha16")) {
1191      Variant = PPCMCExpr::VK_PPC_HA;
1192    }
1193    if (Variant != PPCMCExpr::VK_PPC_None) {
1194      Parser.Lex(); // Eat the xx16
1195      if (getLexer().isNot(AsmToken::LParen))
1196        return Error(Parser.getTok().getLoc(), "expected '('");
1197      Parser.Lex(); // Eat the '('
1198    }
1199    break;
1200  }
1201
1202  if (getParser().parseExpression(EVal))
1203    return true;
1204
1205  if (Variant != PPCMCExpr::VK_PPC_None) {
1206    if (getLexer().isNot(AsmToken::RParen))
1207      return Error(Parser.getTok().getLoc(), "expected ')'");
1208    Parser.Lex(); // Eat the ')'
1209    EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1210  }
1211  return false;
1212}
1213
1214/// ParseOperand
1215/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1216/// rNN for MachO.
1217bool PPCAsmParser::
1218ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1219  SMLoc S = Parser.getTok().getLoc();
1220  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1221  const MCExpr *EVal;
1222  PPCOperand *Op;
1223
1224  // Attempt to parse the next token as an immediate
1225  switch (getLexer().getKind()) {
1226  // Special handling for register names.  These are interpreted
1227  // as immediates corresponding to the register number.
1228  case AsmToken::Percent:
1229    Parser.Lex(); // Eat the '%'.
1230    unsigned RegNo;
1231    int64_t IntVal;
1232    if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1233      Parser.Lex(); // Eat the identifier token.
1234      Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1235      Operands.push_back(Op);
1236      return false;
1237    }
1238    return Error(S, "invalid register name");
1239
1240  case AsmToken::Identifier:
1241    // Note that non-register-name identifiers from the compiler will begin
1242    // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1243    // identifiers like r31foo - so we fall through in the event that parsing
1244    // a register name fails.
1245    if (isDarwin()) {
1246      unsigned RegNo;
1247      int64_t IntVal;
1248      if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1249        Parser.Lex(); // Eat the identifier token.
1250        Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1251        Operands.push_back(Op);
1252        return false;
1253      }
1254    }
1255  // Fall-through to process non-register-name identifiers as expression.
1256  // All other expressions
1257  case AsmToken::LParen:
1258  case AsmToken::Plus:
1259  case AsmToken::Minus:
1260  case AsmToken::Integer:
1261  case AsmToken::Dot:
1262  case AsmToken::Dollar:
1263  case AsmToken::Exclaim:
1264  case AsmToken::Tilde:
1265    if (!ParseExpression(EVal))
1266      break;
1267    /* fall through */
1268  default:
1269    return Error(S, "unknown operand");
1270  }
1271
1272  // Push the parsed operand into the list of operands
1273  Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1274  Operands.push_back(Op);
1275
1276  // Check whether this is a TLS call expression
1277  bool TLSCall = false;
1278  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1279    TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1280
1281  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1282    const MCExpr *TLSSym;
1283
1284    Parser.Lex(); // Eat the '('.
1285    S = Parser.getTok().getLoc();
1286    if (ParseExpression(TLSSym))
1287      return Error(S, "invalid TLS call expression");
1288    if (getLexer().isNot(AsmToken::RParen))
1289      return Error(Parser.getTok().getLoc(), "missing ')'");
1290    E = Parser.getTok().getLoc();
1291    Parser.Lex(); // Eat the ')'.
1292
1293    Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1294    Operands.push_back(Op);
1295  }
1296
1297  // Otherwise, check for D-form memory operands
1298  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1299    Parser.Lex(); // Eat the '('.
1300    S = Parser.getTok().getLoc();
1301
1302    int64_t IntVal;
1303    switch (getLexer().getKind()) {
1304    case AsmToken::Percent:
1305      Parser.Lex(); // Eat the '%'.
1306      unsigned RegNo;
1307      if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1308        return Error(S, "invalid register name");
1309      Parser.Lex(); // Eat the identifier token.
1310      break;
1311
1312    case AsmToken::Integer:
1313      if (!isDarwin()) {
1314        if (getParser().parseAbsoluteExpression(IntVal) ||
1315          IntVal < 0 || IntVal > 31)
1316        return Error(S, "invalid register number");
1317      } else {
1318        return Error(S, "unexpected integer value");
1319      }
1320      break;
1321
1322   case AsmToken::Identifier:
1323    if (isDarwin()) {
1324      unsigned RegNo;
1325      if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1326        Parser.Lex(); // Eat the identifier token.
1327        break;
1328      }
1329    }
1330    // Fall-through..
1331
1332    default:
1333      return Error(S, "invalid memory operand");
1334    }
1335
1336    if (getLexer().isNot(AsmToken::RParen))
1337      return Error(Parser.getTok().getLoc(), "missing ')'");
1338    E = Parser.getTok().getLoc();
1339    Parser.Lex(); // Eat the ')'.
1340
1341    Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1342    Operands.push_back(Op);
1343  }
1344
1345  return false;
1346}
1347
1348/// Parse an instruction mnemonic followed by its operands.
1349bool PPCAsmParser::
1350ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1351                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1352  // The first operand is the token for the instruction name.
1353  // If the next character is a '+' or '-', we need to add it to the
1354  // instruction name, to match what TableGen is doing.
1355  std::string NewOpcode;
1356  if (getLexer().is(AsmToken::Plus)) {
1357    getLexer().Lex();
1358    NewOpcode = Name;
1359    NewOpcode += '+';
1360    Name = NewOpcode;
1361  }
1362  if (getLexer().is(AsmToken::Minus)) {
1363    getLexer().Lex();
1364    NewOpcode = Name;
1365    NewOpcode += '-';
1366    Name = NewOpcode;
1367  }
1368  // If the instruction ends in a '.', we need to create a separate
1369  // token for it, to match what TableGen is doing.
1370  size_t Dot = Name.find('.');
1371  StringRef Mnemonic = Name.slice(0, Dot);
1372  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1373    Operands.push_back(
1374        PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1375  else
1376    Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1377  if (Dot != StringRef::npos) {
1378    SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1379    StringRef DotStr = Name.slice(Dot, StringRef::npos);
1380    if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1381      Operands.push_back(
1382          PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1383    else
1384      Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1385  }
1386
1387  // If there are no more operands then finish
1388  if (getLexer().is(AsmToken::EndOfStatement))
1389    return false;
1390
1391  // Parse the first operand
1392  if (ParseOperand(Operands))
1393    return true;
1394
1395  while (getLexer().isNot(AsmToken::EndOfStatement) &&
1396         getLexer().is(AsmToken::Comma)) {
1397    // Consume the comma token
1398    getLexer().Lex();
1399
1400    // Parse the next operand
1401    if (ParseOperand(Operands))
1402      return true;
1403  }
1404
1405  return false;
1406}
1407
1408/// ParseDirective parses the PPC specific directives
1409bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1410  StringRef IDVal = DirectiveID.getIdentifier();
1411  if (!isDarwin()) {
1412    if (IDVal == ".word")
1413      return ParseDirectiveWord(2, DirectiveID.getLoc());
1414    if (IDVal == ".llong")
1415      return ParseDirectiveWord(8, DirectiveID.getLoc());
1416    if (IDVal == ".tc")
1417      return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1418    if (IDVal == ".machine")
1419      return ParseDirectiveMachine(DirectiveID.getLoc());
1420  } else {
1421    if (IDVal == ".machine")
1422      return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1423  }
1424  return true;
1425}
1426
1427/// ParseDirectiveWord
1428///  ::= .word [ expression (, expression)* ]
1429bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1430  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1431    for (;;) {
1432      const MCExpr *Value;
1433      if (getParser().parseExpression(Value))
1434        return false;
1435
1436      getParser().getStreamer().EmitValue(Value, Size);
1437
1438      if (getLexer().is(AsmToken::EndOfStatement))
1439        break;
1440
1441      if (getLexer().isNot(AsmToken::Comma))
1442        return Error(L, "unexpected token in directive");
1443      Parser.Lex();
1444    }
1445  }
1446
1447  Parser.Lex();
1448  return false;
1449}
1450
1451/// ParseDirectiveTC
1452///  ::= .tc [ symbol (, expression)* ]
1453bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1454  // Skip TC symbol, which is only used with XCOFF.
1455  while (getLexer().isNot(AsmToken::EndOfStatement)
1456         && getLexer().isNot(AsmToken::Comma))
1457    Parser.Lex();
1458  if (getLexer().isNot(AsmToken::Comma)) {
1459    Error(L, "unexpected token in directive");
1460    return false;
1461  }
1462  Parser.Lex();
1463
1464  // Align to word size.
1465  getParser().getStreamer().EmitValueToAlignment(Size);
1466
1467  // Emit expressions.
1468  return ParseDirectiveWord(Size, L);
1469}
1470
1471/// ParseDirectiveMachine (ELF platforms)
1472///  ::= .machine [ cpu | "push" | "pop" ]
1473bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1474  if (getLexer().isNot(AsmToken::Identifier) &&
1475      getLexer().isNot(AsmToken::String)) {
1476    Error(L, "unexpected token in directive");
1477    return false;
1478  }
1479
1480  StringRef CPU = Parser.getTok().getIdentifier();
1481  Parser.Lex();
1482
1483  // FIXME: Right now, the parser always allows any available
1484  // instruction, so the .machine directive is not useful.
1485  // Implement ".machine any" (by doing nothing) for the benefit
1486  // of existing assembler code.  Likewise, we can then implement
1487  // ".machine push" and ".machine pop" as no-op.
1488  if (CPU != "any" && CPU != "push" && CPU != "pop") {
1489    Error(L, "unrecognized machine type");
1490    return false;
1491  }
1492
1493  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1494    Error(L, "unexpected token in directive");
1495    return false;
1496  }
1497  PPCTargetStreamer &TStreamer =
1498      *static_cast<PPCTargetStreamer *>(
1499           getParser().getStreamer().getTargetStreamer());
1500  TStreamer.emitMachine(CPU);
1501
1502  return false;
1503}
1504
1505/// ParseDarwinDirectiveMachine (Mach-o platforms)
1506///  ::= .machine cpu-identifier
1507bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1508  if (getLexer().isNot(AsmToken::Identifier) &&
1509      getLexer().isNot(AsmToken::String)) {
1510    Error(L, "unexpected token in directive");
1511    return false;
1512  }
1513
1514  StringRef CPU = Parser.getTok().getIdentifier();
1515  Parser.Lex();
1516
1517  // FIXME: this is only the 'default' set of cpu variants.
1518  // However we don't act on this information at present, this is simply
1519  // allowing parsing to proceed with minimal sanity checking.
1520  if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1521    Error(L, "unrecognized cpu type");
1522    return false;
1523  }
1524
1525  if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1526    Error(L, "wrong cpu type specified for 64bit");
1527    return false;
1528  }
1529  if (!isPPC64() && CPU == "ppc64") {
1530    Error(L, "wrong cpu type specified for 32bit");
1531    return false;
1532  }
1533
1534  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1535    Error(L, "unexpected token in directive");
1536    return false;
1537  }
1538
1539  return false;
1540}
1541
1542/// Force static initialization.
1543extern "C" void LLVMInitializePowerPCAsmParser() {
1544  RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1545  RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1546  RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1547}
1548
1549#define GET_REGISTER_MATCHER
1550#define GET_MATCHER_IMPLEMENTATION
1551#include "PPCGenAsmMatcher.inc"
1552
1553// Define this matcher function after the auto-generated include so we
1554// have the match class enum definitions.
1555unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1556                                                  unsigned Kind) {
1557  // If the kind is a token for a literal immediate, check if our asm
1558  // operand matches. This is for InstAliases which have a fixed-value
1559  // immediate in the syntax.
1560  int64_t ImmVal;
1561  switch (Kind) {
1562    case MCK_0: ImmVal = 0; break;
1563    case MCK_1: ImmVal = 1; break;
1564    case MCK_2: ImmVal = 2; break;
1565    case MCK_3: ImmVal = 3; break;
1566    default: return Match_InvalidOperand;
1567  }
1568
1569  PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1570  if (Op->isImm() && Op->getImm() == ImmVal)
1571    return Match_Success;
1572
1573  return Match_InvalidOperand;
1574}
1575
1576const MCExpr *
1577PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1578                                  MCSymbolRefExpr::VariantKind Variant,
1579                                  MCContext &Ctx) {
1580  switch (Variant) {
1581  case MCSymbolRefExpr::VK_PPC_LO:
1582    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1583  case MCSymbolRefExpr::VK_PPC_HI:
1584    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1585  case MCSymbolRefExpr::VK_PPC_HA:
1586    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1587  case MCSymbolRefExpr::VK_PPC_HIGHER:
1588    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1589  case MCSymbolRefExpr::VK_PPC_HIGHERA:
1590    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1591  case MCSymbolRefExpr::VK_PPC_HIGHEST:
1592    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1593  case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1594    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1595  default:
1596    return 0;
1597  }
1598}
1599