PPCAsmParser.cpp revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/PPCMCTargetDesc.h"
11#include "MCTargetDesc/PPCMCExpr.h"
12#include "PPCTargetStreamer.h"
13#include "llvm/ADT/STLExtras.h"
14#include "llvm/ADT/SmallString.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringSwitch.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCParser/MCAsmLexer.h"
22#include "llvm/MC/MCParser/MCAsmParser.h"
23#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCTargetAsmParser.h"
28#include "llvm/Support/SourceMgr.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31
32using namespace llvm;
33
34namespace {
35
36static unsigned RRegs[32] = {
37  PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44  PPC::R28, PPC::R29, PPC::R30, PPC::R31
45};
46static unsigned RRegsNoR0[32] = {
47  PPC::ZERO,
48            PPC::R1,  PPC::R2,  PPC::R3,
49  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55  PPC::R28, PPC::R29, PPC::R30, PPC::R31
56};
57static unsigned XRegs[32] = {
58  PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65  PPC::X28, PPC::X29, PPC::X30, PPC::X31
66};
67static unsigned XRegsNoX0[32] = {
68  PPC::ZERO8,
69            PPC::X1,  PPC::X2,  PPC::X3,
70  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76  PPC::X28, PPC::X29, PPC::X30, PPC::X31
77};
78static unsigned FRegs[32] = {
79  PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80  PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81  PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86  PPC::F28, PPC::F29, PPC::F30, PPC::F31
87};
88static unsigned VRegs[32] = {
89  PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90  PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91  PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96  PPC::V28, PPC::V29, PPC::V30, PPC::V31
97};
98static unsigned VSRegs[64] = {
99  PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100  PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101  PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107
108  PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109  PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110  PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111  PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112  PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113  PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114  PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115  PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116};
117static unsigned VSFRegs[64] = {
118  PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119  PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120  PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126
127  PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128  PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129  PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135};
136static unsigned CRBITRegs[32] = {
137  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
138  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
139  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
140  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
141  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
142  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
143  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
144  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
145};
146static unsigned CRRegs[8] = {
147  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
148  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
149};
150
151// Evaluate an expression containing condition register
152// or condition register field symbols.  Returns positive
153// value on success, or -1 on error.
154static int64_t
155EvaluateCRExpr(const MCExpr *E) {
156  switch (E->getKind()) {
157  case MCExpr::Target:
158    return -1;
159
160  case MCExpr::Constant: {
161    int64_t Res = cast<MCConstantExpr>(E)->getValue();
162    return Res < 0 ? -1 : Res;
163  }
164
165  case MCExpr::SymbolRef: {
166    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
167    StringRef Name = SRE->getSymbol().getName();
168
169    if (Name == "lt") return 0;
170    if (Name == "gt") return 1;
171    if (Name == "eq") return 2;
172    if (Name == "so") return 3;
173    if (Name == "un") return 3;
174
175    if (Name == "cr0") return 0;
176    if (Name == "cr1") return 1;
177    if (Name == "cr2") return 2;
178    if (Name == "cr3") return 3;
179    if (Name == "cr4") return 4;
180    if (Name == "cr5") return 5;
181    if (Name == "cr6") return 6;
182    if (Name == "cr7") return 7;
183
184    return -1;
185  }
186
187  case MCExpr::Unary:
188    return -1;
189
190  case MCExpr::Binary: {
191    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
192    int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
193    int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
194    int64_t Res;
195
196    if (LHSVal < 0 || RHSVal < 0)
197      return -1;
198
199    switch (BE->getOpcode()) {
200    default: return -1;
201    case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
202    case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
203    }
204
205    return Res < 0 ? -1 : Res;
206  }
207  }
208
209  llvm_unreachable("Invalid expression kind!");
210}
211
212struct PPCOperand;
213
214class PPCAsmParser : public MCTargetAsmParser {
215  MCSubtargetInfo &STI;
216  MCAsmParser &Parser;
217  const MCInstrInfo &MII;
218  bool IsPPC64;
219  bool IsDarwin;
220
221  MCAsmParser &getParser() const { return Parser; }
222  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
223
224  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
225  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
226
227  bool isPPC64() const { return IsPPC64; }
228  bool isDarwin() const { return IsDarwin; }
229
230  bool MatchRegisterName(const AsmToken &Tok,
231                         unsigned &RegNo, int64_t &IntVal);
232
233  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
234
235  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
236                                        PPCMCExpr::VariantKind &Variant);
237  const MCExpr *FixupVariantKind(const MCExpr *E);
238  bool ParseExpression(const MCExpr *&EVal);
239  bool ParseDarwinExpression(const MCExpr *&EVal);
240
241  bool ParseOperand(OperandVector &Operands);
242
243  bool ParseDirectiveWord(unsigned Size, SMLoc L);
244  bool ParseDirectiveTC(unsigned Size, SMLoc L);
245  bool ParseDirectiveMachine(SMLoc L);
246  bool ParseDarwinDirectiveMachine(SMLoc L);
247
248  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
249                               OperandVector &Operands, MCStreamer &Out,
250                               unsigned &ErrorInfo,
251                               bool MatchingInlineAsm) override;
252
253  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
254
255  /// @name Auto-generated Match Functions
256  /// {
257
258#define GET_ASSEMBLER_HEADER
259#include "PPCGenAsmMatcher.inc"
260
261  /// }
262
263
264public:
265  PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
266               const MCInstrInfo &_MII,
267               const MCTargetOptions &Options)
268      : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
269    // Check for 64-bit vs. 32-bit pointer mode.
270    Triple TheTriple(STI.getTargetTriple());
271    IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
272               TheTriple.getArch() == Triple::ppc64le);
273    IsDarwin = TheTriple.isMacOSX();
274    // Initialize the set of available features.
275    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276  }
277
278  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
279                        SMLoc NameLoc, OperandVector &Operands) override;
280
281  bool ParseDirective(AsmToken DirectiveID) override;
282
283  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
284                                      unsigned Kind) override;
285
286  const MCExpr *applyModifierToExpr(const MCExpr *E,
287                                    MCSymbolRefExpr::VariantKind,
288                                    MCContext &Ctx) override;
289};
290
291/// PPCOperand - Instances of this class represent a parsed PowerPC machine
292/// instruction.
293struct PPCOperand : public MCParsedAsmOperand {
294  enum KindTy {
295    Token,
296    Immediate,
297    Expression,
298    TLSRegister
299  } Kind;
300
301  SMLoc StartLoc, EndLoc;
302  bool IsPPC64;
303
304  struct TokOp {
305    const char *Data;
306    unsigned Length;
307  };
308
309  struct ImmOp {
310    int64_t Val;
311  };
312
313  struct ExprOp {
314    const MCExpr *Val;
315    int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
316  };
317
318  struct TLSRegOp {
319    const MCSymbolRefExpr *Sym;
320  };
321
322  union {
323    struct TokOp Tok;
324    struct ImmOp Imm;
325    struct ExprOp Expr;
326    struct TLSRegOp TLSReg;
327  };
328
329  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
330public:
331  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
332    Kind = o.Kind;
333    StartLoc = o.StartLoc;
334    EndLoc = o.EndLoc;
335    IsPPC64 = o.IsPPC64;
336    switch (Kind) {
337    case Token:
338      Tok = o.Tok;
339      break;
340    case Immediate:
341      Imm = o.Imm;
342      break;
343    case Expression:
344      Expr = o.Expr;
345      break;
346    case TLSRegister:
347      TLSReg = o.TLSReg;
348      break;
349    }
350  }
351
352  /// getStartLoc - Get the location of the first token of this operand.
353  SMLoc getStartLoc() const override { return StartLoc; }
354
355  /// getEndLoc - Get the location of the last token of this operand.
356  SMLoc getEndLoc() const override { return EndLoc; }
357
358  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
359  bool isPPC64() const { return IsPPC64; }
360
361  int64_t getImm() const {
362    assert(Kind == Immediate && "Invalid access!");
363    return Imm.Val;
364  }
365
366  const MCExpr *getExpr() const {
367    assert(Kind == Expression && "Invalid access!");
368    return Expr.Val;
369  }
370
371  int64_t getExprCRVal() const {
372    assert(Kind == Expression && "Invalid access!");
373    return Expr.CRVal;
374  }
375
376  const MCExpr *getTLSReg() const {
377    assert(Kind == TLSRegister && "Invalid access!");
378    return TLSReg.Sym;
379  }
380
381  unsigned getReg() const override {
382    assert(isRegNumber() && "Invalid access!");
383    return (unsigned) Imm.Val;
384  }
385
386  unsigned getVSReg() const {
387    assert(isVSRegNumber() && "Invalid access!");
388    return (unsigned) Imm.Val;
389  }
390
391  unsigned getCCReg() const {
392    assert(isCCRegNumber() && "Invalid access!");
393    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
394  }
395
396  unsigned getCRBit() const {
397    assert(isCRBitNumber() && "Invalid access!");
398    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
399  }
400
401  unsigned getCRBitMask() const {
402    assert(isCRBitMask() && "Invalid access!");
403    return 7 - countTrailingZeros<uint64_t>(Imm.Val);
404  }
405
406  bool isToken() const override { return Kind == Token; }
407  bool isImm() const override { return Kind == Immediate || Kind == Expression; }
408  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
409  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
410  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
411  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
412  bool isU16Imm() const { return Kind == Expression ||
413                                 (Kind == Immediate && isUInt<16>(getImm())); }
414  bool isS16Imm() const { return Kind == Expression ||
415                                 (Kind == Immediate && isInt<16>(getImm())); }
416  bool isS16ImmX4() const { return Kind == Expression ||
417                                   (Kind == Immediate && isInt<16>(getImm()) &&
418                                    (getImm() & 3) == 0); }
419  bool isS17Imm() const { return Kind == Expression ||
420                                 (Kind == Immediate && isInt<17>(getImm())); }
421  bool isTLSReg() const { return Kind == TLSRegister; }
422  bool isDirectBr() const { return Kind == Expression ||
423                                   (Kind == Immediate && isInt<26>(getImm()) &&
424                                    (getImm() & 3) == 0); }
425  bool isCondBr() const { return Kind == Expression ||
426                                 (Kind == Immediate && isInt<16>(getImm()) &&
427                                  (getImm() & 3) == 0); }
428  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
429  bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
430  bool isCCRegNumber() const { return (Kind == Expression
431                                       && isUInt<3>(getExprCRVal())) ||
432                                      (Kind == Immediate
433                                       && isUInt<3>(getImm())); }
434  bool isCRBitNumber() const { return (Kind == Expression
435                                       && isUInt<5>(getExprCRVal())) ||
436                                      (Kind == Immediate
437                                       && isUInt<5>(getImm())); }
438  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
439                                    isPowerOf2_32(getImm()); }
440  bool isMem() const override { return false; }
441  bool isReg() const override { return false; }
442
443  void addRegOperands(MCInst &Inst, unsigned N) const {
444    llvm_unreachable("addRegOperands");
445  }
446
447  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
448    assert(N == 1 && "Invalid number of operands!");
449    Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
450  }
451
452  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
453    assert(N == 1 && "Invalid number of operands!");
454    Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
455  }
456
457  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
458    assert(N == 1 && "Invalid number of operands!");
459    Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
460  }
461
462  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
463    assert(N == 1 && "Invalid number of operands!");
464    Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
465  }
466
467  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
468    if (isPPC64())
469      addRegG8RCOperands(Inst, N);
470    else
471      addRegGPRCOperands(Inst, N);
472  }
473
474  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
475    if (isPPC64())
476      addRegG8RCNoX0Operands(Inst, N);
477    else
478      addRegGPRCNoR0Operands(Inst, N);
479  }
480
481  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
482    assert(N == 1 && "Invalid number of operands!");
483    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
484  }
485
486  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
487    assert(N == 1 && "Invalid number of operands!");
488    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
489  }
490
491  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
492    assert(N == 1 && "Invalid number of operands!");
493    Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
494  }
495
496  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
497    assert(N == 1 && "Invalid number of operands!");
498    Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
499  }
500
501  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
502    assert(N == 1 && "Invalid number of operands!");
503    Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
504  }
505
506  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
507    assert(N == 1 && "Invalid number of operands!");
508    Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
509  }
510
511  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
512    assert(N == 1 && "Invalid number of operands!");
513    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
514  }
515
516  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
517    assert(N == 1 && "Invalid number of operands!");
518    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
519  }
520
521  void addImmOperands(MCInst &Inst, unsigned N) const {
522    assert(N == 1 && "Invalid number of operands!");
523    if (Kind == Immediate)
524      Inst.addOperand(MCOperand::CreateImm(getImm()));
525    else
526      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
527  }
528
529  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
530    assert(N == 1 && "Invalid number of operands!");
531    if (Kind == Immediate)
532      Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
533    else
534      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
535  }
536
537  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
538    assert(N == 1 && "Invalid number of operands!");
539    Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
540  }
541
542  StringRef getToken() const {
543    assert(Kind == Token && "Invalid access!");
544    return StringRef(Tok.Data, Tok.Length);
545  }
546
547  void print(raw_ostream &OS) const override;
548
549  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
550                                                 bool IsPPC64) {
551    auto Op = make_unique<PPCOperand>(Token);
552    Op->Tok.Data = Str.data();
553    Op->Tok.Length = Str.size();
554    Op->StartLoc = S;
555    Op->EndLoc = S;
556    Op->IsPPC64 = IsPPC64;
557    return Op;
558  }
559
560  static std::unique_ptr<PPCOperand>
561  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
562    // Allocate extra memory for the string and copy it.
563    // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
564    // deleter which will destroy them by simply using "delete", not correctly
565    // calling operator delete on this extra memory after calling the dtor
566    // explicitly.
567    void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
568    std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
569    Op->Tok.Data = (const char *)(Op.get() + 1);
570    Op->Tok.Length = Str.size();
571    std::memcpy((void *)Op->Tok.Data, Str.data(), Str.size());
572    Op->StartLoc = S;
573    Op->EndLoc = S;
574    Op->IsPPC64 = IsPPC64;
575    return Op;
576  }
577
578  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
579                                               bool IsPPC64) {
580    auto Op = make_unique<PPCOperand>(Immediate);
581    Op->Imm.Val = Val;
582    Op->StartLoc = S;
583    Op->EndLoc = E;
584    Op->IsPPC64 = IsPPC64;
585    return Op;
586  }
587
588  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
589                                                SMLoc E, bool IsPPC64) {
590    auto Op = make_unique<PPCOperand>(Expression);
591    Op->Expr.Val = Val;
592    Op->Expr.CRVal = EvaluateCRExpr(Val);
593    Op->StartLoc = S;
594    Op->EndLoc = E;
595    Op->IsPPC64 = IsPPC64;
596    return Op;
597  }
598
599  static std::unique_ptr<PPCOperand>
600  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
601    auto Op = make_unique<PPCOperand>(TLSRegister);
602    Op->TLSReg.Sym = Sym;
603    Op->StartLoc = S;
604    Op->EndLoc = E;
605    Op->IsPPC64 = IsPPC64;
606    return Op;
607  }
608
609  static std::unique_ptr<PPCOperand>
610  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
611    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
612      return CreateImm(CE->getValue(), S, E, IsPPC64);
613
614    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
615      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
616        return CreateTLSReg(SRE, S, E, IsPPC64);
617
618    return CreateExpr(Val, S, E, IsPPC64);
619  }
620};
621
622} // end anonymous namespace.
623
624void PPCOperand::print(raw_ostream &OS) const {
625  switch (Kind) {
626  case Token:
627    OS << "'" << getToken() << "'";
628    break;
629  case Immediate:
630    OS << getImm();
631    break;
632  case Expression:
633    getExpr()->print(OS);
634    break;
635  case TLSRegister:
636    getTLSReg()->print(OS);
637    break;
638  }
639}
640
641void PPCAsmParser::ProcessInstruction(MCInst &Inst,
642                                      const OperandVector &Operands) {
643  int Opcode = Inst.getOpcode();
644  switch (Opcode) {
645  case PPC::LAx: {
646    MCInst TmpInst;
647    TmpInst.setOpcode(PPC::LA);
648    TmpInst.addOperand(Inst.getOperand(0));
649    TmpInst.addOperand(Inst.getOperand(2));
650    TmpInst.addOperand(Inst.getOperand(1));
651    Inst = TmpInst;
652    break;
653  }
654  case PPC::SUBI: {
655    MCInst TmpInst;
656    int64_t N = Inst.getOperand(2).getImm();
657    TmpInst.setOpcode(PPC::ADDI);
658    TmpInst.addOperand(Inst.getOperand(0));
659    TmpInst.addOperand(Inst.getOperand(1));
660    TmpInst.addOperand(MCOperand::CreateImm(-N));
661    Inst = TmpInst;
662    break;
663  }
664  case PPC::SUBIS: {
665    MCInst TmpInst;
666    int64_t N = Inst.getOperand(2).getImm();
667    TmpInst.setOpcode(PPC::ADDIS);
668    TmpInst.addOperand(Inst.getOperand(0));
669    TmpInst.addOperand(Inst.getOperand(1));
670    TmpInst.addOperand(MCOperand::CreateImm(-N));
671    Inst = TmpInst;
672    break;
673  }
674  case PPC::SUBIC: {
675    MCInst TmpInst;
676    int64_t N = Inst.getOperand(2).getImm();
677    TmpInst.setOpcode(PPC::ADDIC);
678    TmpInst.addOperand(Inst.getOperand(0));
679    TmpInst.addOperand(Inst.getOperand(1));
680    TmpInst.addOperand(MCOperand::CreateImm(-N));
681    Inst = TmpInst;
682    break;
683  }
684  case PPC::SUBICo: {
685    MCInst TmpInst;
686    int64_t N = Inst.getOperand(2).getImm();
687    TmpInst.setOpcode(PPC::ADDICo);
688    TmpInst.addOperand(Inst.getOperand(0));
689    TmpInst.addOperand(Inst.getOperand(1));
690    TmpInst.addOperand(MCOperand::CreateImm(-N));
691    Inst = TmpInst;
692    break;
693  }
694  case PPC::EXTLWI:
695  case PPC::EXTLWIo: {
696    MCInst TmpInst;
697    int64_t N = Inst.getOperand(2).getImm();
698    int64_t B = Inst.getOperand(3).getImm();
699    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
700    TmpInst.addOperand(Inst.getOperand(0));
701    TmpInst.addOperand(Inst.getOperand(1));
702    TmpInst.addOperand(MCOperand::CreateImm(B));
703    TmpInst.addOperand(MCOperand::CreateImm(0));
704    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
705    Inst = TmpInst;
706    break;
707  }
708  case PPC::EXTRWI:
709  case PPC::EXTRWIo: {
710    MCInst TmpInst;
711    int64_t N = Inst.getOperand(2).getImm();
712    int64_t B = Inst.getOperand(3).getImm();
713    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
714    TmpInst.addOperand(Inst.getOperand(0));
715    TmpInst.addOperand(Inst.getOperand(1));
716    TmpInst.addOperand(MCOperand::CreateImm(B + N));
717    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
718    TmpInst.addOperand(MCOperand::CreateImm(31));
719    Inst = TmpInst;
720    break;
721  }
722  case PPC::INSLWI:
723  case PPC::INSLWIo: {
724    MCInst TmpInst;
725    int64_t N = Inst.getOperand(2).getImm();
726    int64_t B = Inst.getOperand(3).getImm();
727    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
728    TmpInst.addOperand(Inst.getOperand(0));
729    TmpInst.addOperand(Inst.getOperand(0));
730    TmpInst.addOperand(Inst.getOperand(1));
731    TmpInst.addOperand(MCOperand::CreateImm(32 - B));
732    TmpInst.addOperand(MCOperand::CreateImm(B));
733    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
734    Inst = TmpInst;
735    break;
736  }
737  case PPC::INSRWI:
738  case PPC::INSRWIo: {
739    MCInst TmpInst;
740    int64_t N = Inst.getOperand(2).getImm();
741    int64_t B = Inst.getOperand(3).getImm();
742    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
743    TmpInst.addOperand(Inst.getOperand(0));
744    TmpInst.addOperand(Inst.getOperand(0));
745    TmpInst.addOperand(Inst.getOperand(1));
746    TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
747    TmpInst.addOperand(MCOperand::CreateImm(B));
748    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
749    Inst = TmpInst;
750    break;
751  }
752  case PPC::ROTRWI:
753  case PPC::ROTRWIo: {
754    MCInst TmpInst;
755    int64_t N = Inst.getOperand(2).getImm();
756    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
757    TmpInst.addOperand(Inst.getOperand(0));
758    TmpInst.addOperand(Inst.getOperand(1));
759    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
760    TmpInst.addOperand(MCOperand::CreateImm(0));
761    TmpInst.addOperand(MCOperand::CreateImm(31));
762    Inst = TmpInst;
763    break;
764  }
765  case PPC::SLWI:
766  case PPC::SLWIo: {
767    MCInst TmpInst;
768    int64_t N = Inst.getOperand(2).getImm();
769    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
770    TmpInst.addOperand(Inst.getOperand(0));
771    TmpInst.addOperand(Inst.getOperand(1));
772    TmpInst.addOperand(MCOperand::CreateImm(N));
773    TmpInst.addOperand(MCOperand::CreateImm(0));
774    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
775    Inst = TmpInst;
776    break;
777  }
778  case PPC::SRWI:
779  case PPC::SRWIo: {
780    MCInst TmpInst;
781    int64_t N = Inst.getOperand(2).getImm();
782    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
783    TmpInst.addOperand(Inst.getOperand(0));
784    TmpInst.addOperand(Inst.getOperand(1));
785    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
786    TmpInst.addOperand(MCOperand::CreateImm(N));
787    TmpInst.addOperand(MCOperand::CreateImm(31));
788    Inst = TmpInst;
789    break;
790  }
791  case PPC::CLRRWI:
792  case PPC::CLRRWIo: {
793    MCInst TmpInst;
794    int64_t N = Inst.getOperand(2).getImm();
795    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
796    TmpInst.addOperand(Inst.getOperand(0));
797    TmpInst.addOperand(Inst.getOperand(1));
798    TmpInst.addOperand(MCOperand::CreateImm(0));
799    TmpInst.addOperand(MCOperand::CreateImm(0));
800    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
801    Inst = TmpInst;
802    break;
803  }
804  case PPC::CLRLSLWI:
805  case PPC::CLRLSLWIo: {
806    MCInst TmpInst;
807    int64_t B = Inst.getOperand(2).getImm();
808    int64_t N = Inst.getOperand(3).getImm();
809    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
810    TmpInst.addOperand(Inst.getOperand(0));
811    TmpInst.addOperand(Inst.getOperand(1));
812    TmpInst.addOperand(MCOperand::CreateImm(N));
813    TmpInst.addOperand(MCOperand::CreateImm(B - N));
814    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
815    Inst = TmpInst;
816    break;
817  }
818  case PPC::EXTLDI:
819  case PPC::EXTLDIo: {
820    MCInst TmpInst;
821    int64_t N = Inst.getOperand(2).getImm();
822    int64_t B = Inst.getOperand(3).getImm();
823    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
824    TmpInst.addOperand(Inst.getOperand(0));
825    TmpInst.addOperand(Inst.getOperand(1));
826    TmpInst.addOperand(MCOperand::CreateImm(B));
827    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
828    Inst = TmpInst;
829    break;
830  }
831  case PPC::EXTRDI:
832  case PPC::EXTRDIo: {
833    MCInst TmpInst;
834    int64_t N = Inst.getOperand(2).getImm();
835    int64_t B = Inst.getOperand(3).getImm();
836    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
837    TmpInst.addOperand(Inst.getOperand(0));
838    TmpInst.addOperand(Inst.getOperand(1));
839    TmpInst.addOperand(MCOperand::CreateImm(B + N));
840    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
841    Inst = TmpInst;
842    break;
843  }
844  case PPC::INSRDI:
845  case PPC::INSRDIo: {
846    MCInst TmpInst;
847    int64_t N = Inst.getOperand(2).getImm();
848    int64_t B = Inst.getOperand(3).getImm();
849    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
850    TmpInst.addOperand(Inst.getOperand(0));
851    TmpInst.addOperand(Inst.getOperand(0));
852    TmpInst.addOperand(Inst.getOperand(1));
853    TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
854    TmpInst.addOperand(MCOperand::CreateImm(B));
855    Inst = TmpInst;
856    break;
857  }
858  case PPC::ROTRDI:
859  case PPC::ROTRDIo: {
860    MCInst TmpInst;
861    int64_t N = Inst.getOperand(2).getImm();
862    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
863    TmpInst.addOperand(Inst.getOperand(0));
864    TmpInst.addOperand(Inst.getOperand(1));
865    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
866    TmpInst.addOperand(MCOperand::CreateImm(0));
867    Inst = TmpInst;
868    break;
869  }
870  case PPC::SLDI:
871  case PPC::SLDIo: {
872    MCInst TmpInst;
873    int64_t N = Inst.getOperand(2).getImm();
874    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
875    TmpInst.addOperand(Inst.getOperand(0));
876    TmpInst.addOperand(Inst.getOperand(1));
877    TmpInst.addOperand(MCOperand::CreateImm(N));
878    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
879    Inst = TmpInst;
880    break;
881  }
882  case PPC::SRDI:
883  case PPC::SRDIo: {
884    MCInst TmpInst;
885    int64_t N = Inst.getOperand(2).getImm();
886    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
887    TmpInst.addOperand(Inst.getOperand(0));
888    TmpInst.addOperand(Inst.getOperand(1));
889    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
890    TmpInst.addOperand(MCOperand::CreateImm(N));
891    Inst = TmpInst;
892    break;
893  }
894  case PPC::CLRRDI:
895  case PPC::CLRRDIo: {
896    MCInst TmpInst;
897    int64_t N = Inst.getOperand(2).getImm();
898    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
899    TmpInst.addOperand(Inst.getOperand(0));
900    TmpInst.addOperand(Inst.getOperand(1));
901    TmpInst.addOperand(MCOperand::CreateImm(0));
902    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
903    Inst = TmpInst;
904    break;
905  }
906  case PPC::CLRLSLDI:
907  case PPC::CLRLSLDIo: {
908    MCInst TmpInst;
909    int64_t B = Inst.getOperand(2).getImm();
910    int64_t N = Inst.getOperand(3).getImm();
911    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
912    TmpInst.addOperand(Inst.getOperand(0));
913    TmpInst.addOperand(Inst.getOperand(1));
914    TmpInst.addOperand(MCOperand::CreateImm(N));
915    TmpInst.addOperand(MCOperand::CreateImm(B - N));
916    Inst = TmpInst;
917    break;
918  }
919  }
920}
921
922bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
923                                           OperandVector &Operands,
924                                           MCStreamer &Out, unsigned &ErrorInfo,
925                                           bool MatchingInlineAsm) {
926  MCInst Inst;
927
928  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
929  default: break;
930  case Match_Success:
931    // Post-process instructions (typically extended mnemonics)
932    ProcessInstruction(Inst, Operands);
933    Inst.setLoc(IDLoc);
934    Out.EmitInstruction(Inst, STI);
935    return false;
936  case Match_MissingFeature:
937    return Error(IDLoc, "instruction use requires an option to be enabled");
938  case Match_MnemonicFail:
939      return Error(IDLoc, "unrecognized instruction mnemonic");
940  case Match_InvalidOperand: {
941    SMLoc ErrorLoc = IDLoc;
942    if (ErrorInfo != ~0U) {
943      if (ErrorInfo >= Operands.size())
944        return Error(IDLoc, "too few operands for instruction");
945
946      ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
947      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
948    }
949
950    return Error(ErrorLoc, "invalid operand for instruction");
951  }
952  }
953
954  llvm_unreachable("Implement any new match types added!");
955}
956
957bool PPCAsmParser::
958MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
959  if (Tok.is(AsmToken::Identifier)) {
960    StringRef Name = Tok.getString();
961
962    if (Name.equals_lower("lr")) {
963      RegNo = isPPC64()? PPC::LR8 : PPC::LR;
964      IntVal = 8;
965      return false;
966    } else if (Name.equals_lower("ctr")) {
967      RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
968      IntVal = 9;
969      return false;
970    } else if (Name.equals_lower("vrsave")) {
971      RegNo = PPC::VRSAVE;
972      IntVal = 256;
973      return false;
974    } else if (Name.startswith_lower("r") &&
975               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
976      RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
977      return false;
978    } else if (Name.startswith_lower("f") &&
979               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
980      RegNo = FRegs[IntVal];
981      return false;
982    } else if (Name.startswith_lower("v") &&
983               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
984      RegNo = VRegs[IntVal];
985      return false;
986    } else if (Name.startswith_lower("cr") &&
987               !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
988      RegNo = CRRegs[IntVal];
989      return false;
990    }
991  }
992
993  return true;
994}
995
996bool PPCAsmParser::
997ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
998  const AsmToken &Tok = Parser.getTok();
999  StartLoc = Tok.getLoc();
1000  EndLoc = Tok.getEndLoc();
1001  RegNo = 0;
1002  int64_t IntVal;
1003
1004  if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1005    Parser.Lex(); // Eat identifier token.
1006    return false;
1007  }
1008
1009  return Error(StartLoc, "invalid register name");
1010}
1011
1012/// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1013/// the expression and check for VK_PPC_LO/HI/HA
1014/// symbol variants.  If all symbols with modifier use the same
1015/// variant, return the corresponding PPCMCExpr::VariantKind,
1016/// and a modified expression using the default symbol variant.
1017/// Otherwise, return NULL.
1018const MCExpr *PPCAsmParser::
1019ExtractModifierFromExpr(const MCExpr *E,
1020                        PPCMCExpr::VariantKind &Variant) {
1021  MCContext &Context = getParser().getContext();
1022  Variant = PPCMCExpr::VK_PPC_None;
1023
1024  switch (E->getKind()) {
1025  case MCExpr::Target:
1026  case MCExpr::Constant:
1027    return nullptr;
1028
1029  case MCExpr::SymbolRef: {
1030    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1031
1032    switch (SRE->getKind()) {
1033    case MCSymbolRefExpr::VK_PPC_LO:
1034      Variant = PPCMCExpr::VK_PPC_LO;
1035      break;
1036    case MCSymbolRefExpr::VK_PPC_HI:
1037      Variant = PPCMCExpr::VK_PPC_HI;
1038      break;
1039    case MCSymbolRefExpr::VK_PPC_HA:
1040      Variant = PPCMCExpr::VK_PPC_HA;
1041      break;
1042    case MCSymbolRefExpr::VK_PPC_HIGHER:
1043      Variant = PPCMCExpr::VK_PPC_HIGHER;
1044      break;
1045    case MCSymbolRefExpr::VK_PPC_HIGHERA:
1046      Variant = PPCMCExpr::VK_PPC_HIGHERA;
1047      break;
1048    case MCSymbolRefExpr::VK_PPC_HIGHEST:
1049      Variant = PPCMCExpr::VK_PPC_HIGHEST;
1050      break;
1051    case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1052      Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1053      break;
1054    default:
1055      return nullptr;
1056    }
1057
1058    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1059  }
1060
1061  case MCExpr::Unary: {
1062    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1063    const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1064    if (!Sub)
1065      return nullptr;
1066    return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1067  }
1068
1069  case MCExpr::Binary: {
1070    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1071    PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1072    const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1073    const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1074
1075    if (!LHS && !RHS)
1076      return nullptr;
1077
1078    if (!LHS) LHS = BE->getLHS();
1079    if (!RHS) RHS = BE->getRHS();
1080
1081    if (LHSVariant == PPCMCExpr::VK_PPC_None)
1082      Variant = RHSVariant;
1083    else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1084      Variant = LHSVariant;
1085    else if (LHSVariant == RHSVariant)
1086      Variant = LHSVariant;
1087    else
1088      return nullptr;
1089
1090    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1091  }
1092  }
1093
1094  llvm_unreachable("Invalid expression kind!");
1095}
1096
1097/// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1098/// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1099/// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1100/// FIXME: This is a hack.
1101const MCExpr *PPCAsmParser::
1102FixupVariantKind(const MCExpr *E) {
1103  MCContext &Context = getParser().getContext();
1104
1105  switch (E->getKind()) {
1106  case MCExpr::Target:
1107  case MCExpr::Constant:
1108    return E;
1109
1110  case MCExpr::SymbolRef: {
1111    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1112    MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1113
1114    switch (SRE->getKind()) {
1115    case MCSymbolRefExpr::VK_TLSGD:
1116      Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1117      break;
1118    case MCSymbolRefExpr::VK_TLSLD:
1119      Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1120      break;
1121    default:
1122      return E;
1123    }
1124    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1125  }
1126
1127  case MCExpr::Unary: {
1128    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1129    const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1130    if (Sub == UE->getSubExpr())
1131      return E;
1132    return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1133  }
1134
1135  case MCExpr::Binary: {
1136    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1137    const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1138    const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1139    if (LHS == BE->getLHS() && RHS == BE->getRHS())
1140      return E;
1141    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1142  }
1143  }
1144
1145  llvm_unreachable("Invalid expression kind!");
1146}
1147
1148/// ParseExpression.  This differs from the default "parseExpression" in that
1149/// it handles modifiers.
1150bool PPCAsmParser::
1151ParseExpression(const MCExpr *&EVal) {
1152
1153  if (isDarwin())
1154    return ParseDarwinExpression(EVal);
1155
1156  // (ELF Platforms)
1157  // Handle \code @l/@ha \endcode
1158  if (getParser().parseExpression(EVal))
1159    return true;
1160
1161  EVal = FixupVariantKind(EVal);
1162
1163  PPCMCExpr::VariantKind Variant;
1164  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1165  if (E)
1166    EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1167
1168  return false;
1169}
1170
1171/// ParseDarwinExpression.  (MachO Platforms)
1172/// This differs from the default "parseExpression" in that it handles detection
1173/// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1174/// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1175/// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1176/// for this to be done at a higher level.
1177bool PPCAsmParser::
1178ParseDarwinExpression(const MCExpr *&EVal) {
1179  PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1180  switch (getLexer().getKind()) {
1181  default:
1182    break;
1183  case AsmToken::Identifier:
1184    // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1185    // something starting with any other char should be part of the
1186    // asm syntax.  If handwritten asm includes an identifier like lo16,
1187    // then all bets are off - but no-one would do that, right?
1188    StringRef poss = Parser.getTok().getString();
1189    if (poss.equals_lower("lo16")) {
1190      Variant = PPCMCExpr::VK_PPC_LO;
1191    } else if (poss.equals_lower("hi16")) {
1192      Variant = PPCMCExpr::VK_PPC_HI;
1193    } else if (poss.equals_lower("ha16")) {
1194      Variant = PPCMCExpr::VK_PPC_HA;
1195    }
1196    if (Variant != PPCMCExpr::VK_PPC_None) {
1197      Parser.Lex(); // Eat the xx16
1198      if (getLexer().isNot(AsmToken::LParen))
1199        return Error(Parser.getTok().getLoc(), "expected '('");
1200      Parser.Lex(); // Eat the '('
1201    }
1202    break;
1203  }
1204
1205  if (getParser().parseExpression(EVal))
1206    return true;
1207
1208  if (Variant != PPCMCExpr::VK_PPC_None) {
1209    if (getLexer().isNot(AsmToken::RParen))
1210      return Error(Parser.getTok().getLoc(), "expected ')'");
1211    Parser.Lex(); // Eat the ')'
1212    EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1213  }
1214  return false;
1215}
1216
1217/// ParseOperand
1218/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1219/// rNN for MachO.
1220bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1221  SMLoc S = Parser.getTok().getLoc();
1222  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1223  const MCExpr *EVal;
1224
1225  // Attempt to parse the next token as an immediate
1226  switch (getLexer().getKind()) {
1227  // Special handling for register names.  These are interpreted
1228  // as immediates corresponding to the register number.
1229  case AsmToken::Percent:
1230    Parser.Lex(); // Eat the '%'.
1231    unsigned RegNo;
1232    int64_t IntVal;
1233    if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1234      Parser.Lex(); // Eat the identifier token.
1235      Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1236      return false;
1237    }
1238    return Error(S, "invalid register name");
1239
1240  case AsmToken::Identifier:
1241    // Note that non-register-name identifiers from the compiler will begin
1242    // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1243    // identifiers like r31foo - so we fall through in the event that parsing
1244    // a register name fails.
1245    if (isDarwin()) {
1246      unsigned RegNo;
1247      int64_t IntVal;
1248      if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1249        Parser.Lex(); // Eat the identifier token.
1250        Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1251        return false;
1252      }
1253    }
1254  // Fall-through to process non-register-name identifiers as expression.
1255  // All other expressions
1256  case AsmToken::LParen:
1257  case AsmToken::Plus:
1258  case AsmToken::Minus:
1259  case AsmToken::Integer:
1260  case AsmToken::Dot:
1261  case AsmToken::Dollar:
1262  case AsmToken::Exclaim:
1263  case AsmToken::Tilde:
1264    if (!ParseExpression(EVal))
1265      break;
1266    /* fall through */
1267  default:
1268    return Error(S, "unknown operand");
1269  }
1270
1271  // Push the parsed operand into the list of operands
1272  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1273
1274  // Check whether this is a TLS call expression
1275  bool TLSCall = false;
1276  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1277    TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1278
1279  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1280    const MCExpr *TLSSym;
1281
1282    Parser.Lex(); // Eat the '('.
1283    S = Parser.getTok().getLoc();
1284    if (ParseExpression(TLSSym))
1285      return Error(S, "invalid TLS call expression");
1286    if (getLexer().isNot(AsmToken::RParen))
1287      return Error(Parser.getTok().getLoc(), "missing ')'");
1288    E = Parser.getTok().getLoc();
1289    Parser.Lex(); // Eat the ')'.
1290
1291    Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1292  }
1293
1294  // Otherwise, check for D-form memory operands
1295  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1296    Parser.Lex(); // Eat the '('.
1297    S = Parser.getTok().getLoc();
1298
1299    int64_t IntVal;
1300    switch (getLexer().getKind()) {
1301    case AsmToken::Percent:
1302      Parser.Lex(); // Eat the '%'.
1303      unsigned RegNo;
1304      if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1305        return Error(S, "invalid register name");
1306      Parser.Lex(); // Eat the identifier token.
1307      break;
1308
1309    case AsmToken::Integer:
1310      if (!isDarwin()) {
1311        if (getParser().parseAbsoluteExpression(IntVal) ||
1312          IntVal < 0 || IntVal > 31)
1313        return Error(S, "invalid register number");
1314      } else {
1315        return Error(S, "unexpected integer value");
1316      }
1317      break;
1318
1319   case AsmToken::Identifier:
1320    if (isDarwin()) {
1321      unsigned RegNo;
1322      if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1323        Parser.Lex(); // Eat the identifier token.
1324        break;
1325      }
1326    }
1327    // Fall-through..
1328
1329    default:
1330      return Error(S, "invalid memory operand");
1331    }
1332
1333    if (getLexer().isNot(AsmToken::RParen))
1334      return Error(Parser.getTok().getLoc(), "missing ')'");
1335    E = Parser.getTok().getLoc();
1336    Parser.Lex(); // Eat the ')'.
1337
1338    Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1339  }
1340
1341  return false;
1342}
1343
1344/// Parse an instruction mnemonic followed by its operands.
1345bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1346                                    SMLoc NameLoc, OperandVector &Operands) {
1347  // The first operand is the token for the instruction name.
1348  // If the next character is a '+' or '-', we need to add it to the
1349  // instruction name, to match what TableGen is doing.
1350  std::string NewOpcode;
1351  if (getLexer().is(AsmToken::Plus)) {
1352    getLexer().Lex();
1353    NewOpcode = Name;
1354    NewOpcode += '+';
1355    Name = NewOpcode;
1356  }
1357  if (getLexer().is(AsmToken::Minus)) {
1358    getLexer().Lex();
1359    NewOpcode = Name;
1360    NewOpcode += '-';
1361    Name = NewOpcode;
1362  }
1363  // If the instruction ends in a '.', we need to create a separate
1364  // token for it, to match what TableGen is doing.
1365  size_t Dot = Name.find('.');
1366  StringRef Mnemonic = Name.slice(0, Dot);
1367  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1368    Operands.push_back(
1369        PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1370  else
1371    Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1372  if (Dot != StringRef::npos) {
1373    SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1374    StringRef DotStr = Name.slice(Dot, StringRef::npos);
1375    if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1376      Operands.push_back(
1377          PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1378    else
1379      Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1380  }
1381
1382  // If there are no more operands then finish
1383  if (getLexer().is(AsmToken::EndOfStatement))
1384    return false;
1385
1386  // Parse the first operand
1387  if (ParseOperand(Operands))
1388    return true;
1389
1390  while (getLexer().isNot(AsmToken::EndOfStatement) &&
1391         getLexer().is(AsmToken::Comma)) {
1392    // Consume the comma token
1393    getLexer().Lex();
1394
1395    // Parse the next operand
1396    if (ParseOperand(Operands))
1397      return true;
1398  }
1399
1400  return false;
1401}
1402
1403/// ParseDirective parses the PPC specific directives
1404bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1405  StringRef IDVal = DirectiveID.getIdentifier();
1406  if (!isDarwin()) {
1407    if (IDVal == ".word")
1408      return ParseDirectiveWord(2, DirectiveID.getLoc());
1409    if (IDVal == ".llong")
1410      return ParseDirectiveWord(8, DirectiveID.getLoc());
1411    if (IDVal == ".tc")
1412      return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1413    if (IDVal == ".machine")
1414      return ParseDirectiveMachine(DirectiveID.getLoc());
1415  } else {
1416    if (IDVal == ".machine")
1417      return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1418  }
1419  return true;
1420}
1421
1422/// ParseDirectiveWord
1423///  ::= .word [ expression (, expression)* ]
1424bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1425  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1426    for (;;) {
1427      const MCExpr *Value;
1428      if (getParser().parseExpression(Value))
1429        return false;
1430
1431      getParser().getStreamer().EmitValue(Value, Size);
1432
1433      if (getLexer().is(AsmToken::EndOfStatement))
1434        break;
1435
1436      if (getLexer().isNot(AsmToken::Comma))
1437        return Error(L, "unexpected token in directive");
1438      Parser.Lex();
1439    }
1440  }
1441
1442  Parser.Lex();
1443  return false;
1444}
1445
1446/// ParseDirectiveTC
1447///  ::= .tc [ symbol (, expression)* ]
1448bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1449  // Skip TC symbol, which is only used with XCOFF.
1450  while (getLexer().isNot(AsmToken::EndOfStatement)
1451         && getLexer().isNot(AsmToken::Comma))
1452    Parser.Lex();
1453  if (getLexer().isNot(AsmToken::Comma)) {
1454    Error(L, "unexpected token in directive");
1455    return false;
1456  }
1457  Parser.Lex();
1458
1459  // Align to word size.
1460  getParser().getStreamer().EmitValueToAlignment(Size);
1461
1462  // Emit expressions.
1463  return ParseDirectiveWord(Size, L);
1464}
1465
1466/// ParseDirectiveMachine (ELF platforms)
1467///  ::= .machine [ cpu | "push" | "pop" ]
1468bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1469  if (getLexer().isNot(AsmToken::Identifier) &&
1470      getLexer().isNot(AsmToken::String)) {
1471    Error(L, "unexpected token in directive");
1472    return false;
1473  }
1474
1475  StringRef CPU = Parser.getTok().getIdentifier();
1476  Parser.Lex();
1477
1478  // FIXME: Right now, the parser always allows any available
1479  // instruction, so the .machine directive is not useful.
1480  // Implement ".machine any" (by doing nothing) for the benefit
1481  // of existing assembler code.  Likewise, we can then implement
1482  // ".machine push" and ".machine pop" as no-op.
1483  if (CPU != "any" && CPU != "push" && CPU != "pop") {
1484    Error(L, "unrecognized machine type");
1485    return false;
1486  }
1487
1488  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1489    Error(L, "unexpected token in directive");
1490    return false;
1491  }
1492  PPCTargetStreamer &TStreamer =
1493      *static_cast<PPCTargetStreamer *>(
1494           getParser().getStreamer().getTargetStreamer());
1495  TStreamer.emitMachine(CPU);
1496
1497  return false;
1498}
1499
1500/// ParseDarwinDirectiveMachine (Mach-o platforms)
1501///  ::= .machine cpu-identifier
1502bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1503  if (getLexer().isNot(AsmToken::Identifier) &&
1504      getLexer().isNot(AsmToken::String)) {
1505    Error(L, "unexpected token in directive");
1506    return false;
1507  }
1508
1509  StringRef CPU = Parser.getTok().getIdentifier();
1510  Parser.Lex();
1511
1512  // FIXME: this is only the 'default' set of cpu variants.
1513  // However we don't act on this information at present, this is simply
1514  // allowing parsing to proceed with minimal sanity checking.
1515  if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1516    Error(L, "unrecognized cpu type");
1517    return false;
1518  }
1519
1520  if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1521    Error(L, "wrong cpu type specified for 64bit");
1522    return false;
1523  }
1524  if (!isPPC64() && CPU == "ppc64") {
1525    Error(L, "wrong cpu type specified for 32bit");
1526    return false;
1527  }
1528
1529  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1530    Error(L, "unexpected token in directive");
1531    return false;
1532  }
1533
1534  return false;
1535}
1536
1537/// Force static initialization.
1538extern "C" void LLVMInitializePowerPCAsmParser() {
1539  RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1540  RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1541  RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1542}
1543
1544#define GET_REGISTER_MATCHER
1545#define GET_MATCHER_IMPLEMENTATION
1546#include "PPCGenAsmMatcher.inc"
1547
1548// Define this matcher function after the auto-generated include so we
1549// have the match class enum definitions.
1550unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1551                                                  unsigned Kind) {
1552  // If the kind is a token for a literal immediate, check if our asm
1553  // operand matches. This is for InstAliases which have a fixed-value
1554  // immediate in the syntax.
1555  int64_t ImmVal;
1556  switch (Kind) {
1557    case MCK_0: ImmVal = 0; break;
1558    case MCK_1: ImmVal = 1; break;
1559    case MCK_2: ImmVal = 2; break;
1560    case MCK_3: ImmVal = 3; break;
1561    default: return Match_InvalidOperand;
1562  }
1563
1564  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1565  if (Op.isImm() && Op.getImm() == ImmVal)
1566    return Match_Success;
1567
1568  return Match_InvalidOperand;
1569}
1570
1571const MCExpr *
1572PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1573                                  MCSymbolRefExpr::VariantKind Variant,
1574                                  MCContext &Ctx) {
1575  switch (Variant) {
1576  case MCSymbolRefExpr::VK_PPC_LO:
1577    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1578  case MCSymbolRefExpr::VK_PPC_HI:
1579    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1580  case MCSymbolRefExpr::VK_PPC_HA:
1581    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1582  case MCSymbolRefExpr::VK_PPC_HIGHER:
1583    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1584  case MCSymbolRefExpr::VK_PPC_HIGHERA:
1585    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1586  case MCSymbolRefExpr::VK_PPC_HIGHEST:
1587    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1588  case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1589    return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1590  default:
1591    return nullptr;
1592  }
1593}
1594